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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,027 records · Page 57
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

Low cost high efficiency GaAs monolithic RF module for SARSAT distress beacons

Low cost high performance (5 Watts output) 406 MHz beacons are urgently needed to realize the maximum utilization of the Search and Rescue Satellite-Aided Tracking (SARSAT) system spearheaded in the U.S. by NASA. Although current technology can produce beacons meeting the output power requirement, power consumption is high due to the low efficiency of available transmitters. Field performance is currently unsatisfactory due to the lack of safe and reliable high density batteries capable of operation at -40 C. Low cost production is also a crucial but elusive requirement for the ultimate wide scale utilization of this system. Microwave Monolithics Incorporated (MMInc.) has proposed to make both the technical and cost goals for the SARSAT beacon attainable by developing a monolithic GaAs chip set for the RF module. This chip set consists of a high efficiency power amplifier and a bi-phase modulator. In addition to implementing the RF module in Monolithic Microwave Integrated Circuit (MMIC) form to minimize ultimate production costs, the power amplifier has a power-added efficiency nearly twice that attained with current commercial technology. A distress beacon built using this RF module chip set will be significantly smaller in size and lighter in weight due to a smaller battery requirement, since the 406 MHz signal source and the digital controller have far lower power consumption compared to the 5 watt power amplifier. All the program tasks have been successfully completed. The GaAs MMIC RF module chip set has been designed to be compatible with the present 406 MHz signal source and digital controller. A complete high performance low cost SARSAT beacon can be realized with only additional minor iteration and systems integration.

Petersen, W. C.↗
NASA NTRS1994

Hardware description languages

Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

Tucker, Jerry H.↗
DOE OSTI2025

Semiconductor-compatible topological digital alloys

Recently, GeSn alloys have attracted much interest for direct-gap infrared photonics and as potential topological materials which are compatible with the semiconductor industry. However, for photonics, the high-Sn content required leads to low detectivity, associated with poor material quality, and the (>35 %) Sn required for topological properties have been out of reach experimentally. Here, we demonstrate that by patterning the Sn distribution within Ge, the electronic properties have a far greater tunability than is possible with the random alloy. For the GeSn δ-digital alloy (DA) formed by confining Sn atoms in atomic layer(s) along the [111] direction of Ge, we show that ∼ 10 % Sn can lead to a triple-point semimetal. These findings are understood in terms of Sn ordering causing spatial separation of Sn and Ge band edges, leading to band inversion. This mechanism can also lead to a weak topological insulator, Weyl semimetal, and enables tunable direct bandgaps down to 2 meV, covering the entire infrared range. This DA induced topological properties are also identified in compound semiconductors, such as InAs 1-x Sb x , showing the general applicability of the DA design for realizing topological properties on conventional semiconductor platforms. Furthermore, our findings not only point to a new class of currently unexplored topological systems accessible by epitaxy, but also establish the promise of low-Sn GeSn DAs for application as infrared laser diodes and photodetectors in Si photonic integrated circuits and infrared image sensors.

3D topological semimetal↗
DOE OSTI2025

A virtual Frisch-grid geometry-based CZT gamma detector for in-field radioisotope identification

Here, we present a Virtual Frisch-Grid geometry-based CZT gamma detector developed for identifying different radioisotopes over an energy range from a few keV up to 2 MeV, and useful for efficient characterization of CZT crystals. The detector is built with a 3 x 3 matrix of CZT crystals, each measuring approximately 6 mm x 6 mm x 15 mm. The charge generated within the sensor’s active volume is read out via an anode connected directly to the AVG3_Dev integrated circuit. A current signal induced by charge drift is collected on side pads of the crystals, enabling reconstruction of a 3D interaction position. This paper discusses the design, development, and performance of the standalone, mobile detector system, which integrates the AVG3_Dev readout IC developed at Brookhaven National Laboratory, a high-speed FPGA-based with per-channel digital signal processing, and embedded system capabilities. The device is compact, battery-powered, and supports wireless data streaming, making it suitable for field operations for radioisotope identification.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Multi-channel front-end ASIC for a 3D position-sensitive detector

Arrays of 3D position-sensitive detectors (3DPSD), operating at room temperature and using cadmium zinc telluride (CZT) and thallium bromide (TIBr) sensors, are suitable for gamma-ray spectrometry in many applications. One detector configuration, the 3D position-sensitive Virtual Frisch-Grid detector (VFG), is particularly advantageous for integrating into large area arrays. The signals generated inside each detector of the array are captured with the anode, cathode and four pads that enable the reconstruction of the position and energy of the ionizing interaction by measurements of amplitude and timing of the signals. For these applications, a low-noise front-end ASIC has been developed, capable of processing bipolar signals (needed because of AC-coupling of certain electrodes). The ASIC can be coupled to an ADC in order to form a compound “waveform digitizer” capable of post-processing the analog signals and determining amplitude and timing information. This paper describes a 32-channel front-end ASIC that is suitable for reading out a 3 × 3 or 4 × 4 element matrix in the VFG configuration. Each channel is composed of a low-noise charge amplifier with an adaptive continuous reset feedback circuit suitable for both positive and negative charge, a first order shaper and a single-to-differential converter output stage. Voltage and current references are all internally generated by 10-bit DACs and the chip is fully controllable with the I 2 C communication protocol. The readout channel response has been verified using the implemented injection circuit. Linear behavior up to ~75 ke ± with the gain of ~80 mV/fC, and up to ~200 ke ± with the gain of ~30 mV/fC was demonstrated. In conclusion, the first test result waveforms using a 137 Cs radioactive source on a 5 × 5 × 12 mm 3 TIBr crystal are reported.

47 OTHER INSTRUMENTATION↗
NASA NTRS1998

FPGA Based Reconfigurable ATM Switch Test Bed

Various issues associated with "FPGA Based Reconfigurable ATM Switch Test Bed" are presented in viewgraph form. Specific topics include: 1) Network performance evaluation; 2) traditional approaches; 3) software simulation; 4) hardware emulation; 5) test bed highlights; 6) design environment; 7) test bed architecture; 8) abstract sheared-memory switch; 9) detailed switch diagram; 10) traffic generator; 11) data collection circuit and user interface; 12) initial results; and 13) the following conclusions: Advances in FPGA make hardware emulation feasible for performance evaluation, hardware emulation can provide several orders of magnitude speed-up over software simulation; due to the complexity of hardware synthesis process, development in emulation is much more difficult than simulation and requires knowledge in both networks and digital design.

Chu, Pong P.↗
NASA NTRS2010

NASA Tech Briefs, October 2010

Topics covered include: Hybrid Architecture Active Wavefront Sensing and Control; Carbon-Nanotube-Based Chemical Gas Sensor; Aerogel-Positronium Technology for the Detection of Small Quantities of Organic and/or Toxic Materials; Graphene-Based Reversible Nano-Switch/Sensor Schottky Diode; Inductive Non-Contact Position Sensor; High-Temperature Surface-Acoustic-Wave Transducer; Grid-Sphere Electrodes for Contact with Ionospheric Plasma; Enabling IP Header Compression in COTS Routers via Frame Relay on a Simplex Link; Ka-Band SiGe Receiver Front-End MMIC for Transponder Applications; Robust Optimization Design Algorithm for High-Frequency TWTs; Optimal and Local Connectivity Between Neuron and Synapse Array in the Quantum Dot/Silicon Brain; Method and Circuit for In-Situ Health Monitoring of Solar Cells in Space; BGen: A UML Behavior Network Generator Tool; Platform for Post-Processing Waveform-Based NDE; Electrochemical Hydrogen Peroxide Generator; Fabrication of Single, Vertically Aligned Carbon Nanotubes in 3D Nanoscale Architectures; Process to Create High-Fidelity Lunar Dust Simulants; Lithium-Ion Electrolytes Containing Phosphorous-Based, Flame-Retardant Additives; InGaP Heterojunction Barrier Solar Cells; Straight-Pore Microfilter with Efficient Regeneration; Determining Shear Stress Distribution in a Laminate; Self-Adjusting Liquid Injectors for Combustors; Handling Qualities Prediction of an F-16XL-Based Reduced Sonic Boom Aircraft; Tele-Robotic ATHLETE Controller for Kinematics - TRACK; Three-Wheel Brush-Wheel Sampler; Heterodyne Interferometer Angle Metrology; Aligning Astronomical Telescopes via Identification of Stars; Generation of Optical Combs in a WGM Resonator from a Bichromatic Pump; Large-Format AlGaN PIN Photodiode Arrays for UV Images; Fiber-Coupled Planar Light-Wave Circuit for Seed Laser Control in High Spectral Resolution Lidar Systems; On Calculating the Zero-Gravity Surface Figure of a Mirror; Optical Modification of Casimir Forces for Improved Function of Micro- and Nano-Scale Devices; Analysis, Simulation, and Verification of Knowledge-Based, Rule-Based, and Expert Systems; Core and Off-Core Processes in Systems Engineering; Digital Reconstruction Supporting Investigation of Mishaps; and Template Matching Approach to Signal Prediction.

Source record↗
NASA NTRS1991

Rendezvous radar for the orbital maneuvering vehicle

This paper describes the development of the Rendezvous Radar Set (RRS) for the Orbital Maneuvering Vehicle (OMV) for the National Aeronautics and Space Administration (NASA). The RRS was to be used to locate, and then provide vectoring information to, target satellites (or Shuttle or Space Station) to aid the OMV in making a minimum-fuel-consumption approach and rendezvous. The RRS design is that of an X-Band, all solid-state, monopulse tracking, frequency hopping, pulse-Doppler radar system. The development of the radar was terminated when the OMV prime contract to TRW was terminated by NASA. At the time of the termination, the development was in the circuit design stage. The system design was virtually completed, the PDR had been held. The RRS design was based on Motorola's experiences, both in the design and production of radar systems for the US Army and in the design and production of hi-rel communications systems for NASA space programs. Experience in these fields was combined with the latest digital signal processor and micro-processor technology to design a light-weight, low-power, spaceborne radar. The antenna and antenna positioner (gimbals) technology developed for the RRS is now being used in the satellite-to-satellite communication link design for Motorola's Iridium telecommunications system.

Locke, John W.↗
NASA NTRS2008

NASA Tech Briefs, August 2008

Customizable Digital Receivers for Radar Two-Camera Acquisition and Tracking of a Flying Target Visual Data Analysis for Satellites A Data Type for Efficient Representation of Other Data Types Hand-Held Ultrasonic Instrument for Reading Matrix Symbols Broadband Microstrip-to-Coplanar Strip Double-Y Balun A Topographical Lidar System for Terrain-Relative Navigation Programmable Low-Voltage Circuit Breaker and Tester Electronic Switch Arrays for Managing Microbattery Arrays Topics covered include: Lower-Dark-Current, Higher-Blue-Response CMOS Imagers; Fabricating Large-Area Sheets of Single-Layer Graphene by CVD; Support for Diagnosis of Custom Computer Hardware; Providing Goal-Based Autonomy for Commanding a Spacecraft; Dynamic Method for Identifying Collected Sample Mass; Optimal Planning and Problem-Solving; Attitude-Control Algorithm for Minimizing Maneuver Execution Errors; Grants Document-Generation System; Heat-Storage Modules Containing LiNO3 3H2O and Graphite Foam; Precipitation-Strengthened, High-Temperature, High-Force Shape Memory Alloys; Improved Relief Valve Would Be Less Susceptible to Failure; Safety Modification of Cam-and-Groove Hose Coupling; Using Composite Materials in a Cryogenic Pump; Using Electronic Noses to Detect Tumors During Neurosurgery; Producing Newborn Synchronous Mammalian Cells; Smaller, Lower-Power Fast-Neutron Scintillation Detectors; Rotationally Vibrating Electric-Field Mill; Estimating Hardness from the USDC Tool-Bit Temperature Rise; Particle-Charge Spectrometer; Automated Production of Movies on a Cluster of Computers; FIDO-Class Development Rover; and Tone-Based Command of Deep Space Probes Using Ground Antennas.

Source record↗
NASA NTRS2013

Compact Radar Transceiver with Included Calibration

The Digital Beamforming Synthetic Aperture Radar (DBSAR) is an eight-channel phased array radar system that employs solid-state radar transceivers, a microstrip patch antenna, and a reconfigurable waveform generator and processor unit. The original DBSAR transceiver design utilizes connectorized electronic components that tend to be physically large and heavy. To achieve increased functionality in a smaller volume, PCB (printed circuit board) transceivers were designed to replace the large connectorized transceivers. One of the most challenging problems designing the transceivers in a PCB format was achieving proper performance in the calibration path. For a radar loop-back calibration path, a portion of the transmit signal is coupled out of the antenna feed and fed back into the receiver. This is achieved using passive components for stability and repeatability. Some signal also leaks through the receive path. As these two signal paths are correlated via an unpredictable phase, the leakage through the receive path during transmit must be 30 dB below the calibration path. For DBSAR s design, this requirement called for a 100-dB isolation in the receiver path during transmit. A total of 16 solid-state L-band transceivers on a PCB format were designed. The transceivers include frequency conversion stages, T/R switching, and a calibration path capable of measuring the transmit power-receiver gain product during transmit for pulse-by-pulse calibration or matched filtering. In particular, this calibration path achieves 100-dB isolation between the transmitted signal and the low-noise amplifier through the use of a switching network and a section of physical walls achieving attenuation of radiated leakage. The transceivers were designed in microstrip PCBs with lumped elements and individually packaged components for compactness. Each transceiver was designed on a single PCB with a custom enclosure providing interior walls and compartments to isolate transceiver subsystems from radiated interference. The enclosure also acts as a heat sink for the voltage regulators and power amplifiers inside the system. The PCB transceiver design produces transmit pulses of 2 W with an arbitrary duty cycle. Each transceiver is fed by an external 120-MHz signal transmit and two 1,140-MHz local oscillator signals. The received signal is amplified and down-converted to 120 MHz and is fed to the data processor. The transceiver dimensions are approximately 3.5 11.5 0.6 in. (9 29 1.5 cm). The PCB transceiver design reduces the volume and weight of the DBSAR instrument while maintaining the functionality found in the original design. Both volume and weight are critical for airborne and flight remote sensing instrumentation.

McLinden, Matthew↗
DOE OSTI2026

Realization of fermionic Laughlin state on a quantum processor

Strongly correlated topological phases of matter are central to modern condensed matter physics and quantum information technology but often challenging to probe and control in material systems. The experimental difficulty of accessing these phases has motivated the use of engineered quantum platforms for simulation and manipulation of exotic topological states. Among these, the Laughlin state stands as a cornerstone for topological matter, embodying fractionalization, anyonic excitations, and incompressibility. Although its bosonic analogs have been realized on programmable quantum simulators, a genuine fermionic Laughlin state has yet to be demonstrated on a quantum processor. Here, we realize the ν = 1/3 fermionic Laughlin state on IonQ’s trapped-ion quantum computer using an efficient and scalable Hamiltonian variational ansatz with 369 two-qubit gates on a 16-qubit circuit. Employing symmetry-verification error mitigation, we extract key observables that characterize the Laughlin state, including correlation hole, bulk-edge correspondence, and topological entanglement entropy, with strong agreement to exact diagonalization benchmarks. This work demonstrates an end-to-end workflow to simulate material-intrinsic topological orders and provides a starting point to explore its dynamics and excitations on digital quantum processors.

Shen, Lingnan [Univ. of Washington, Seattle, WA (U↗
NASA NTRS1973

Analysis and synthesis of distributed-lumped-active networks by digital computer

The use of digital computational techniques in the analysis and synthesis of DLA (distributed lumped active) networks is considered. This class of networks consists of three distinct types of elements, namely, distributed elements (modeled by partial differential equations), lumped elements (modeled by algebraic relations and ordinary differential equations), and active elements (modeled by algebraic relations). Such a characterization is applicable to a broad class of circuits, especially including those usually referred to as linear integrated circuits, since the fabrication techniques for such circuits readily produce elements which may be modeled as distributed, as well as the more conventional lumped and active ones.

Source record↗
DOE OSTI2022

Waveform processing using neural network algorithms on the front-end electronics

In a multi-channel radiation detector readout system, waveform sampling, digitization, and raw data transmission to the data acquisition system constitute a conventional processing chain. The deposited energy on the sensor is estimated by extracting peak amplitudes, area under pulse envelopes from the raw data, and starting times of signals or time of arrivals. However, such quantities can be estimated using machine learning algorithms on the front-end Application-Specific Integrated Circuits (ASICs), often termed as “edge computing”. Edge computation offers enormous benefits, especially when the analytical forms are not fully known or the registered waveform suffers from noise and imperfections of practical implementations. In this work, we aim to predict peak amplitude from a single waveform snippet whose rising and falling edges containing only 3 to 4 samples. We thoroughly studied two well-accepted neural network algorithms, Multi-Layer Perceptron (MLP) and Convolutional Neural Network (CNN) by varying their model sizes. Further, to better fit front-end electronics, neural network model reduction techniques, such as network pruning methods and variable-bit quantization approaches, were also studied. By combining pruning and quantization, our best performing model has the size of 1.5 KB, reduced from 16.6 KB of its full model counterpart. It can reach mean absolute error of 0.034 comparing to that of a naive baseline of 0.135. Such parameter-efficient and predictive neural network models established feasibility and practicality of their deployment on front-end ASICs.

47 OTHER INSTRUMENTATION↗
NASA NTRS1976

Rapid and precise measurement of flatband voltage

The paper outlines the design, principles of operation, and calibration of a five-IC network intended to give a rapid, precise, and automatic determination of the flatband voltage of MOS capacitors. The basic principle of measurement is to compare the analog output voltage of a capacitance meter - which is directly proportional to the capacitance being measured - with a preset or dialed-in voltage proportional to the calculated flatband capacitance by means of a comparator circuit. The bias to the MOS capacitor supplied through the capacitance meter is provided by a ramp voltage going from a negative toward a positive voltage level and vice versa. The network employs two monostable multivibrators for reading and recording the flatband voltage and for resetting the initial conditions and restarting the ramp. The flatband voltage can be held and read on a digital voltmeter.

Li, S. P.↗
NASA NTRS2000

Development of a Two Dimensional Synthetic Aperture Radiometer at L-Band

A radiometer that uses aperture synthesis in two dimensions is being built as part of research under NASA's Instrument Incubator Program. The instrument development team consists of engineers at the Goddard Space Flight Center, the University of Massachusetts and Quadrant Engineering. This will be an aircraft instrument operating at L-band which builds on the heritage of ESTAR. The choice of L-band was made because the problem of achieving adequate resolution in space is most critical at this wavelength and because a polarimetric, conical scanning airborne radiometer for future experiments to validate soil moisture and ocean salinity retrieval algorithms is not currently available. The instrument will be designed to fly on the NASA P-3 aircraft in a nadir pointing mode, although other options are possible. The antenna will consist of an array of modules arranged in a rectangular grid. Each module will be comprised of a printed circuit dual-polarized patch and integrated receiver. The distribution of modules within the rectangular array will be adjustable so that several different imaging configurations (e.g. "+","Y", "T") can be employed. The integrated receiver will provide amplification and conversion to IF. The IF signal will be routed to a processor where the required correlations performed. The I and Q channels will be created digitally and the correlations will be done digitally in this processor. The digitization will be done with sufficient bits to study the effects of quantization on radiometer performance. A computer/controller will store the data for conversion to an image and will also perform temperature control and other data interfacing and housekeeping tasks. The instrument is currently in the bread boarding phase of development. A design of the critical components has been completed and hardware is being assembled to test the individual elements. It is expected that a complete 2-channel correlator will be tested by the summer of 2000 and that the complete instrument will be ready for flight tests the following summer (2001).

LeVine, D. M.↗
NASA NTRS1995

Low Temperature Performance of High-Speed Neural Network Circuits

Artificial neural networks, derived from their biological counterparts, offer a new and enabling computing paradigm specially suitable for such tasks as image and signal processing with feature classification/object recognition, global optimization, and adaptive control. When implemented in fully parallel electronic hardware, it offers orders of magnitude speed advantage. Basic building blocks of the new architecture are the processing elements called neurons implemented as nonlinear operational amplifiers with sigmoidal transfer function, interconnected through weighted connections called synapses implemented using circuitry for weight storage and multiply functions either in an analog, digital, or hybrid scheme.

artificial neural networks image processing signal↗
DOE OSTI2026

Characterization of Digital Silicon Photomultipliers

Digital Silicon photomultipliers (Digital SiPMs) have become an increasingly viable option for single-photon detection due to their compact size and precise timing and resolution. The following work characterizes the noise performance of a diSiPM designed and tested in-house at Fermilab. The SiPM consists of a 26x32 array of single-photon avalanche diode (SPAD) cells. Through the implementation of a shift register masking circuit, individual SPAD cells can be enabled and disabled at will, allowing for precise detection measurements of single columns (accumulator channels) and cells. The provided circuit design operates on voltage clock pulses and collects data on clock edges allowing for precise tuning of the data collection process by varying the clock frequency, pulse width, and integration period.

Shoemaker, Oliver [U. Chicago (main)]↗
NASA NTRS1991

Aid For Simulating Digital Flight Control Systems

DIVERS translator is computer program to convert descriptions of digital flight-control systems (DFCS) into computer program. Language developed to represent design charts of DFCS. Translator converts DIVERS source code into easily transportable language, while minimizing probability that results are affected by interpretation of programmer. Final translated program used as standard of comparison to verify operation of actual flight-control systems. Applicable to simulation of other control systems; for example, electrical circuits and logic processes. Written in C.

Hartman, Richard M.↗