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Two-Photon-Absorption Scheme for Optical Beam Tracking

A new optical beam tracking approach for free-space optical communication links using two-photon absorption (TPA) in a high-bandgap detector material was demonstrated. This tracking scheme is part of the canonical architecture described in the preceding article. TPA is used to track a long-wavelength transmit laser while direct absorption on the same sensor simultaneously tracks a shorter-wavelength beacon. The TPA responsivity was measured for silicon using a PIN photodiode at a laser beacon wavelength of 1,550 nm. As expected, the responsivity shows a linear dependence with incident power level. The responsivity slope is 4.5 x 10(exp -7) A/W2. Also, optical beam spots from the 1,550-nm laser beacon were characterized on commercial charge coupled device (CCD) and complementary metal-oxide semiconductor (CMOS) imagers with as little as 13.7 microWatts of optical power (see figure). This new tracker technology offers an innovative solution to reduce system complexity, improve transmit/receive isolation, improve optical efficiency, improve signal-to-noise ratio (SNR), and reduce cost for free-space optical communications transceivers.

Ortiz, Gerardo G.↗

NASA Tech Briefs, April 2002

The contents include: 1) Application Briefs; 2) Sneak Preview of Sensors Expo; 3) The Complexity of the Diagnosis Problem; 4) Design Concepts for the ISS TransHab Module; 5) Characteristics of Supercritical Transitional Mixing Layers; 6) Electrometer for Triboelectric Evaluation of Materials; 7) Infrared CO2 Sensor With Built-In Calibration Chambers; 8) Solid-State Potentiometric CO Sensor; 9) Planetary Rover Absolute Heading Detection Using a Sun Sensor; 10) Concept for Utilizing Full Areas of STJ Photodetector Arrays; 11) Development of Cognitive Sensors; 12) Enabling Higher-Voltage Operation of SOl CMOS Transistors; 13) Estimating Antenna-Pointing Errors From Beam Squints; 14) Advanced-Fatigue-Crack-Growth and Fracture- Mechanics Program; 15) Software for Sequencing Spacecraft Actions; 16) Program Distributes and Tracks Organizational Memoranda; 16) Flat Membrane Device for Dehumidification of Air; 17) Inverted Hindle Mount Reduces Sag of a Large, Precise Mirror; 18) Heart-Pump-Outlet/Cannula Coupling; 19) Externally Triggered Microcapsules Release Drugs In Situ; 20) Combinatorial Drug Design Augmented by Information Theory; 21) Multiple-Path-Length Optical Absorbance Cell; 22) Model of a Fluidized Bed Containing a Mixture of Particles; 23) Refractive Secondary Concentrators for Solar Thermal Systems; 24) Cold Flow Calorimeter; 25) Methodology for Tracking Hazards and Predicting Failures; 26) Estimating Heterodyne-Interferometer Polarization Leakage; 27) An Efficient Algorithm for Propagation of Temporal- Constraint Networks; 28) Software for Continuous Replanning During Execution; 29) Surface-Launched Explorers for Reconnaissance/Scouting; 30) Firmware for a Small Motion-Control Processor; 31) Gear Bearings and Gear-Bearing Transmissions; and 32) Linear Dynamometer With Variable Stroke and Frequency.

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Performance of the Micropower Voltage Reference ADR3430 Under Extreme Temperatures

Electronic systems designed for use in space exploration systems are expected to be exposed to harsh temperatures. For example, operation at cryogenic temperatures is anticipated in space missions such as polar craters of the moon (-223 C), James Webb Space Telescope (-236 C), Mars (-140 C), Europa (-223 C), Titan (-178 C), and other deep space probes away from the sun. Similarly, rovers and landers on the lunar surface, and deep space probes intended for the exploration of Venus are expected to encounter high temperature extremes. Electronics capable of operation under extreme temperatures would not only meet the requirements of future spacebased systems, but would also contribute to enhancing efficiency and improving reliability of these systems through the elimination of the thermal control elements that present electronics need for proper operation under the harsh environment of space. In this work, the performance of a micropower, high accuracy voltage reference was evaluated over a wide temperature range. The Analog Devices ADR3430 chip uses a patented voltage reference architecture to achieve high accuracy, low temperature coefficient, and low noise in a CMOS process [1]. The device combines two voltages of opposite temperature coefficients to create an output voltage that is almost independent of ambient temperature. It is rated for the industrial temperature range of -40 C to +125 C, and is ideal for use in low power precision data acquisition systems and in battery-powered devices. Table 1 shows some of the manufacturer s device specifications.

Patterson, Richard L.↗

NASA Tech Briefs, April 2011

Topics covered include: Amperometric Solid Electrolyte Oxygen Microsensors with Easy Batch Fabrication; Two-Axis Direct Fluid Shear Stress Sensor for Aerodynamic Applications; Target Assembly to Check Boresight Alignment of Active Sensors; Virtual Sensor Test Instrumentation; Evaluation of the Reflection Coefficient of Microstrip Elements for Reflectarray Antennas; Miniaturized Ka-Band Dual-Channel Radar; Continuous-Integration Laser Energy Lidar Monitor; Miniaturized Airborne Imaging Central Server System; Radiation-Tolerant, SpaceWire-Compatible Switching Fabric; Small Microprocessor for ASIC or FPGA Implementation; Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters; High-Voltage-Input Level Translator Using Standard CMOS; Monitoring Digital Closed-Loop Feedback Systems; MASCOT - MATLAB Stability and Control Toolbox; MIRO Continuum Calibration for Asteroid Mode; GOATS Image Projection Component; Coded Modulation in C and MATLAB; Low-Dead-Volume Inlet for Vacuum Chamber; Thermal Control Method for High-Current Wire Bundles by Injecting a Thermally Conductive Filler; Method for Selective Cleaning of Mold Release from Composite Honeycomb Surfaces; Infrared-Bolometer Arrays with Reflective Backshorts; Commercialization of LARC (trade mark) -SI Polyimide Technology; Novel Low-Density Ablators Containing Hyperbranched Poly(azomethine)s; Carbon Nanotubes on Titanium Substrates for Stray Light Suppression; Monolithic, High-Speed Fiber-Optic Switching Array for Lidar; Grid-Tied Photovoltaic Power System; Spectroelectrochemical Instrument Measures TOC; A Miniaturized Video System for Monitoring Drosophila Behavior; Hydrofocusing Bioreactor Produces Anti-Cancer Alkaloids; Creep Measurement Video Extensometer; Radius of Curvature Measurement of Large Optics Using Interferometry and Laser Tracker n-B-pi-p Superlattice Infrared Detector; Safe Onboard Guidance and Control Under Probabilistic Uncertainty; General Tool for Evaluating High-Contrast Coronagraphic Telescope Performance Error Budgets; Hidden Statistics of Schroedinger Equation; Optimal Padding for the Two-Dimensional Fast Fourier Transform; Spatial Query for Planetary Data; Higher Order Mode Coupling in Feed Waveguide of a Planar Slot Array Antenna; Evolutionary Computational Methods for Identifying Emergent Behavior in Autonomous Systems; Sampling Theorem in Terms of the Bandwidth and Sampling Interval; Meteoroid/Orbital Debris Shield Engineering Development Practice and Procedure; Self-Balancing, Optical-Center-Pivot, Fast-Steering Mirror; Wireless Orbiter Hang-Angle Inclinometer System; and Internal Electrostatic Discharge Monitor - IESDM.

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A Miniaturized Video System for Monitoring Drosophila Behavior

Long-term spaceflight may induce a variety of harmful effects in astronauts, resulting in altered motor and cognitive behavior. The stresses experienced by humans in space - most significantly weightlessness (microgravity) and cosmic radiation - are difficult to accurately simulate on Earth. In fact, prolonged and concomitant exposure to microgravity and cosmic radiation can only be studied in space. Behavioral studies in space have focused on model organisms, including Drosophila melanogaster. Drosophila is often used due to its short life span and generational cycle, small size, and ease of maintenance. Additionally, the well-characterized genetics of Drosophila behavior on Earth can be applied to the analysis of results from spaceflights, provided that the behavior in space is accurately recorded. In 2001, the BioExplorer project introduced a low-cost option for researchers: the small satellite. While this approach enabled multiple inexpensive launches of biological experiments, it also imposed stringent restrictions on the monitoring systems in terms of size, mass, data bandwidth, and power consumption. Suggested parameters for size are on the order of 100 mm3 and 1 kg mass for the entire payload. For Drosophila behavioral studies, these engineering requirements are not met by commercially available systems. One system that does meet many requirements for behavioral studies in space is the actimeter. Actimeters use infrared light gates to track the number of times a fly crosses a boundary within a small container (3x3x40 mm). Unfortunately, the apparatus needed to monitor several flies at once would be larger than the capacity of the small satellite. A system is presented, which expands on the actimeter approach to achieve a highly compact, low-power, ultra-low bandwidth solution for simultaneous monitoring of the behavior of multiple flies in space. This also provides a simple, inexpensive alternative to the current systems for monitoring Drosophila populations in terrestrial experiments, and could be especially useful in field experiments in remote locations. Two practical limitations of the system should be noted: first, only walking flies can be observed - not flying - and second, although it enables population studies, tracking individual flies within the population is not currently possible. The system used video recording and an analog circuit to extract the average light changes as a function of time. Flies were held in a 5-cm diameter Petri dish and illuminated from below by a uniform light source. A miniature, monochrome CMOS (complementary metal-oxide semiconductor) video camera imaged the flies. This camera had automatic gain control, and this did not affect system performance. The camera was positioned 5-7 cm above the Petri dish such that the imaging area was 2.25 sq cm. With this basic setup, still images and continuous video of 15 flies at one time were obtained. To reduce the required data bandwidth by several orders of magnitude, a band-pass filter (0.3-10 Hz) circuit compressed the video signal and extracted changes in image luminance over time. The raw activity signal output of this circuit was recorded on a computer and digitally processed to extract the fly movement "events" from the waveform. These events corresponded to flies entering and leaving the image and were used for extracting activity parameters such as inter-event duration. The efficacy of the system in quantifying locomotor activity was evaluated by varying environmental temperature, then measuring the activity level of the flies.

Bhattacharya, Sharmila↗

NASA Tech Briefs, February 2011

Topics covered include: Multi-Segment Radius Measurement Using an Absolute Distance Meter Through a Null Assembly; Fiber-Optic Magnetic-Field-Strength Measurement System for Lightning Detection; Photocatalytic Active Radiation Measurements and Use; Computer Generated Hologram System for Wavefront Measurement System Calibration; Non-Contact Thermal Properties Measurement with Low-Power Laser and IR Camera System; SpaceCube 2.0: An Advanced Hybrid Onboard Data Processor; CMOS Imager Has Better Cross-Talk and Full-Well Performance; High-Performance Wireless Telemetry; Telemetry-Based Ranging; JWST Wavefront Control Toolbox; Java Image I/O for VICAR, PDS, and ISIS; X-Band Acquisition Aid Software; Antimicrobial-Coated Granules for Disinfecting Water; Range 7 Scanner Integration with PaR Robot Scanning System; Methods of Antimicrobial Coating of Diverse Materials; High-Operating-Temperature Barrier Infrared Detector with Tailorable Cutoff Wavelength; A Model of Reduced Kinetics for Alkane Oxidation Using Constituents and Species for N-Heptane; Thermally Conductive Tape Based on Carbon Nanotube Arrays; Two Catalysts for Selective Oxidation of Contaminant Gases; Nanoscale Metal Oxide Semiconductors for Gas Sensing; Lightweight, Ultra-High-Temperature, CMC-Lined Carbon/Carbon Structures; Sample Acquisition and Handling System from a Remote Platform; Improved Rare-Earth Emitter Hollow Cathode; High-Temperature Smart Structures for Engine Noise Reduction and Performance Enhancement; Cryogenic Scan Mechanism for Fourier Transform Spectrometer; Piezoelectric Rotary Tube Motor; Thermoelectric Energy Conversion Technology for High-Altitude Airships; Combustor Computations for CO2-Neutral Aviation; Use of Dynamic Distortion to Predict and Alleviate Loss of Control; Cycle Time Reduction in Trapped Mercury Ion Atomic Frequency Standards; and A (201)Hg+ Comagnetometer for (199)Hg+ Trapped Ion Space Atomic Clocks.

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Multifunctional Logic Gate Controlled by Temperature

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Stoica, Adrian↗

Multifunctional Logic Gate Controlled by Supply Voltage

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Stoica, Adrian↗

Radiation Status of Sub-65 nm Electronics

Ultra-scaled complementary metal oxide semiconductor (CMOS) includes commercial foundry capabilities at and below the 65 nm technology node Radiation evaluations take place using standard products and test characterization vehicles (memories, logic/latch chains, etc.) NEPP focus is two-fold: (1) Conduct early radiation evaluations to ascertain viability for future NASA missions (i.e. leverage commercial technology development). (2) Uncover gaps in current testing methodologies and mechanism comprehension -- early risk mitigation.

Pellish, Jonathan A.↗

Modeling of SONOS Memory Cell Erase Cycle

Utilization of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile semiconductor memories as a flash memory has many advantages. These electrically erasable programmable read-only memories (EEPROMs) utilize low programming voltages, have a high erase/write cycle lifetime, are radiation hardened, and are compatible with high-density scaled CMOS for low power, portable electronics. In this paper, the SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. Comparisons were made between the model predictions and experimental data.

Phillips, Thomas A.↗

Parallel-Processing Equalizers for Multi-Gbps Communications

Architectures have been proposed for the design of frequency-domain least-mean-square complex equalizers that would be integral parts of parallel- processing digital receivers of multi-gigahertz radio signals and other quadrature-phase-shift-keying (QPSK) or 16-quadrature-amplitude-modulation (16-QAM) of data signals at rates of multiple gigabits per second. Equalizers as used here denotes receiver subsystems that compensate for distortions in the phase and frequency responses of the broad-band radio-frequency channels typically used to convey such signals. The proposed architectures are suitable for realization in very-large-scale integrated (VLSI) circuitry and, in particular, complementary metal oxide semiconductor (CMOS) application- specific integrated circuits (ASICs) operating at frequencies lower than modulation symbol rates. A digital receiver of the type to which the proposed architecture applies (see Figure 1) would include an analog-to-digital converter (A/D) operating at a rate, fs, of 4 samples per symbol period. To obtain the high speed necessary for sampling, the A/D and a 1:16 demultiplexer immediately following it would be constructed as GaAs integrated circuits. The parallel-processing circuitry downstream of the demultiplexer, including a demodulator followed by an equalizer, would operate at a rate of only fs/16 (in other words, at 1/4 of the symbol rate). The output from the equalizer would be four parallel streams of in-phase (I) and quadrature (Q) samples.

Gray, Andrew↗

NASA Tech Briefs, July 2004

Topics: Optoelectronic Sensor System for Guidance in Docking; Hybrid Piezoelectric/Fiber-Optic Sensor Sheets; Multisensor Arrays for Greater Reliability and Accuracy; Integrated-Optic Oxygen Sensors; Ka-Band Autonomous Formation Flying Sensor; CMOS VLSI Active-Pixel Sensor for Tracking; Lightweight, Self-Deploying Foam Antenna Structures; Electrically Small Microstrip Quarter-Wave Monopole Antennas; A 2-to-28-MHz Phase-Locked Loop; Portable Electromyograph; Open-Source Software for Modeling of Nanoelectronic Devices; Software for Generating Strip Maps from SAR Data; Calibration Software for use with Jurassicprok; Software for Probabilistic Risk Reduction; Software Processes SAR Motion-Measurement Data; Improved Method of Purifying Carbon Nanotubes; Patterned Growth of Carbon Nanotubes or Nanofibers; Lightweight, Rack-Mountable Composite Cold Plate/Shelves; SiC-Based Miniature High-Temperature Cantilever Anemometer; Inlet Housing for a Partial-Admission Turbine; Lightweight Thermoformed Structural Components and Optics; Growing High-Quality InAs Quantum Dots for Infrared Lasers; Selected Papers on Protoplanetary Disks; Module for Oxygenating Water without Generating Bubbles; Coastal Research Imaging Spectrometer; Rapid Switching and Modulation by use of Coupled VCSELs; Laser-Induced-Fluorescence Photogrammetry and Videogrammetry; Laboratory Apparatus Generates Dual-Species Cold Atomic Beam; Laser Ablation of Materials for Propulsion of Spacecraft; Small Active Radiation Monitor; Hybrid Image-Plane/Stereo Manipulation; Partitioning a Gridded Rectangle into Smaller Rectangles; Digital Radar-Signal Processors Implemented in FPGAs; Part 1 of a Computational Study of a Drop-Laden Mixing Layer; and Some Improvements in Signal-Conditioning Circuits.

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Wide Range SET Pulse Measurement

A method for measuring a wide range of SET pulses is demonstrated. Use of dynamic logic, faster than ordinary CMOS, allows capture of short pulses. A weighted binning of SET lengths allows measurement of a wide range of pulse lengths with compact circuitry. A pulse-length-conservative pulse combiner tree routes SETs from combinational logic to the measurement circuit, allowing SET measurements in circuits that cannot easily be arranged in long chains. The method is applied to add-multiplex combinational logic, and to an array of NFET routing switches, at .35 micron. Pulses are captured in a chain of Domino Logic AND gates. Propagation through the chain is frozen on the trailing edge by dropping low the second "enable" input to the AND gates. Capacitive loading is increased in the latter stages to create an approximately logarithmic weighted binning, so that a broad range of pulse lengths can be captured with a 10 stage capture chain. Simulations show pulses can be captured which are 1/5th the length of those typically captured with leading edge triggered latch methods, and less than the length of those captured with a trailing edge latch method. After capture, the pulse pattern is transferred to an SEU protected shift register for readout. 64 instances of each of two types of logic are used as targets. One is a full adder with a 4 to 1 mux on its inputs. The other is a 4 x 4 NFET routing matrix. The outputs are passed through buffered XNOR comparators to identify pulses, which are merged in a buffered not-nand (OR) tree designed to avoid pulse absorption as much as possible. The output from each of the two test circuits are input into separate pulse measurement circuits. Test inputs were provided so that the circuit could be bench tested and calibrated. A third SET measurement circuit with no inputs was used to judge the contribution from direct hits on the measurement circuit. Heavy ions were used with an LET range from 12 to 176. At LET of 21 and below, the very small number of SETs were not significantly higher in the test over the control circuits. At higher LET the test circuit SETs are one or two orders of magnitude greater than for the control circuit. The NFET circuit produces more and slightly longer SETs as expected. But the differences do not appear to be significant enough to modify strategies now used to avoid capture of SETs in chips such as FPGAs. Complete data and graphs will be in the full paper / presentation. In the summary figure below left, NOCL is the reference circuit without any input, and number of stages triggered is plotted. Simulation at right shows the smallest pulse captured (stage 2) at about 300 ps. Our conclusion is that the method is promising, but that improvements in the merge network are desirable before applying in a deep submicron process

Shuler, Robert L.↗

Architecture for a 1-GHz Digital RADAR

An architecture for a Direct RF-digitization Type Digital Mode RADAR was developed at GSFC in 2008. Two variations of a basic architecture were developed for use on RADAR imaging missions using aircraft and spacecraft. Both systems can operate with a pulse repetition rate up to 10 MHz with 8 received RF samples per pulse repetition interval, or at up to 19 kHz with 4K received RF samples per pulse repetition interval. The first design describes a computer architecture for a Continuous Mode RADAR transceiver with a real-time signal processing and display architecture. The architecture can operate at a high pulse repetition rate without interruption for an infinite amount of time. The second design describes a smaller and less costly burst mode RADAR that can transceive high pulse repetition rate RF signals without interruption for up to 37 seconds. The burst-mode RADAR was designed to operate on an off-line signal processing paradigm. The temporal distribution of RF samples acquired and reported to the RADAR processor remains uniform and free of distortion in both proposed architectures. The majority of the RADAR's electronics is implemented in digital CMOS (complementary metal oxide semiconductor), and analog circuits are restricted to signal amplification operations and analog to digital conversion. An implementation of the proposed systems will create a 1-GHz, Direct RF-digitization Type, L-Band Digital RADAR--the highest band achievable for Nyquist Rate, Direct RF-digitization Systems that do not implement an electronic IF downsample stage (after the receiver signal amplification stage), using commercially available off-the-shelf integrated circuits.

Mallik, Udayan↗

Rad-Hard, Miniaturized, Scalable, High-Voltage Switching Module for Power Applications Rad-Hard, Miniaturized

A paper discusses the successful development of a miniaturized radiation hardened high-voltage switching module operating at 2.5 kV suitable for space application. The high-voltage architecture was designed, fabricated, and tested using a commercial process that uses a unique combination of 0.25 micrometer CMOS (complementary metal oxide semiconductor) transistors and high-voltage lateral DMOS (diffusion metal oxide semiconductor) device with high breakdown voltage (greater than 650 V). The high-voltage requirements are achieved by stacking a number of DMOS devices within one module, while two modules can be placed in series to achieve higher voltages. Besides the high-voltage requirements, a second generation prototype is currently being developed to provide improved switching capabilities (rise time and fall time for full range of target voltages and currents), the ability to scale the output voltage to a desired value with good accuracy (few percent) up to 10 kV, to cover a wide range of high-voltage applications. In addition, to ensure miniaturization, long life, and high reliability, the assemblies will require intensive high-voltage electrostatic modeling (optimized E-field distribution throughout the module) to complete the proposed packaging approach and test the applicability of using advanced materials in a space-like environment (temperature and pressure) to help prevent potential arcing and corona due to high field regions. Finally, a single-event effect evaluation would have to be performed and single-event mitigation methods implemented at the design and system level or developed to ensure complete radiation hardness of the module.

Adell, Philippe C.↗

Analog bus driver and multiplexer

For a source-follower signal chain, the ohmic drop in the selection switch causes unacceptable voltage offset, non-linearity, and reduced small signal gain. For an op amp signal chain, the required bias current and the output noise rises rapidly with increasing the array format due to a rapid increase in the effective capacitance caused by the Miller effect boosting up the contribution of the bus capacitance. A new switched source-follower signal chain circuit overcomes limitations of existing op-amp based or source follower based circuits used in column multiplexers and data readout. This will improve performance of CMOS imagers, and focal plane read-out integrated circuits for detectors of infrared or ultraviolet light.

Pain, Bedabrata↗

Coupling Between Microstrip Lines and Finite Ground Coplanar Lines Embedded in Polyimide Layers for 3D-MMICs on Silicon

Three-dimensional circuits built upon multiple layers of polyimide are required for constructing Si/SiGe monolithic microwave/mm-wave integrated circuits on CMOS (low resistivity) Si wafers. It is expected that these circuits will replace the ones fabricated on GaAs and reduce the overall system cost. However, the closely spaced transmission lines that are required for a high-density circuit environment are susceptible to high levels of cross-coupling, which degrades the overall circuit performance. In this paper, theoretical and experimental results on coupling and ways to reduce it are presented for two types of transmission lines: a) the microstrip line and b) the Finite Ground Coplanar (FGC) line. For microstrip lines it is shown that a fence of metalized via-holes can significantly reduce coupling, especially in the case when both lines are on the same polyimide layer or when the shielding structure extends through several polyimide layers. For closely spaced microstrip lines, coupling is lower for a metal filled trench shield than a via-hole fence. Coupling amongst microstrip lines is dependent on the ratio of line separation to polyimide thickness and is primarily due to magnetic fields. For FGC lines it is shown that they have in general low coupling that can be reduced significantly when there is even a small gap between the ground planes of each line. FGC lines have approximately 8 dB lower coupling than coupled coplanar waveguides (CPW). In addition, forward and backward characteristics of the FGC lines do not resemble those of other transmission lines such as microstrip. Therefore, the coupling mechanism of the FGC lines is different compared to thin film microstrip lines.

Ponchak, G. E.↗

Downsampling Photodetector Array with Windowing

In a photon counting detector array, each pixel in the array produces an electrical pulse when an incident photon on that pixel is detected. Detection and demodulation of an optical communication signal that modulated the intensity of the optical signal requires counting the number of photon arrivals over a given interval. As the size of photon counting photodetector arrays increases, parallel processing of all the pixels exceeds the resources available in current application-specific integrated circuit (ASIC) and gate array (GA) technology; the desire for a high fill factor in avalanche photodiode (APD) detector arrays also precludes this. Through the use of downsampling and windowing portions of the detector array, the processing is distributed between the ASIC and GA. This allows demodulation of the optical communication signal incident on a large photon counting detector array, as well as providing architecture amenable to algorithmic changes. The detector array readout ASIC functions as a parallel-to-serial converter, serializing the photodetector array output for subsequent processing. Additional downsampling functionality for each pixel is added to this ASIC. Due to the large number of pixels in the array, the readout time of the entire photodetector is greater than the time between photon arrivals; therefore, a downsampling pre-processing step is done in order to increase the time allowed for the readout to occur. Each pixel drives a small counter that is incremented at every detected photon arrival or, equivalently, the charge in a storage capacitor is incremented. At the end of a user-configurable counting period (calculated independently from the ASIC), the counters are sampled and cleared. This downsampled photon count information is then sent one counter word at a time to the GA. For a large array, processing even the downsampled pixel counts exceeds the capabilities of the GA. Windowing of the array, whereby several subsets of pixels are designated for processing, is used to further reduce the computational requirements. The grouping of the designated pixel frame as the photon count information is sent one word at a time to the GA, the aggregation of the pixels in a window can be achieved by selecting only the designated pixel counts from the serial stream of photon counts, thereby obviating the need to store the entire frame of pixel count in the gate array. The pixel count se quence from each window can then be processed, forming lower-rate pixel statistics for each window. By having this processing occur in the GA rather than in the ASIC, future changes to the processing algorithm can be readily implemented. The high-bandwidth requirements of a photon counting array combined with the properties of the optical modulation being detected by the array present a unique problem that has not been addressed by current CCD or CMOS sensor array solutions.

Patawaran, Ferze D.↗