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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,009 records · Page 56
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Local structure effects of carbon-doping on the phase change material Ge 2 Sb 2 Te 5

Ge 2 Sb 2 Te 5 is used in phase change memory, a nonvolatile memory technology, due to its phase change properties. The primary advantage of phase change memory over the state-of-the-art (flash memory) is its simple and small device geometry, which allows for denser nodes and lower power consumption. In phase change memory, resistive heating induces fast switching between the high resistance amorphous and low resistance crystalline phases, corresponding to storage of low and high digital states, respectively. However, the instability of the amorphous phase of Ge 2 Sb 2 Te 5 presents issues with processing and long-term data storage; such issues can be resolved by C doping, which stabilizes the amorphous phase and raises the crystallization temperature. To better understand the local structural effects of C doping on Ge 2 Sb 2 Te 5 , in situ Ge K-edge X-ray absorption spectroscopy measurements were taken during heating of films with various C doping concentrations. Here, the range of structural transformation temperatures derived from X-ray absorption near-edge structure analysis across the C doping series proved narrower than crystallization temperatures reported in similar in situ X-ray diffraction experiments, which may reflect changes in local structure that precede long-range ordering during crystallization. In addition, rigorous extended X-ray absorption fine structure fitting across and between temperature series revealed effects of C doping on the rigidity of Ge–Te bonds at low (2 at% and 4 at%) C concentrations.

Langhout, John D.↗
NASA NTRS2001

A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

Bell, L. D.↗
DOE OSTI2022

Progress toward picosecond on-chip magnetic memory

Here, we offer a perspective on the prospects of ultrafast spintronics and opto-magnetism as a pathway to high-performance, energy-efficient, and non-volatile embedded memory in digital integrated circuit applications. Conventional spintronic devices, such as spin-transfer-torque magnetic-resistive random-access memory (STT-MRAM) and spin–orbit torque MRAM, are promising due to their non-volatility, energy-efficiency, and high endurance. STT-MRAMs are now entering into the commercial market; however, they are limited in write speed to the nanosecond timescale. Improvement in the write speed of spintronic devices can significantly increase their usefulness as viable alternatives to the existing CMOS-based devices. In this article, we discuss recent studies that advance the field of ultrafast spintronics and opto-magnetism. An optimized ferromagnet–ferrimagnet exchange-coupled magnetic stack, which can serve as the free layer of a magnetic tunnel junction (MTJ), can be optically switched in as fast as ~3 ps. Integration of ultrafast magnetic switching of a similar stack into an MTJ device has enabled electrical readout of the switched state using a relatively larger tunneling magnetoresistance ratio. Purely electronic ultrafast spin–orbit torque induced switching of a ferromagnet has been demonstrated using ~6 ps long charge current pulses. We conclude our Perspective by discussing some of the challenges that remain to be addressed to accelerate ultrafast spintronics technologies toward practical implementation in high-performance digital information processing systems.

42 ENGINEERING↗
DOE OSTI2018

Scalable energy-efficient magnetoelectric spin–orbit logic

Since the early 1980s, most electronics have relied on the use of complementary metal–oxide–semiconductor (CMOS) transistors. However, the principles of CMOS operation, involving a switchable semiconductor conductance controlled by an insulating gate, have remained largely unchanged, even as transistors are miniaturized to sizes of 10 nanometres. We investigated what dimensionally scalable logic technology beyond CMOS could provide improvements in efficiency and performance for von Neumann architectures and enable growth in emerging computing such as artifical intelligence. Such a computing technology needs to allow progressive miniaturization, reduce switching energy, improve device interconnection and provide a complete logic and memory family. Here we propose a scalable spintronic logic device that operates via spin–orbit transduction (the coupling of an electron’s angular momentum with its linear momentum) combined with magnetoelectric switching. The device uses advanced quantum materials, especially correlated oxides and topological states of matter, for collective switching and detection. We describe progress in magnetoelectric switching and spin–orbit detection of state, and show that in comparison with CMOS technology our device has superior switching energy (by a factor of 10 to 30), lower switching voltage (by a factor of 5) and enhanced logic density (by a factor of 5). Additionally, its non-volatility enables ultralow standby power, which is critical to modern computing. The properties of our device indicate that the proposed technology could enable the development of multi-generational computing.

42 ENGINEERING↗
DOE OSTI2021

High-Speed Ionic Synaptic Memory Based on 2D Titanium Carbide MXene

Synaptic devices with linear high-speed switching can accelerate learning in artificial neural networks (ANNs) embodied in hardware. Conventional resistive memories however suffer from high write noise and asymmetric conductance tuning, preventing parallel programming of ANN arrays. Electrochemical random-access memories (ECRAMs), where resistive switching occurs by ion insertion into a redox-active channel, aim to address these challenges due to their linear switching and low noise. ECRAMs using 2D materials and metal oxides however suffer from slow ion kinetics, whereas organic ECRAMs enable high-speed operation but face challenges toward on-chip integration due to poor temperature stability of polymers. Here, ECRAMs using 2D titanium carbide (Ti 3 C 2 T x ) MXene that combine the high speed of organics and the integration compatibility of inorganic materials in a single high-performance device are demonstrated. These ECRAMs combine the speed, linearity, write noise, switching energy, and endurance metrics essential for parallel acceleration of ANNs, and importantly, they are stable after heat treatment needed for back-end-of-line integration with Si electronics. The high speed and performance of these ECRAMs introduces MXenes, a large family of 2D carbides and nitrides with more than 30 stoichiometric compositions synthesized to date, as promising candidates for devices operating at the nexus of electrochemistry and electronics.

2D materials↗
DOE OSTI2014

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Memristive behavior in a junctionless flash memory cell

We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO{sub 2} as the tunnel dielectric, Al{sub 2}O{sub 3} as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits the pinched hysteresis of a memristor and in the unoptimized device, R{sub off}/R{sub on} ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts R{sub off}/R{sub on} ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 10{sup 6 }s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2018

Software development environment and method of compiling integrated source code

A software development environment (SDE) and a method of compiling integrated source code. One embodiment of the SDE includes: (1) a parser configured to partition an integrated source code into a host code partition and a device code partition, the host code partition including a reference to a device variable, (2) a translator configured to: (2a) embed device machine code, compiled based on the device code partition, into a modified host code, (2b) define a pointer in the modified host code configured to be initialized, upon execution of the integrated source code, to a memory address allocated to the device variable, and (2c) replace the reference with a dereference to the pointer, and (3) a host compiler configured to employ a host library to compile the modified host code.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2016

From MEMRISTOR to MEMImpedance device

The behavior of the capacitance switching of HfO{sub 2} Resistive non-volatile Memories is investigated in view of realizing a MEMImpedance (MEM-Z) device. In such a Metal Insulator Metal structure, the impedance value can be tuned by the adjustment of both resistance and capacitance values. We observe a strong variation of capacitance from positive to negative values in a single layer Metal Insulator Metal device made of HfO{sub 2} deposited by Atomic Layer Deposition, but unfortunately no memory effect is observed. However, in the case of a two layer structure, a device has been obtained with a memory effect where both resistance and capacitance values can be tuned simultaneously, with a variation of capacitance down to negative values to get an inductive behavior. Negative capacitance values are observed for voltage values near SET voltage. A schematic model based on shaped oxygen vacancy density is proposed to account for this capacitance variation. The oxygen vacancies can be either isolated or connected in the bulk of the oxide.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Nonvolatile Memristive Effect in Few-Layer CrI 3 Driven by Electrostatic Gating

The potential of memristive devices for applications in nonvolatile memory and neuromorphic computing has sparked considerable interest, particularly in exploring memristive effects in two-dimensional (2D) magnetic materials. However, the progress in developing nonvolatile, magnetic field-free memristive devices using 2D magnets has been limited. In this work, we report an electrostatic-gating-induced nonvolatile memristive effect in CrI 3 -based tunnel junctions. The few-layer CrI 3 -based tunnel junction manifests notable hysteresis in its tunneling resistance as a function of gate voltage. We further engineered a nonvolatile memristor using the CrI 3 tunneling junction with low writing power and at zero magnetic field. We show that the hysteretic transport observed is not a result of trivial effects or inherent magnetic properties of CrI 3 . We propose a potential association between the memristive effect and the newly predicted ferroelectricity in CrI 3 via gating-induced Jahn–Teller distortion. Furthermore, our work illuminates the potential of 2D magnets in developing next-generation advanced computing technologies.

2D magnet↗
DOE OSTI2021

Interconnect architecture for three-dimensional processing systems

A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.

Jayasena, Nuwan S.↗
DOE OSTI2025

Kelvin Probe Force Microscopy Imaging of Plasticity in Hydrogenated Perovskite Nickelate Multilevel Neuromorphic Devices

Ion drift in nanoscale electronically inhomogeneous semiconductors is among the most important mechanisms being studied for designing neuromorphic computing hardware. However, nondestructive imaging of the ion drift in operando devices directly responsible for multiresistance states and synaptic memory represents a formidable challenge. Here, we present Kelvin probe force microscopy imaging of hydrogen-doped perovskite nickelate device channels subject to high-speed electric field pulses to directly visualize proton distribution by monitoring surface potential changes spatially, which is also supported with finite element-based electric field distribution studies. First-principles calculations provide mechanistic insights into the origin of surface potential changes as a function of hydrogen donor doping that serves as the contrast mechanism. We demonstrate 128 (7-bit) nonvolatile conductance levels in such devices relevant to in-memory computing applications. The synaptic plasticity measurements are implemented in spiking neural networks and show promising results for classification (SciKit Learn’s Iris and Wine data sets) and control (OpenAI’s CartPole-v1 and BipedalWalker-v3) simulation tasks.

Kelvin probe force microscopy↗
DOE OSTI2025

Short-Term Forecasting of Thermostatic and Residential Loads Using Long Short-Term Memory Recurrent Neural Networks

Internet of Things (IoT) devices in smart grids enable intelligent energy management for grid managers and personalized energy services for consumers. Investigating a smart grid with IoT devices requires a simulation framework with IoT devices modeling. However, there lack comprehensive study on the modeling of IoT devices in smart grids. This paper investigates the IoT device modeling of a thermostatic load and implements the recurrent neural networks model for short-term load forecasting in this IoT-based thermostatic load. The recurrent neural network structure is leveraged to build a load forecasting model on temporal correlation. The temporal recurrent neural network layers including long short-term memory cells are employed to learn the data from both the simulation platform and New South Wales residential datasets. The simulation results are provided for demonstration.

electric load forecasting↗
DOE OSTI2020

Beyond Substrates: Strain Engineering of Ferroelectric Membranes

Strain engineering in perovskite oxides provides for dramatic control over material structure, phase, and properties, but is restricted by the discrete strain states produced by available high-quality substrates. Here, using the ferroelectric BaTiO3, production of precisely strain-engineered, substrate-released nanoscale membranes is demonstrated via an epitaxial lift-off process that allows the high crystalline quality of films grown on substrates to be replicated. In turn, fine structural tuning is achieved using interlayer stress in symmetric trilayer oxide-metal/ferroelectric/oxide-metal structures fabricated from the released membranes. Additionally, in devices integrated on silicon, the interlayer stress provides deterministic control of ordering temperature (from 75 to 425 °C) and releasing the substrate clamping is shown to dramatically impact ferroelectric switching and domain dynamics (including reducing coercive fields to <10 kV cm-1 and improving switching times to <5 ns for a 20 µm diameter capacitor in a 100-nm-thick film). In devices integrated on flexible polymers, enhanced room-temperature dielectric permittivity with large mechanical tunability (a 90% change upon ±0.1% strain application) is demonstrated. This approach paves the way toward the fabrication of ultrafast CMOS-compatible ferroelectric memories and ultrasensitive flexible nanosensor devices, and it may also be leveraged for the stabilization of novel phases and functionalities not achievable via direct epitaxial growth.

36 MATERIALS SCIENCE↗
DOE OSTI2010

Parallelizing the QUDA Library for Multi-GPU Calculations in Lattice Quantum Chromodynamics

Graphics Processing Units (GPUs) are having a transformational effect on numerical lattice quantum chromodynamics (LQCD) calculations of importance in nuclear and particle physics. The QUDA library provides a package of mixed precision sparse matrix linear solvers for LQCD applications, supporting single GPUs based on NVIDIA's Compute Unified Device Architecture (CUDA). This library, interfaced to the QDP++/Chroma framework for LQCD calculations, is currently in production use on the "9g" cluster at the Jefferson Laboratory, enabling unprecedented price/performance for a range of problems in LQCD. Nevertheless, memory constraints on current GPU devices limit the problem sizes that can be tackled. In this contribution we describe the parallelization of the QUDA library onto multiple GPUs using MPI, including strategies for the overlapping of communication and computation. We report on both weak and strong scaling for up to 32 GPUs interconnected by InfiniBand, on which we sustain in excess of 4 Tflops.

43 PARTICLE ACCELERATORS↗
NASA NTRS2008

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

LaBel, Kenneth A.↗
NASA NTRS1990

Solid-state thin-film memistor for electronic neural networks

This paper reports on a tungsten-oxide-based, nonvolatile, electrically reprogrammable, variable resistance device as an analog synaptic memory connection for electronic neural networks. A voltage controlled, reversible injection of H(+) ions in electrochromic thin films of WO3 is utilized to modulate its resistance. A hygroscopic thin film of Cr2O3 is the source of H(+) ions. The resistance of the device can be tailored and stabilized over a wide dynamic range (about 4 orders of magnitude), and the programming speed is modulated by the control voltage. The suitability of such a device in terms of its response speed, reversibility, stability, and cyclability for its use in electronic neural networks is discussed.

Thakoor, S.↗
DOE OSTI2022

PUF-Based Two-Factor Authentication Protocol for Securing the Power Grid Against Insider Threat

Recent advances in smart grid technologies have enabled additional distributed control paradigms that allow more efficient and reliable operation. However, this creates new security concerns for the grid, such as attackers using spoofed grid control devices to generate false measurements. This paper introduces a two-factor authentication protocol leveraging standard public-key cryptography as one authentication factor and a hardware-based fingerprint, known as a Physical Unclonable Function, as a second authentication factor. This protocol incurs a small overhead and prevents cyber-attacks even when an adversary is able to compromise the cryptographic keys stored in the non-volatile memory of an intelligent control device.

42 ENGINEERING↗