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All sources NASA NTRS DOE OSTI

NASA NTRS1987

Improved Flux-Gate Magnetometer

Simplified circuit drives heading indicator and senses magnetic field of Earth. Simple flux-gate magnetometer supplies digital readout of magnetic heading of vehicle, developed to drive heading indicator, or supply heading information to autopilot or to other navigational instruments. Important feature is core driven into saturation in one direction only by alternating drive voltage, which swings from zero to one polarity and back. Made in part of commercially available integrated circuits.

Garner, H. Douglas↗

NASA NTRS1994

VLSI technology for smaller, cheaper, faster return link systems

Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

Nanzetta, Kathy↗

NASA NTRS1981

Impact of VLSI/VHSIC on satellite on-board signal processing

Forecasted improvements in IC fabrication techniques, such as the use of X-ray lithography, are expected to yield submicron circuit feature sizes within the decade of the 1980s. As dimensions decrease, reliability, cost, speed, power consumption and density improvements will be realized which have a significant impact on the capabilities of onboard spacecraft signal processing functions. This will in turn result in increases of the intelligence that may be deployed on spaceborne remote sensing platforms. Among programs oriented toward such goals are the silicon-based Very High Speed Integrated Circuit (VHSIC) researches sponsored by the U.S. Department of Defense, and efforts toward the development of GaAs devices which will compete with silicon VLSI technology for future applications. GaAs has an electron mobility which is five to six times that of silicon, and promises commensurate computation speed increases under low field conditions.

Aanstoos, J. V.↗

NASA NTRS2011

Fast Imaging Detector Readout Circuits with In-Pixel ADCs for Fourier Transform Imaging Spectrometers

Focal plane arrays (FPAs) with high frame rates and many pixels benefit several upcoming Earth science missions including GEO-CAPE, GACM, and ACE by enabling broader spatial coverage and higher spectral resolution. FPAs for the PanFTS, a high spatial resolution Fourier transform spectrometer and a candidate instrument for the GEO-CAPE mission are the focus of the developments reported here, but this FPA technology has the potential to enable a variety of future measurements and instruments. The ESTO ACT Program funded the developed of a fast readout integrated circuit (ROIC) based on an innovative in-pixel analog-to-digital converter (ADC). The 128 X 128 pixel ROIC features 60 ?m pixels, a 14-bit ADC in each pixel and operates at a continuous frame rate of 14 kHz consuming only 1.1 W of power. The ROIC outputs digitized data completely eliminating the bulky, power consuming signal chains needed by conventional FPAs. The 128 X 128 pixel ROIC has been fabricated in CMOS and tested at the Jet Propulsion Laboratory. The current version is designed to be hybridized with PIN photodiode arrays via indium bump bonding for light detection in the visible and ultraviolet spectral regions. However, the ROIC design incorporates a small photodiode in each cell to permit detailed characterization of the ROICperformance without the need for hybridization. We will describe the essential features of the ROIC design and present results of ROIC performance measurements.

focal plane arrays (FPAs)↗

NASA NTRS2003

120-GHz HEMT Oscillator With Surface-Wave-Assisted Antenna

Two monolithic microwave integrated circuits (MMICs) have been designed and built to function together as a source of electromagnetic radiation at a frequency of 120 GHz. One of the MMICs is an oscillator and is the highest-power 120-GHz oscillator reported thus far in the literature. The other MMIC is an end-fire antenna that radiates the oscillator signal. Although these MMICs were constructed as separate units and electrically connected with wire bonds, future oscillator/ antenna combinations could readily be fabricated as monolithic integrated units. Such units could be used as relatively high-power solid-state microwave sources in diverse applications that include automotive radar, imaging, scientific instrumentation, communications, and radio astronomy. As such, these units would be attractive alternatives to vacuum-tube oscillators, which are still used to obtain acceptably high power in the frequency range of interest. The oscillator (see figure) includes a high-electron-mobility transistor (HEMT), with gate-periphery dimensions of 4 by 37 m, in a common-source configuration. The series feedback element of the oscillator is a grounded coplanar waveguide (CPW) at the source. The HEMT is biased for class-A operation (meaning that current is conducted throughout the oscillation cycle) to maximize the output power of the oscillator. Input and output impedance-matching circuit elements are designed to maximize output power and to establish the conditions needed for oscillation. The design of the antenna takes advantage of surface waves, which, heretofore, have been regarded as highly disadvantageous because they can leak power and degrade the performances of antennas that have not been designed to exploit them. Measures taken to suppress surface waves have included complex machining of circuit substrates and addition of separate substrates. These measures are difficult to implement in standard MMIC fabrication processes. In contrast, because the design of the present antenna eliminates the need to suppress surface waves, the fabrication of the antenna is fully compatible with standard MMIC fabrication processes.

Samoska, Lorene↗

NASA NTRS1988

GaAs MMIC elements in phased-array antennas

Over the last six years NASA Lewis Research Center has carried out a program aimed at the development of advanced monolithic microwave integrated circuit technology, principally for use in phased-array antenna applications. Arising out of the Advanced Communications Technology Satellite (ACTS) program, the initial targets of the program were chips which operated at 30 and 20 GHz. Included in this group of activities were monolithic power modules with an output of 2 watts at GHz, variable phase shifters at both 20 and 30 GHz, low noise technology at 30 GHz, and a fully integrated (phase shifter, variable gain amplifier, power amplifier) transmit module at 20 GHz. Subsequent developments are centered on NASA mission requirements, particularly Space Station communications systems and deep space data communications.

Leonard, Regis F.↗

DOE OSTI2026

Characterization of the First Prototype of the L1K65n Differential-Output Charge-Sensitive Preamplifier ASIC for High-Performance, Low-Background HPGe Detector Readout

Next-generation neutrinoless double-beta (0νββ) decay searches require a large detector/isotope mass and very low radioactive backgrounds. The upcoming LEGEND-1000 experiment (Large Enriched Germanium Experiment for Neutrinoless double-beta Decay) constitute a ton-scale array of several hundred high-purity germanium (HPGe) detectors enriched in 76Ge, the isotope of interest. It aims to reach a sensitivity beyond 10 28 years on the 0νββ decay half-life of 76Ge, necessitating an order of magnitude reduction in background with respect to the state of the art. This will require the implementation of a dedicated application specific integrated circuit (ASIC) preamplifier that will significantly lower background contribution compared to the conventional low-mass front end (LMFE) employed in the Majorana Demonstrator and LEGEND-200 experiments while maintaining or improving energy resolution and other performance parameters. Features include a high (9 MeV) dynamic range with noise low enough to achieve a trigger threshold of <1 keV, a single power supply to reduce background-inducing cabling, and a differential output to maintain signal integrity over several meters of transmission line. The chip would be optimized to operate in liquid argon (87 K) and be able to do so reliably for ten years. Following on from an earlier 180-nm prototype, we have developed a differential-output charge-sensitive preamplifier ASIC fabricated in a 65-nm process, 1×2 mm in size, that addresses these needs. Here, we present recent results from the successful testing and characterization of the first version of this device.

ASIC↗

NASA NTRS1972

Design, processing, and testing of lsi arrays for space station

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Lile, W. R.↗

NASA NTRS2010

Advances in HgCdTe APDs and LADAR Receivers

Raytheon is developing NIR sensor chip assemblies (SCAs) for scanning and staring 3D LADAR systems. High sensitivity is obtained by integrating high performance detectors with gain i.e. APDs with very low noise Readout Integrated Circuits. Unique aspects of these designs include: independent acquisition (non-gated) of pulse returns, multiple pulse returns with both time and intensity reported to enable full 3D reconstruction of the image. Recent breakthrough in device design has resulted in HgCdTe APDs operating at 300K with essentially no excess noise to gains in excess of 100, low NEP <1nW and GHz bandwidths and have demonstrated linear mode photon counting. SCAs utilizing these high performance APDs have been integrated and demonstrated excellent spatial and range resolution enabling detailed 3D imagery both at short range and long ranges. In this presentation we will review progress in high resolution scanning, staring and ultra-high sensitivity photon counting LADAR sensors.

Bailey, Steven↗

NASA NTRS1990

Custom CMOS Reed Solomon coder for the Hubble Space Telescope

A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.

Whitaker, S.↗

NASA NTRS2005

Method of forming ultra thin film devices by vacuum arc vapor deposition

A method for providing an ultra thin electrical circuit integral with a portion of a surface of an object, including using a focal Vacuum Arc Vapor Deposition device having a chamber, a nozzle and a nozzle seal, depressing the nozzle seal against the portion of the object surface to create an airtight compartment in the chamber and depositing one or more ultra thin film layer(s) only on the portion of the surface of the object, the layers being of distinct patterns such that they form the circuit.

Schramm, Harry F.↗

NASA NTRS2012

Advances in LADAR Components and Subsystems at Raytheon

Raytheon is developing NIR sensor chip assemblies (SCAs) for scanning and staring 3D LADAR systems. High sensitivity is obtained by integrating high performance detectors with gain, i.e., APDs with very low noise Readout Integrated Circuits (ROICs). Unique aspects of these designs include: independent acquisition (non-gated) of pulse returns, multiple pulse returns with both time and intensity reported to enable full 3D reconstruction of the image. Recent breakthrough in device design has resulted in HgCdTe APDs operating at 300K with essentially no excess noise to gains in excess of 100, low NEP <1nW and GHz bandwidths and have demonstrated linear mode photon counting. SCAs utilizing these high performance APDs have been integrated and demonstrated excellent spatial and range resolution enabling detailed 3D imagery both at short range and long ranges. In the following we will review progress in real-time 3D LADAR imaging receiver products in three areas: (1) scanning 256 x 4 configuration for the Multi-Mode Sensor Seeker (MMSS) program and (2) staring 256 x 256 configuration for the Autonomous Landing and Hazard Avoidance Technology (ALHAT) lunar landing mission and (3) Photon-Counting SCAs which have demonstrated a dramatic reduction in dark count rate due to improved design, operation and processing.

Jack, Michael↗

DOE OSTI2023

Intelligent Proppants for Hydraulic Fracture Diagnostics

This Phase 1 Report details our Phase 1 progress in proving the feasibility of a highly integrated, highly miniaturized sensor ball. The ball contains sensors, analog to digital converters, memory, a clock, and an acoustic communications module all integrated onto a single silicon chip. Phase 2 is to focus on the application specific integrated circuit (ASIC). Phase 1 piecewise proves the feasibility of this innovation by examining a few critical subsystems including the communications module and inertial sensor performance. Acoustic simulations of an acoustically active and traceable proppant are also performed and summarized in this report.

01 COAL, LIGNITE, AND PEAT↗

DOE OSTI2020

Physics and applications of quantum dot lasers for silicon photonics

Abstract Photonic integrated circuits (PICs) have enabled numerous high performance, energy efficient, and compact technologies for optical communications, sensing, and metrology. One of the biggest challenges in scaling PICs comes from the parasitic reflections that feed light back into the laser source. These reflections increase noise and may cause laser destabilization. To avoid parasitic reflections, expensive and bulky optical isolators have been placed between the laser and the rest of the PIC leading to large increases in device footprint for on-chip integration schemes and significant increases in packaging complexity and cost for lasers co-packaged with passive PICs. This review article reports new findings on epitaxial quantum dot lasers on silicon and studies both theoretically and experimentally the connection between the material properties and the ultra-low reflection sensitivity that is achieved. Our results show that such quantum dot lasers on silicon exhibit much lower linewidth enhancement factors than any quantum well lasers. Together with the large damping factor, we show that the quantum dot gain medium is fundamentally dependent on dot uniformity, but through careful optimization, even epitaxial lasers on silicon can operate without an optical isolator, which is of paramount importance for the future high-speed silicon photonic systems.

36 MATERIALS SCIENCE↗

DOE OSTI2021

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS1986

Optical techniques to feed and control GaAs MMIC modules for phased array antenna applications

A complex signal distribution system is required to feed and control GaAs monolithic microwave integrated circuits (MMICs) for phased array antenna applications above 20 GHz. Each MMIC module will require one or more RF lines, one or more bias voltage lines, and digital lines to provide a minimum of 10 bits of combined phase and gain control information. In a closely spaced array, the routing of these multiple lines presents difficult topology problems as well as a high probability of signal interference. To overcome GaAs MMIC phased array signal distribution problems optical fibers interconnected to monolithically integrated optical components with GaAs MMIC array elements are proposed as a solution. System architecture considerations using optical fibers are described. The analog and digital optical links to respectively feed and control MMIC elements are analyzed. It is concluded that a fiber optic network will reduce weight and complexity, and increase reliability and performance, but higher power will be required.

Bhasin, K. B.↗

NASA NTRS1986

Optical techniques to feed and control GaAs MMIC modules for phased array antenna applications

Bhasin, K. B.↗

NASA NTRS1994

QPPM receiver for free-space laser communications

A prototype receiver developed at NASA Lewis Research Center for direct detection and demodulation of quaternary pulse position modulated (QPPM) optical carriers is described. The receiver enables dual-channel communications at 325-Megabits per second (Mbps) per channel. The optical components of the prototype receiver are briefly described. The electronic components, comprising the analog signal conditioning, slot clock recovery, matched filter and maximum likelihood data recovery circuits are described in more detail. A novel digital symbol clock recovery technique is presented as an alternative to conventional analog methods. Simulated link degradations including noise and pointing-error induced amplitude variations are applied. The bit-error-rate performance of the electronic portion of the prototype receiver under varying optical signal-to-noise power ratios is found to be within 1.5-dB of theory. Implementation of the receiver as a hybrid of analog and digital application specific integrated circuits is planned.

Budinger, J. M.↗