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DOE OSTI2026

Digital Twin User Guide for Chelan County Public Utility District

This user manual offers a comprehensive guide for developing a Digital twin (DT) of a Kaplan turbine at Chelan County Public Utility District (Chelan PUD) using neural networks. As variable renewable generation expands, hydropower units must operate with optimal efficiency and stability. For Kaplan machines, this flexibility is achieved through coordinated control of guide vane (wicket gates) opening and runner blade pitch, which amplifies the plant’s inherent nonlinear behavior and challenges traditional physics-only modeling. The efficiency of the Kaplan turbine varies with different combinations of the guide vans (wicket gate) opening and the blade angle. Each guide van opening and blade angle has a corresponding highest efficiency point, forming a cam relationship that represents the optimal combination.The discharge of a hydraulic turbine is controlled by the opening angle of the guide vans. Therefore, for each value of head, there is a certain guide van opening and blade angle that corresponds to the highest efficiency. For a given head, different combinations of the guide van opening and blade angle have different efficiencies. Therefore, coordinate cam curves are used to describe the relationship between the wicket gate opening and blade angle with different water head. To address these challenges, the manual details a data-driven modeling and learning workflow centered on structured neural networks. The approach is designed to forecast critical operational variables—discharge flow, net head, penstock (or scroll-case) pressure, and generator electrical outputs—by leveraging real-time inputs such as the generator power control setpoint, exciter field current and field voltage, together with hydromechanical commands (e.g., gate position and, when available, runner blade-pitch angle). The neural models are trained and validated on operational data from a Kaplan unit operated by Chelan PUD, demonstrating that the structured NN architecture can learn the coupled gate–blade–electrical dynamics. The result is a robust DT that improves situational awareness and supports data-informed decision-making for Chelan PUD’s Kaplan turbine operations.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2026

Pulse control of superconducting cavity-based qudits with a Fock-state basis

Fock-basis-encoding qudits allow quantum gates to operate on multiple qudit levels simultaneously. This capability is advantageous for applications involving complex local gate operations, such as the digital quantum simulation of non-Abelian gauge theories. However, compiling unitary operations to native qudit gates remains a challenging task, often requiring substantial computational resources. In this work, we theoretically investigate the direct pulse control of a superconducting radio-frequency cavity coupled to an ancilla transmon for gate synthesis. We will discuss the improvements and limitations applicable to high Fock states. This work paves the way toward more efficient and robust qudit-gate synthesis.

Li, Andy C.Y. [Fermilab] (ORCID:0000000345423739)↗

DOE OSTI2026

Pulse control of superconducting cavity-based qudits with a Fock-state basis

Li, Andy C.Y. [Fermilab] (ORCID:0000000345423739)↗

DOE OSTI2023

AlGaN High Electron Mobility Transistor for High-Temperature Logic

Here we report on AlGaN high electron mobility transistor (HEMT)-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature-dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data (from 30°C to 500°C) revealed the reference GaN-channel HEMT experienced a 6.9x reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200-nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

42 ENGINEERING↗

NASA NTRS1972

Design, processing, and testing of lsi arrays for space station

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Lile, W. R.↗

NASA NTRS1974

Ultrasonic biomedical measuring and recording apparatus

A train of ultrasonic pulses is beamed into the body of an animal. Organs intercepted by the beam reflect echo pulses following each transmitted pulse. An electronic gate with a variable width and a variable time delay relative to the transmitted pulse is utilized for selecting echoes derived from other organs or portions of organs. The integral of the echo signals received within the first half of the gate period is subtracted from a corresponding integral of the echo signal received during the second half of the gate to derive an error signal for controlling the time delay of the gate. In this manner, the selected echo signal is always maintained in the center of the gate.

Lee, R. D.↗

NASA NTRS1976

Method and apparatus for measurement of trap density and energy distribution in dielectric films

Trap densities in dielectric films are determined by tunnel injection measurements when the film is incorporated in an insulated-gate field effect transistor. Under applied bias to the transistor gate, carriers (electrons or holes) tunnel into traps in the dielectric film. The resulting space charge tends to change channel conductance. By feeding back a signal from the source contact to the gate electrode, channel conductance is held constant, and by recording the gate voltage as a function of time, trap density can be determined as a function of distance from the dielectric-semiconductor interface. The process is repeated with the gate bias voltage at different levels in order to determine the energy distribution of traps as a function of distance from the interface.

Maserjian, J.↗

NASA NTRS1983

Pinhole array capacitor for oxide integrity analysis

The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk processes. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used in this study contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.

Buehler, M. G.↗

NASA NTRS1985

Pinhole array capacitor for oxide integrity analysis

The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk process. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.

Buehler, M. G.↗

NASA NTRS1990

Low-noise nozzle valve

A low noise, variable discharage area, valve is constructed having opposed recesses within which a pair of gates are slidably disposed. Each of the gates is provided with upstream edges having a radius thereon, the radius enabling smooth, accelerated, low noise flow therebetween. The gates are further provided with tracks along each side, which in turn slide along splines set in the side walls of the valve. A threaded rod which rotates in a threaded insert in a rear wall of each of the gates, serves to move the gates within their respective recesses.

Gwin, Hal S.↗

NASA NTRS1991

A parallel algorithm for multi-level logic synthesis using the transduction method

The Transduction Method has been shown to be a powerful tool in the optimization of multilevel networks. Many tools such as the SYLON synthesis system (X90), (CM89), (LM90) have been developed based on this method. A parallel implementation is presented of SYLON-XTRANS (XM89) on an eight processor Encore Multimax shared memory multiprocessor. It minimizes multilevel networks consisting of simple gates through parallel pruning, gate substitution, gate merging, generalized gate substitution, and gate input reduction. This implementation, called Parallel TRANSduction (PTRANS), also uses partitioning to break large circuits up and performs inter- and intra-partition dynamic load balancing. With this, good speedups and high processor efficiencies are achievable without sacrificing the resulting circuit quality.

Lim, Chieng-Fai↗

NASA NTRS1993

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

Attia, John Okyere↗

NASA NTRS1993

Improvements to pulsed phase locked loop strain monitor

A pulse phase locked loop system according to the present invention is described. A frequency generator such as a voltage controlled oscillator (VCO) generates an output signal and a reference signal having a frequency equal to that of the output signal. A transmitting gate gates the output frequency signal and this gated signal drives a transmitting transducer which transmits an acoustic wave through a material. A sample/hold samples a signal indicative of the transmitted wave which is received by a receiving transducer. Divide-by-n counters control these gating and sampling functions in response to the reference signal of the frequency generator. Specifically, the output signal is gated at a rate of F/h, wherein F is the frequency of the output signal and h is an integer; and the received signal is sampled at a delay of F/n wherein n is an integer.

Froggatt, Mark E.↗

NASA NTRS1999

Optical Imaging of Flow Pattern and Phantom

Time-resolved optical imaging technique has been used to image the spatial distribution of small droplets and jet sprays in a highly scattering environment. The snake and ballistic components of the transmitted pulse are less scattered, and contain direct information about the sample to facilitate image formation as opposed to the diffusive components which are due to multiple collisions as a light pulse propagates through a scattering medium. In a time-gated imaging scheme, these early-arriving, image-bearing components of the incident pulse are selected by opening a gate for an ultrashort period of time and a shadowgram image is detected. Using a single shot cooled CCD camera system, the formation of water droplets is monitored as a function of time. Picosecond time-gated image of drop in scattering cells, spray droplets as a function of let speed and gas pressure, and model calcification samples consisted of calcium carbonate particles of irregular shapes ranging in size from 0. 1 to 1.5 mm affixed to a microscope slide have been measured. Formation produced by an impinging jet will be further monitored using a CCD with 1 kHz framing illuminated with pulsed light. The desired image resolution of the fuel droplets is on the 20 pm scale using early light through a highly scattering medium. A 10(exp -6)m displacement from a jet spray with a flow speed of 100 m/sec introduced by the ns grating pulse used in the imaging is negligible. Early ballistic/snake light imaging offers nondestructive and noninvasive method to observe the spatial distribution of hidden objects inside a highly scattering environment for space, biomedical, and materials applications. In this paper, the techniques we will present are time-resolved K-F transillumination imaging and time-gated scattered light imaging. With a large dynamic range and high resolution, time-gated early light imaging has the potential for improving rocket/aircraft design by determining jets shape and particle sizes. Refinements to these techniques may enable drop size measurements in the highly scattering, optically dense region of multi-element rocket injectors. These types of measurements should greatly enhance the design of stable, and higher performing rocket engines.

Galland, Pierre A.↗

NASA NTRS2003

Spectral Retrieval of Latent Heating Profiles from TRMM PR Data: Comparison of Look-Up Tables

The primary goal of the Tropical Rainfall Measuring Mission (TRMM) is to use the information about distributions of precipitation to determine the four dimensional (i.e., temporal and spatial) patterns of latent heating over the whole tropical region. The Spectral Latent Heating (SLH) algorithm has been developed to estimate latent heating profiles for the TRMM Precipitation Radar (PR) with a cloud- resolving model (CRM). The method uses CRM- generated heating profile look-up tables for the three rain types; convective, shallow stratiform, and anvil rain (deep stratiform with a melting level). For convective and shallow stratiform regions, the look-up table refers to the precipitation top height (PTH). For anvil region, on the other hand, the look- up table refers to the precipitation rate at the melting level instead of PTH. For global applications, it is necessary to examine the universality of the look-up table. In this paper, we compare the look-up tables produced from the numerical simulations of cloud ensembles forced with the Tropical Ocean Global Atmosphere (TOGA) Coupled Atmosphere-Ocean Response Experiment (COARE) data and the GARP Atlantic Tropical Experiment (GATE) data. There are some notable differences between the TOGA-COARE table and the GATE table, especially for the convective heating. First, there is larger number of deepest convective profiles in the TOGA-COARE table than in the GATE table, mainly due to the differences in SST. Second, shallow convective heating is stronger in the TOGA COARE table than in the GATE table. This might be attributable to the difference in the strength of the low-level inversions. Third, altitudes of convective heating maxima are larger in the TOGA COARE table than in the GATE table. Levels of convective heating maxima are located just below the melting level, because warm-rain processes are prevalent in tropical oceanic convective systems. Differences in levels of convective heating maxima probably reflect differences in melting layer heights. We are now extending our study to simulations of other field experiments (e.g. SCSMEX and ARM) in order to examine the universality of the look-up table. The impact of look-up tables on the retrieved latent heating profiles will also be assessed.

Shige, Shoichi↗

NASA NTRS2005

Static and Turn-on Switching Characteristics of 4H-Silicon Carbide SITs to 200 deg C

Test results are presented for normally-off 4H-SiC Static Induction Transistors (SITs) intended for power switching and are among the first normally-off such devices realized in SiC. At zero gate bias, the gate p-n junction depletion layers extend far enough into the conduction channel to cut off the channel. Application of forward gate bias narrows the depletion regions, opening up the channel to conduction by majority carriers. In the present devices, narrow vertical channels get pinched by depletion regions from opposite sides. Since the material is SiC, the devices are usable at temperatures above 150 C. Static curve and pulse mode switching observations were done at selected temperatures up to 200 C on a device with average static characteristics from a batch of similar devices. Gate and drain currents were limited to about 400 mA and 3.5 A, respectively. The drain voltage was limited to roughly 300 V, which is conservative for this 600 V rated device. At 23 C, 1 kW, or even more, could be pulse mode switched in 65 ns (10 to 90 percent) into a 100 load. But at 200 C, the switching capability is greatly reduced in large part by the excessive gate current required. Severe collapse of the saturated drain-to-source current was observed at 200 C. The relation of this property to channel mobility is reviewed.

Niedra, Janis M.↗

NASA NTRS2004

Optimal design of two-qubit quantum circuits

In order to demonstrate non-trivial quantum computations experimentally, such as the synthesis of arbitrary entangled states, it will be useful to nderstand how to decompose a desired quantum computation into the shortest possible sequence of one-qubit and two-qubit gates. We contribute to this effort by providing a method to construct an optimal quantum circuit for a general two-qubit gate that requires at most 3 CNOT gates and 15 elementary one qubit gates. We then prove that these constructions are optimal with respect to the family of CNOT, y-rotation, z-rotation, and phase gates.

quantum circuit unitary operation↗

NASA NTRS1995

Pulsed phase locked loop strain monitor

Froggatt, Mark E.↗