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At least 991 records · Page 55
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

Computers in Spaceflight: the NASA Experience

This book examines the computer systems used in actual spaceflight or in close support of it. Computer systems used in administration and in aeronautical and other research not directly related to spaceflight are ignored. Each chapter deals with either a specific program, such as Gemini or Apollo onboard computers, or a closely related set of systems, such as launch processing or mission control.. A glossary of computer terms is included.

assembly language↗
NASA NTRS1989

Machine parts recognition using a trinary associative memory

The convergence mechanism of vectors in Hopfield's neural network in relation to recognition of partially known patterns is studied in terms of both inner products and Hamming distance. It has been shown that Hamming distance should not always be used in determining the convergence of vectors. Instead, inner product weighting coefficients play a more dominant role in certain data representations for determining the convergence mechanism. A trinary neuron representation for associative memory is found to be more effective for associative recall. Applications of the trinary associative memory to reconstruct machine part images that are partially missing are demonstrated by means of computer simulation as examples of the usefulness of this approach.

Awwal, Abdul Ahad S.↗
NASA NTRS1990

An adaptive vector quantization scheme

Vector quantization is known to be an effective compression scheme to achieve a low bit rate so as to minimize communication channel bandwidth and also to reduce digital memory storage while maintaining the necessary fidelity of the data. However, the large number of computations required in vector quantizers has been a handicap in using vector quantization for low-rate source coding. An adaptive vector quantization algorithm is introduced that is inherently suitable for simple hardware implementation because it has a simple architecture. It allows fast encoding and decoding because it requires only addition and subtraction operations.

Cheung, K.-M.↗
NASA NTRS1994

A report of work activities on the NASA Spacelink public electronic library

NASA Spacelink is a comprehensive electronic data base of NASA and other source educational and informational materials. This service originates at Marshall Space Flight Center (MSFC) in Huntsville, Alabama. This is an education service of NASA Headquarters, through the MSFC Education Office, that first began in February of 1988. The new NASA Spacelink Public Electronic Library was the result of a study conducted to investigate an upgrade or redesign of the original NASA Spacelink. The UNIX Operating System was chosen to be the host operating system for the new NASA Spacelink Public Electronic Library. The UNIX system was selected for this project because of the strengths built into the embedded communication system and for its simple and direct file handling capabilities. The host hardware of the new system is a Sun Microsystems SPARCserver 1000 computer system. The configuration has four 50-MHz SuperSPARC processors with 128 megabytes of shared memory; three SB800 serial ports allowing 24 cable links for phone communications; 4.1 gigabytes of on-line disk storage; and ten (10) CD-ROM drives. Communications devices on the system are sufficient to support the expected number of users through the Internet, the local dial services, long distance dial services; the MSFC PABX, and the NPSS (NASA Packet Switching System) and 1-800 access service for the registered teachers.

Smith, Willard A.↗
NASA NTRS1996

Satisfiability Test with Synchronous Simulated Annealing on the Fujitsu AP1000 Massively-Parallel Multiprocessor

Solving the hard Satisfiability Problem is time consuming even for modest-sized problem instances. Solving the Random L-SAT Problem is especially difficult due to the ratio of clauses to variables. This report presents a parallel synchronous simulated annealing method for solving the Random L-SAT Problem on a large-scale distributed-memory multiprocessor. In particular, we use a parallel synchronous simulated annealing procedure, called Generalized Speculative Computation, which guarantees the same decision sequence as sequential simulated annealing. To demonstrate the performance of the parallel method, we have selected problem instances varying in size from 100-variables/425-clauses to 5000-variables/21,250-clauses. Experimental results on the AP1000 multiprocessor indicate that our approach can satisfy 99.9 percent of the clauses while giving almost a 70-fold speedup on 500 processors.

Sohn, Andrew↗
NASA NTRS1994

Some Problems and Solutions in Transferring Ecosystem Simulation Codes to Supercomputers

Many computer codes for the simulation of ecological systems have been developed in the last twenty-five years. This development took place initially on main-frame computers, then mini-computers, and more recently, on micro-computers and workstations. Recent recognition of ecosystem science as a High Performance Computing and Communications Program Grand Challenge area emphasizes supercomputers (both parallel and distributed systems) as the next set of tools for ecological simulation. Transferring ecosystem simulation codes to such systems is not a matter of simply compiling and executing existing code on the supercomputer since there are significant differences in the system architectures of sequential, scalar computers and parallel and/or vector supercomputers. To more appropriately match the application to the architecture (necessary to achieve reasonable performance), the parallelism (if it exists) of the original application must be exploited. We discuss our work in transferring a general grassland simulation model (developed on a VAX in the FORTRAN computer programming language) to a Cray Y-MP. We show the Cray shared-memory vector-architecture, and discuss our rationale for selecting the Cray. We describe porting the model to the Cray and executing and verifying a baseline version, and we discuss the changes we made to exploit the parallelism in the application and to improve code execution. As a result, the Cray executed the model 30 times faster than the VAX 11/785 and 10 times faster than a Sun 4 workstation. We achieved an additional speed-up of approximately 30 percent over the original Cray run by using the compiler's vectorizing capabilities and the machine's ability to put subroutines and functions "in-line" in the code. With the modifications, the code still runs at only about 5% of the Cray's peak speed because it makes ineffective use of the vector processing capabilities of the Cray. We conclude with a discussion and future plans.

Skiles, J. W.↗
NASA NTRS2001

Transonic Drag Prediction Using an Unstructured Multigrid Solver

This paper summarizes the results obtained with the NSU-3D unstructured multigrid solver for the AIAA Drag Prediction Workshop held in Anaheim, CA, June 2001. The test case for the workshop consists of a wing-body configuration at transonic flow conditions. Flow analyses for a complete test matrix of lift coefficient values and Mach numbers at a constant Reynolds number are performed, thus producing a set of drag polars and drag rise curves which are compared with experimental data. Results were obtained independently by both authors using an identical baseline grid and different refined grids. Most cases were run in parallel on commodity cluster-type machines while the largest cases were run on an SGI Origin machine using 128 processors. The objective of this paper is to study the accuracy of the subject unstructured grid solver for predicting drag in the transonic cruise regime, to assess the efficiency of the method in terms of convergence, cpu time, and memory, and to determine the effects of grid resolution on this predictive ability and its computational efficiency. A good predictive ability is demonstrated over a wide range of conditions, although accuracy was found to degrade for cases at higher Mach numbers and lift values where increasing amounts of flow separation occur. The ability to rapidly compute large numbers of cases at varying flow conditions using an unstructured solver on inexpensive clusters of commodity computers is also demonstrated.

Mavriplis, D. J.↗
NASA NTRS1997

Efficacy of Code Optimization on Cache-Based Processors

In this paper a number of techniques for improving the cache performance of a representative piece of numerical software is presented. Target machines are popular processors from several vendors: MIPS R5000 (SGI Indy), MIPS R8000 (SGI PowerChallenge), MIPS R10000 (SGI Origin), DEC Alpha EV4 + EV5 (Cray T3D & T3E), IBM RS6000 (SP Wide-node), Intel PentiumPro (Ames' Whitney), Sun UltraSparc (NERSC's NOW). The optimizations all attempt to increase the locality of memory accesses. But they meet with rather varied and often counterintuitive success on the different computing platforms. We conclude that it may be genuinely impossible to obtain portable performance on the current generation of cache-based machines. At the least, it appears that the performance of modern commodity processors cannot be described with parameters defining the cache alone.

VanderWijngaart, Rob F.↗
NASA NTRS2006

A History of High-Performance Computing

Faster than most speedy computers. More powerful than its NASA data-processing predecessors. Able to leap large, mission-related computational problems in a single bound. Clearly, it s neither a bird nor a plane, nor does it need to don a red cape, because it s super in its own way. It's Columbia, NASA s newest supercomputer and one of the world s most powerful production/processing units. Named Columbia to honor the STS-107 Space Shuttle Columbia crewmembers, the new supercomputer is making it possible for NASA to achieve breakthroughs in science and engineering, fulfilling the Agency s missions, and, ultimately, the Vision for Space Exploration. Shortly after being built in 2004, Columbia achieved a benchmark rating of 51.9 teraflop/s on 10,240 processors, making it the world s fastest operational computer at the time of completion. Putting this speed into perspective, 20 years ago, the most powerful computer at NASA s Ames Research Center, home of the NASA Advanced Supercomputing Division (NAS), ran at a speed of about 1 gigaflop (one billion calculations per second). The Columbia supercomputer is 50,000 times faster than this computer and offers a tenfold increase in capacity over the prior system housed at Ames. What s more, Columbia is considered the world s largest Linux-based, shared-memory system. The system is offering immeasurable benefits to society and is the zenith of years of NASA/private industry collaboration that has spawned new generations of commercial, high-speed computing systems.

Source record↗
NASA NTRS2009

Flightspeed Integral Image Analysis Toolkit

The Flightspeed Integral Image Analysis Toolkit (FIIAT) is a C library that provides image analysis functions in a single, portable package. It provides basic low-level filtering, texture analysis, and subwindow descriptor for applications dealing with image interpretation and object recognition. Designed with spaceflight in mind, it addresses: Ease of integration (minimal external dependencies) Fast, real-time operation using integer arithmetic where possible (useful for platforms lacking a dedicated floatingpoint processor) Written entirely in C (easily modified) Mostly static memory allocation 8-bit image data The basic goal of the FIIAT library is to compute meaningful numerical descriptors for images or rectangular image regions. These n-vectors can then be used directly for novelty detection or pattern recognition, or as a feature space for higher-level pattern recognition tasks. The library provides routines for leveraging training data to derive descriptors that are most useful for a specific data set. Its runtime algorithms exploit a structure known as the "integral image." This is a caching method that permits fast summation of values within rectangular regions of an image. This integral frame facilitates a wide range of fast image-processing functions. This toolkit has applicability to a wide range of autonomous image analysis tasks in the space-flight domain, including novelty detection, object and scene classification, target detection for autonomous instrument placement, and science analysis of geomorphology. It makes real-time texture and pattern recognition possible for platforms with severe computational restraints. The software provides an order of magnitude speed increase over alternative software libraries currently in use by the research community. FIIAT can commercially support intelligent video cameras used in intelligent surveillance. It is also useful for object recognition by robots or other autonomous vehicles

Thompson, David R.↗
NASA NTRS1989

Development of a software interface for optical disk archival storage for a new life sciences flight experiments computer

The current Life Sciences Laboratory Equipment (LSLE) microcomputer for life sciences experiment data acquisition is now obsolete. Among the weaknesses of the current microcomputer are small memory size, relatively slow analog data sampling rates, and the lack of a bulk data storage device. While life science investigators normally prefer data to be transmitted to Earth as it is taken, this is not always possible. No down-link exists for experiments performed in the Shuttle middeck region. One important aspect of a replacement microcomputer is provision for in-flight storage of experimental data. The Write Once, Read Many (WORM) optical disk was studied because of its high storage density, data integrity, and the availability of a space-qualified unit. In keeping with the goals for a replacement microcomputer based upon commercially available components and standard interfaces, the system studied includes a Small Computer System Interface (SCSI) for interfacing the WORM drive. The system itself is designed around the STD bus, using readily available boards. Configurations examined were: (1) master processor board and slave processor board with the SCSI interface; (2) master processor with SCSI interface; (3) master processor with SCSI and Direct Memory Access (DMA); (4) master processor controlling a separate STD bus SCSI board; and (5) master processor controlling a separate STD bus SCSI board with DMA.

Bartram, Peter N.↗
NASA NTRS2015

Self-Repairing Fatigue Damage in Metallic Structures for Aerospace Vehicles Using Shape Memory Alloy Self-healing (SMASH) Technology

This DAA is for the Phase II webinar presentation of the ARMD-funded SMASH technology. A self-repairing aluminum-based composite system has been developed using liquid-assisted healing theory in conjunction with the shape memory effect of wire reinforcements. The metal matrix composite was thermodynamically designed to have a matrix with a relatively even dispersion of low-melting phase, allowing for repair of cracks at a pre-determined temperature. Shape memory alloy wire reinforcements were used within the composite to provide crack closure. Investigators focused the research on fatigue cracks propagating through the matrix in order to optimize and computer model the SMASH technology for aeronautical applications.

fatigue↗
NASA NTRS1993

Towards the formal specification of the requirements and design of a processor interface unit: HOL listings

This technical report contains the HOL listings of the specification of the design and major portions of the requirements for a commercially developed processor interface unit (or PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU specification as it currently exists. Section two of this report contains general-purpose HOL theories that support the PIU specification. These theories include definitions for the hardware components used in the PIU, our implementation of bit words, and our implementation of temporal logic. Section three contains the HOL listings for the PIU design specification. Aside from the PIU internal bus (I-Bus), this specification is complete. Section four contains the HOL listings for a major portion of the PIU requirements specification. Specifically, it contains most of the definition for the PIU behavior associated with memory accesses initiated by the local processor.

Fura, David A.↗
NASA NTRS1997

Reduced Navier Stokes Relaxation Procedures for Internal Flows

In spite of significant advancement in the field of high speed computing, flow calculations involving complex geometries and/or flow behavior still require large amounts of CPU time and memory. In order to predict such flows without sacrificing grid convergence and accuracy, adaptive gridding techniques that provide optimal resolution are highly desirable. The present work combines multigrid techniques and domain decomposition concepts to provide local, solution adaptive, grid refinement. Several viscous compressible and incompressible, two and three-dimensional, flows with strong inviscid interaction and/or axial flow reversal, are considered with a segmented multigrid domain decomposition (SMGDD) procedure for which uniform meshes result in each domain. A pressure-based form of flux-vector splitting is applied to the Navier-Stokes equations, which are represented by an implicit lowest-order reduced Navier-Stokes (RNS) system and a purely diffusive, higher-order, deferred-corrector. A trapezoidal or box-like form of discretization insures that all mass conservation properties are satisfied at interfacial and outflow boundaries, even for this primitive-variable non-staggered grid computation. The SMGDD technique presented herein has previously been applied for incompressible two dimensional flows. The present work offers improvement in the gridding strategy, by allowing for disjoint subdomains that provide optimal resolution of disparate flow features. It also extends the SMGDD technique to three dimensional compressible flows. Laminar and turbulent flow in a backward facing step channel is considered; although the procedure is applicable to more severe geometries. The standard K-epsilon model is applied for turbulence closure. For Re greater than 400, differences between two-dimensional theory and experiment are resolved through a three dimensional simulation, which confirms the experimentally observed three dimensionality of the recirculation patterns on the upper and lower surfaces.

Rubin, Stanley G.↗
NASA NTRS1987

A neurocomputer based on an analog-digital hybrid architecture

A novel analog-digital hybrid architecture based on the utilization of high density digital random access memories for the storage of the synaptic weights of a neural network, and high speed analog hardware to perform neural computation is described. An electronic neurocomputer based on such an architecture is ideally suited for investigating the dynamics, associative recall properties, and computational capabilities of neural networks and provides significant speed improvement in comparison to conventional software based neural network simulations. As a demonstration of the feasibility of the hybrid architectural concept, a prototype breadboard hybrid neurocomputer system with 32 neurons has been designed and fabricated with off-the-shelf hardware components. The performance of the breadboard system has been tested for variety of applications including associative memory and combinatorial problem solving such as Graph Coloring, and is discussed in this paper.

Moopenn, A.↗
NASA NTRS1990

Multi-processing on supercomputers for computational aerodynamics

The MIMD concept is applied, through multitasking, with relatively minor modifications to an existing code for a single processor. This approach maps the available memory to multiple processors, exploiting the C-FORTRAN-Unix interface. An existing single processor algorithm is mapped without the need for developing a new algorithm. The procedure of designing a code utilizing this approach is automated with the Unix stream editor. A Multiple Processor Multiple Grid (MPMG) code is developed as a demonstration of this approach. This code solves the three-dimensional, Reynolds-averaged, thin-layer and slender-layer Navier-Stokes equations with an implicit, approximately factored and diagonalized method. This solver is applied to a generic, oblique-wing aircraft problem on a four-processor computer using one process for data management and nonparallel computations and three processes for pseudotime advance on three different grid systems.

Yarrow, Maurice↗
NASA NTRS1979

The solution of the three-dimensional viscous-compressible Navier-Stokes equations on a vector computer

The development of a vectorized computer code for the solution of the three-dimensional viscous-compressible Navier-Stokes equations is described. The code is applied on the CDC STAR-100 vector computer which is capable of achieving high result rates when a high degree of parallelism is present in the computations. The computational technique is an explicit time-split MacCormack predictor-corrector algorithm. Since a large volume of data is processed and virtual memory utilized, a data management scheme based on interleaving is used. The program has been applied to obtain the solution of the laminar supersonic flow about a family of three-dimensional corners. The equations of motion are expressed in a generalized form relative to a uniform rectangular computational domain. The metric coefficient and boundary conditions must be supplied for the corresponding physical domain. For calculations with 30,000 grid points, a computational rate of 0.00015 seconds per grid point per time step is observed.

Smith, R. E.↗
NASA NTRS1992

Content addressable memory project

A parameterized version of the tree processor was designed and tested (by simulation). The leaf processor design is 90 percent complete. We expect to complete and test a combination of tree and leaf cell designs in the next period. Work is proceeding on algorithms for the computer aided manufacturing (CAM), and once the design is complete we will begin simulating algorithms for large problems. The following topics are covered: (1) the practical implementation of content addressable memory; (2) design of a LEAF cell for the Rutgers CAM architecture; (3) a circuit design tool user's manual; and (4) design and analysis of efficient hierarchical interconnection networks.

Hall, J. Storrs↗