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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 991 records · Page 55

SEE and TID extension testing of the Xilinx XQR18V04 4Mbit radiation hardened configuration PROM

The XQR18V04 was evaluated for single event upset rates using proton and heavy ions. The PROM was demonstrated to be immune to latch-up, as well as to static upset in the flash memory cells, to an LET > 125 MeV/mg/cmz (effective). The PROM was also tested in a dynamic mode, which revealed three distinct error modes: Read Bit Errors, Address Errors, and a Single Event Functional Interrupt (SEW which affected the data output drivers. Saturation cross-sections, and onset thresholds, for these errorinodes were measured at the heavy ion facility at Texas A&M University, and the proton facility at UC Davis. Additional testing was performed at UC Davis and the Cobalt 60 source at McClellan Air Force Base to examine the effect to TID life as a function of power biasing. The PROM demonstrated a 100% improvement in total TID life with an 84% percent decrease in device usage.

FPGA Virtex II SEU↗

Observations on the Presumed LET Dependence of SEGR

Single-event gate rupture (SEGR)in vertical power MOSFETs is induced by charge deposited in the epitaxial region (below the gate oxide) in concert with the weakening of the oxide, both are a result of the ion passage.

Single-event gate rupture SEGR vertical power MOSF↗

Compendium of Single Event Failures in Power MOSFETs

This compendium of SEGR and SEB data organizes results from several laboratories comparing failure thresholds for several different manufacturers and technologies. The results of this compendium are aimed at the designer to show the possible variations between manufacturers and processes.

Single Event Failures MOSFETs SEGR SEB↗

Evaluation of Radiation Effects in Flash Memories

Features of flash memories: Flash memories are non-volatile; that is they do not require power to retain the information in its memory. They can be erased and written to while the device is still in the circuit.

Radiation effects↗

Impact of CMOS Scaling on Single-Event Hard Errors in Space Systems

Applications of highly scaled devices in space applications are shown to be limited by hard errors from cosmic rays. Hard errors were first observed in 0.8 (micro)m DRAMs. For feature sizes below 0.5 (micro)m, scaling theory predicts that low power devices will have much lower hard error rates than devices optimized for high speed.

CMOS Scaling↗