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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 991 records · Page 55
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Holographic data storage crystals for the LDEF

Lithium niobate is a significant electro-optic material, with potential applications in ultra high capacity storage and processing systems. Lithium niobate is the material of choice for many integrated optical devices and holographic mass memory systems. For crystals of lithium niobate were passively exposed to the space environment of the Long Duration Exposure Facility (LDEF). Three of these crystals contained volume holograms. Although the crystals suffered the surface damage characteristics of most of the other optical components on the Georgia Tech tray, the crystals were recovered intact. The holograms were severely degraded because of the lengthy exposure, but the bulk properties are being investigated to determine the spaceworthiness for space data storage and retrieval systems.

Callen, W. Russell↗
NASA NTRS1993

Acoustic charge transport technology investigation for advanced development transponder

Acoustic charge transport (ACT) technology has provided a basis for a new family of analog signal processors, including a programmable transversal filter (PTF). Through monolithic integration of ACT delay lines with GaAs metal semiconductor field effect transistor (MESFET) digital memory and controllers, these devices significantly extend the performance of PTF's. This article introduces the basic operation of these devices and summarizes their present and future specifications. The production and testing of these devices indicate that this new technology is a promising one for future space applications.

Kayalar, S.↗
NASA NTRS1984

NSC 800, 8-bit CMOS microprocessor

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.↗
NASA NTRS1999

Thin Film Li Ion Microbatteries for NASA Applications

Rechargeable thin film microbatteries have recently become the topic of widespread research for use in low power applications such as battery-backed CMOS memory, miniaturized implantable medical devices and smart cards. In particular, the Center for Integrated Space Microsystems (CISM) at NASA's Jet Propulsion Laboratory has interest in applying this technology for secondary power systems in miniaturized satellites, microsensors, microactuators and other remote MEMS applications. The general requirements of the microbatteries for these applications are high specific energy, wide range of temperature stability. low self-discharge rate, and flexibility of cell design. The thin film Li ion materials system using LiCoO2(LiPO(x)N(1-x))SnO is expected to fulfill these requirements.

West, W. C.↗
NASA NTRS2016

Enhancing the Cassini Mission Through FP Applications After Launch

Although rigorous pre-emptive measures are taken to preclude failures and anomalous conditions from occurring in JPL spacecraft missions prior to launch, unforeseeable problems can still surface after liftoff. In the case of the Cassini/Huygens Mission-to-Saturn spacecraft, several problems were observed post-launch: 1) immediately after takeoff, the collected engineering/science data stored on the Solid State Recorders (SSR) contained a significantly higher number of corrupted bits than was expected (considerably over spec) due to human error in the memory mapping of these devices, 2) numerous Solid State Power Switches (SSPS) sporadically tripped off throughout the mission due to cosmic ray bombardment from the unique space environment, and 3) false assumptions in the pressure regulator design in combination with missing heritage test data led to inaccurate design conclusions, causing the issuance of two waivers for the regulator to close properly (a potentially mission catastrophic single-point failure which occurred 24 days after launch) - amongst other problems. For Cassini, some of these anomalies led to arduous work-arounds or required continuous monitoring of telemetry variables by the ground-based Spacecraft Operations Flight Support (SOFS) team in order to detect and fix fault occurrences as they happened. Fortunately, sufficient funding and schedule margin allowed several Fault Protection (FP) solutions to be implemented into post-launch Flight Software (FSW) uploads to help resolve these issues autonomously, reducing SOFS ground support efforts while improving anomaly recovery time in order to preserve maximum science capture. This paper details the FP applications used to resolve the above issues as well as to optimize solutions for several other problems experienced by the Cassini spacecraft during its fight, in order to enhance the spacecraft's overall mission success throughout the 18 years of its 20 year expedition to and within the Saturnian system.

fault protection↗
DOE OSTI2016

Methods for resistive switching of memristors

The present invention is directed generally to resistive random-access memory (RRAM or ReRAM) devices and systems, as well as methods of employing a thermal resistive model to understand and determine switching of such devices. In particular example, the method includes generating a power-resistance measurement for the memristor device and applying an isothermal model to the power-resistance measurement in order to determine one or more parameters of the device (e.g., filament state).

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2014

OpenSoC Fabric

Recent advancements in technology scaling have shown a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation proves insufficient to study the tradeoffs in such complex systems due to slow execution time, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, an on-chip network generation infrastructure which aims to provide a parameterizable and powerful on-chip network generator for evaluating future high performance computing architectures based on SoC technology. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by its base language, Scala, and generates both software (C++) and hardware (Verilog) models from a single code base. The OpenSoC Fabric2 infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, and follows object-oriented design and functional programming to make functionality extension as easy as possible.

Source record↗
DOE OSTI2022

From PeleC to PeleACC, to PeleC++

PeleC is an Exascale Computing Project application for simulating compressible combustion in complex geometries. It has been built on top of the popular AMReX library. In the beginning of the Exascale Computing Project, PeleC was focused on KNL. It uses a mixture of C++, C, and kernels written in Fortran to obtain performance by focusing on vectorization. Recently we have taken two approaches in deciding PeleC's future for obtaining performance on exascale GPU machines. In the first programming model, we decorated the Fortran kernels with OpenACC directives. This expedited our ability to run at large scales on Summit's GPUs, where we achieved a significant speedup over the CPUs on Summit. The second programming model involved rewriting the Fortran kernels in C++ and using AMReX's Kokkos-like lambda abstractions for running on the GPU. This resulted in similar speedups on Summit's GPUs over merely utilizing the CPUs. Both approaches involved AMReX's management of memory transfers between the device and host. In this work, we compare and contrast the benefits and pitfalls to both programming approaches regarding performance, performance portability, and productivity. We also discuss advantages we have found in taking the time to modernize our code and why have chosen a specific pathway to prepare our code for the future DOE exascale machines.

exascale computing↗
DOE OSTI2011

Dielectric and ferroelectric properties of lanthanum doped SrBi{sub 4}Ti{sub 4}O{sub 15} ferroelectric ceramics

Bismuth layer structure ferroelectrics (BLSFs) have attracted intensive investigation for the potential use in non volatile ferroelectric random access memory (FeRAM) and piezoelectric devices suitable at high temperature. Bismuth layered structured compounds with general formula of (Bi{sub 2}O{sub 2}){sup 2+} (A{sub m-1}B{sub m}O{sub 3m+1}){sup 2-} are firstly found by Aurivillius. The structure of these compounds can be described as pseudo-perovskite (A{sub m-1}B{sub m}O{sub 3m+1}){sup 2-} slabs separated by (Bi{sub 2}O{sub 2}){sup 2+} layers along the crystallographic c-axis. The 12-coordinated A site can be occupied by such cations as La{sup 3+}, Bi{sup 3+}, Ba{sup 2+}, Sr{sup 2+}, Pb{sup 2+}, Ca{sup 2+}, Na{sup +}, etc. While the octahedral-coordinated B site can be occupied by W{sup 6+}, Nb{sup 5+}, Ta{sup 5+}, Ti{sup 4+} etc. Lanthanum substituted BiT (Bi{sub 4}Ti{sub 4}O{sub 12}) known as BLT has been extensively investigated. With this substitution, BLT shows relatively large P{sub r}, low synthesis temperature and good fatigue endurance which makes it a potential candidate for FeRAM application. So, lanthanum doping is an effective way to improve the ferroelectric and fatigue properties of Bi{sub 4}Ti{sub 4}O{sub 12}. Lanthanum doped Bismuth layer structure ferroelectrics (BLSFs) ceramics SrBi{sub 4-x}La{sub x}Ti{sub 4}O{sub 15} (x=0, 0.025, 0.050, 0.075, 0.1) were prepared by solid state reaction method. X-ray diffraction pattern showed that single phase was formed when x=0-0.1. Morphological studies were carried out by SEM analysis. It was found that crystal lattice constant, dielectric and electrical properties of SBT ferroelectrics varied appreciably with amount of doping. Dielectric measurements in the frequency range 100Hz-1MHz were made using an impedance analyzer (Wayne Kerr 6500P) and the measurements were carried out from RT to 600 deg C. The ferroelectric hysteresis loop was traced at room temperature by a standard P-E loop tracer based on sawyer-tower circuit. The values of 2P{sub r} and E{sub c} for pure and lanthanum doped SBT are given. The above results indicate that La{sup 3+} modification is an effective way to improve the ferro electrical properties of SrBi{sub 4}Ti{sub 4}O{sub 15}. The transition temperature (T{sub c}) and dielectric constant for SrBi{sub 4}Ti{sub 4}O{sub 15} are given. It is observed that with the increasing of lanthanum content remnant polarization increases and coercive field decreases. It is believed that these materials are potentially attractive candidates for FeRAM industry.

36 MATERIALS SCIENCE↗
DOE OSTI2024

The Tiny Median Filter: A Small Size, Flexible Arbitrary Percentile Finder Scheme Suitable for FPGA Implementation

This document reports the design, implementation and testing of a small silicon resource usage, very flexible arbitrary percentile finding scheme called the Tiny Median Filter. It can be used not only as a median filter in image processing with square filtering windows, but also for applications of any percentile filter or maximum or minimum finder with any size of data set as long as the number of bits of the data is finite. It opens possibilities for image processing tasks with non-square or irregular filter windows. In this scheme, data swapping or data bit manipulating are avoided and high functional efficiency of the logic components is applied to save silicon resources. Some logic functions are absorbed into other functions to further reduce the complexity. The combinational logic paths are designed to be sufficiently short so that the firmware can be compiled to the maximum operating frequency allowed by the block memories of the FPGA devices. The Tiny Median Filter receives, processes and output data in non-stop manner with no irregular timing which helps to simplify design of surrounding stages.

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)↗
NASA NTRS1987

Quantification of the memory imprint effect for a charged particle environment

The effects of total accumulated dose on the single-event vulnerability of NMOS resistive-load SRAMs are investigated. The bias-dependent shifts in device parameters can imprint the memory state present during exposure or erase the imprinted state. Analysis of these effects is presented along with an analytic model developed for the quantification of these effects. The results indicate that the imprint effect is dominated by the difference in the threshold voltage of the n-channel devices.

Bhuva, B. L.↗
DOE OSTI2010

Quantum throughput: Quantifying quantum-communication devices with homodyne measurements

Quantum communication relies on optical implementations of channels, memories, and repeaters. In the absence of perfect devices, a minimum requirement on real-world devices is that they preserve quantum correlations, meaning that they have some throughput of a quantum-mechanical nature. Previous work has verified throughput in optical devices while using minimal resources. We extend this approach to the quantitative regime. Our method is illustrated in a setting where the input consists of two coherent states while the output is measured by two homodyne measurement settings.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Resistive memory switching in ultrathin TiO{sub 2} films grown by atomic layer deposition

Electric field controlled forming free and unipolar resistive memory switching was observed in Au/TiO{sub 2}/Pt devices containing ultrathin TiO{sub 2} films of thickness ~ 4 nm grown by atomic layer deposition. These devices showed a large resistance ratio of ~ 10{sup 3} between high and low resistance states along with appreciable time retention for ~ 10{sup 4} seconds and endurance. The spread of reset and set voltages was from ~ 0.4-0.6 V and 1.1-1.5 V respectively with a clear window between them. The resistive switching mechanism was explained based on conductive filamentary model.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2011

Distributed non-equilibrium Green’s function algorithms for the simulation of nanoelectronic devices with scattering

Through the non-equilibrium Green’s function (NEGF) formalism, quantum-scale device simulation can be performed with the inclusion of electron-phonon scattering. Yet, the simulation of realistically sized devices under the NEGF formalism typically requires prohibitive amounts of memory and computation time. Two of the most demanding computational problems for NEGF simulation involve mathematical operations with structured matrices called semiseparable matrices. In this work, we present parallel approaches for these computational problems which allow for efficient distribution of both memory and computation based upon the underlying device structure. This is vital when simulating realistically sized devices due to the aforementioned computational burdens. First, we consider determining a distributed compact representation for the retarded Green’s function matrix G R . This compact representation is exact and allows for any entry in the matrix to be generated through the inherent semiseparable structure. The second parallel operation allows for the computation of electron density and current characteristics for the device. Specifically, matrix products between the distributed representation for the semiseparable matrix G R and the self-energy scattering terms in Σ < produce the less-than Green’s function G < . As an illustration of the computational efficiency of our approach, we stably generate the mobility for nanowires with cross-sectional sizes as large as 4.5 nm, assuming an atomistic model with scattering.

47 OTHER INSTRUMENTATION↗
DOE OSTI2014

Self-selection bipolar resistive switching phenomena observed in NbON/NbN bilayer for cross-bar array memory applications

In this letter, to integrate bipolar resistive switching cells into cross bar array (CBA) structure, we study one-selector (1S) and one-resistor (1R) behavior of a niobium oxynitride (NbON) and niobium nitride (NbN) bilayer for the applications of resistive random access memory (RRAM). In this structure, a NbN layer exhibits bipolar switching characteristics while a NbON layer acts as the selector. The NbN-based 1S1R devices within a single RRAM memory cell can be directly integrated into a CBA structure without the need of extra diodes; this can significantly reduce the fabrication complexity.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS1999

SRAM Based Re-programmable FPGA for Space Applications

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

Wang, J. J.↗
DOE OSTI2017

Solution Monolayer Epitaxy for Tunable Atomically Sharp Oxide Interfaces

Abstract Interfaces play an important role in a variety of devices including transistors, solar cells, and memory components. Atomically sharp interfaces are essential to avoid charge traps that hamper efficient device operation. Sharp interfaces usually require thin‐film fabrication techniques involving ultrahigh vacuum and high substrate temperatures. A new self‐limiting wet chemical process for deposition of epitaxial layers from alkoxide precursors is presented. This method is fast, cheap, and yields perfect interfaces as validated by various analysis techniques. It allows the growth of heterostructures with half‐unit‐cell resolution. The method is demonstrated by designing a hole‐type oxide interface SrTiO 3 /BaO/LaAlO 3 . It is shown that transport through this interface exhibits properties of mixed electron–hole contributions with hole mobility exceeding that of electrons.

Ron, Alon↗