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All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗
DOE OSTI2021

Hybrid integrated photonic platforms: opinion

While photonic integration has made remarkable progress in recent years, there is no one integrated photonic platform that offers all desired functionalities and manufacturability on the same platform. GaAs and InP-based optoelectronic integrated circuits (OEICs) were very popular in the past decades; however, silicon photonics has recently emerged as a preferred platform due to its high-density and high-yield manufacturability leveraging the CMOS ecosystem, although it lacks optical gain, the Pockels effect, and other characteristics. On the other hand, hybrid photonic integration adds new and diverse functionalities to the host materials like silicon. This opinion paper investigates hybrid integrated photonic platforms, and discusses the new functionalities added to the silicon CMOS photonic platform.

42 ENGINEERING↗
NASA NTRS2003

Development of a 1K x 1K GaAs QWIP Far IR Imaging Array

In the on-going evolution of GaAs Quantum Well Infrared Photodetectors (QWIPs) we have developed a 1,024 x 1,024 (1K x1K), 8.4-9 microns infrared focal plane array (FPA). This 1 megapixel detector array is a hybrid using the Rockwell TCM 8050 silicon readout integrated circuit (ROIC) bump bonded to a GaAs QWIP array fabricated jointly by engineers at the Goddard Space Flight Center (GSFC) and the Army Research Laboratory (ARL). The finished hybrid is thinned at the Jet Propulsion Lab. Prior to this development the largest format array was a 512 x 640 FPA. We have integrated the 1K x 1K array into an imaging camera system and performed tests over the 40K-90K temperature range achieving BLIP performance at an operating temperature of 76K (f/2 camera system). The GaAs array is relatively easy to fabricate once the superlattice structure of the quantum wells has been defined and grown. The overall arrays costs are currently dominated by the costs associated with the silicon readout since the GaAs array fabrication is based on high yield, well-established GaAs processing capabilities. In this paper we will present the first results of our 1K x 1K QWIP array development including fabrication methodology, test data and our imaging results.

Jhabvala, M.↗
NASA NTRS1999

Experiments on Evolving Software Models of Analog Circuits

Analog circuits are of great importance in electronic system design since the world is fundamentally analog in nature. While the amount of digital design activity far outpaces that of analog design, most digital systems require analog modules for interfacing with the external world. It was recently estimated that approximately 60% of digital application- specific integrated circuit designs incorporated analog circuits. With challenging analog circuit design problems and few analog design engineers, there are economic reasons for automating the analog design process, especially time-to-market considerations. Techniques for analog circuit design automation began appearing about two decades ago. These methods incorporated heuristics [6], knowledge bases [1], simulated annealing [5], and other algorithms. Efforts using techniques from evolutionary computation began appearing over the last few years. These include the use of genetic algorithms to select electronic component values (for example, the resistance value of a resistor), to select circuit topologies, and to design amplifiers using a limited set of canned topologies [4]. A genetic programming-based analog circuit design system has been demonstrated in which the circuit sizes, component values, and the circuit topologies are determined automatically [3]. The genetic-algorithm systems typically represent circuit structures as vectors of parameters encoded in binary strings, while the genetic programming system manipulates tree data structures.

Lohn, Jason D.↗
NASA NTRS2011

Infrared-Bolometer Arrays with Reflective Backshorts

Integrated circuits that incorporate square arrays of superconducting-transition- edge bolometers with optically reflective backshorts are being developed for use in image sensors in the spectral range from far infrared to millimeter wavelengths. To maximize the optical efficiency (and, thus, sensitivity) of such a sensor at a specific wavelength, resonant optical structures are created by placing the backshorts at a quarter wavelength behind the bolometer plane. The bolometer and backshort arrays are fabricated separately, then integrated to form a single unit denoted a backshort-under-grid (BUG) bolometer array. In a subsequent fabrication step, the BUG bolometer array is connected, by use of single-sided indium bump bonding, to a readout device that comprises mostly a superconducting quantum interference device (SQUID) multiplexer circuit. The resulting sensor unit comprising the BUG bolometer array and the readout device is operated at a temperature below 1 K. The concept of increasing optical efficiency by use of backshorts at a quarter wavelength behind the bolometers is not new. Instead, the novelty of the present development lies mainly in several features of the design of the BUG bolometer array and the fabrication sequence used to implement the design. Prior to joining with the backshort array, the bolometer array comprises, more specifically, a square grid of free-standing molybdenum/gold superconducting-transition-edge bolometer elements on a 1.4- m-thick top layer of silicon that is part of a silicon support frame made from a silicon-on-insulator wafer. The backshort array is fabricated separately as a frame structure that includes support beams and contains a correspond - ing grid of optically reflective patches on a single-crystal silicon substrate. The process used to fabricate the bolometer array includes standard patterning and etching steps that result in the formation of deep notches in the silicon support frame. These notches are designed to interlock with the support beams on the backshort-array structure to provide structural support and precise relative positioning. The backshort-array structure is inserted in the silicon support frame behind the bolometer array, and the notches in the frame serve to receive the support beams of the backshort-array structure and thus determine the distance between the backshort and bolometer planes. The depth of the notches and, thus, the distance between the backshort and bolometer planes, can be tailored to a value between 25 to 300 m adjusting only a few process steps. The backshort array is designed so as not to interfere with the placement of indium bumps for subsequent indium bump-bonding to the multiplexing readout circuitry

Miller, Timothy M.↗
DOE OSTI2022

Reconfigurable quantum phononic circuits via piezo-acoustomechanical interactions

Abstract We show that piezoelectric strain actuation of acoustomechanical interactions can produce large phase velocity changes in an existing quantum phononic platform: aluminum nitride on suspended silicon. Using finite element analysis, we demonstrate a piezo-acoustomechanical phase shifter waveguide capable of producing ± π phase shifts for GHz frequency phonons in 10s of μm with 10s of volts applied. Then, using the phase shifter as a building block, we demonstrate several phononic integrated circuit elements useful for quantum information processing. In particular, we show how to construct programmable multi-mode interferometers for linear phononic processing and a dynamically reconfigurable phononic memory that can switch between an ultra-long-lifetime state and a state strongly coupled to its bus waveguide. From the master equation for the full open quantum system of the reconfigurable phononic memory, we show that it is possible to perform read and write operations with over 90% quantum state transfer fidelity for an exponentially decaying pulse.

Taylor, Jeffrey C. (ORCID:0000000215982436)↗
NASA NTRS2003

Electronic Components and Circuits for Extreme Temperature Environments

Planetary exploration missions and deep space probes require electrical power management and control systems that are capable of efficient and reliable operation in very low temperature environments. Presently, spacecraft operating in the cold environment of deep space carry a large number of radioisotope heating units in order to maintain the surrounding temperature of the on-board electronics at approximately 20 C. Electronics capable of operation at cryogenic temperatures will not only tolerate the hostile environment of deep space but also reduce system size and weight by eliminating or reducing the radioisotope heating units and their associate structures; thereby reducing system development as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results from better behavior and tolerance in the electrical and thermal properties of semiconductor and dielectric materials at low temperatures. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical components, circuits, and systems suitable for applications in the aerospace environment and deep space exploration missions. Research is being conducted on devices and systems for reliable use down to cryogenic temperatures. Some of the commercial-off-the-shelf as well as developed components that are being characterized include switching devices, resistors, magnetics, and capacitors. Semiconductor devices and integrated circuits including digital-to-analog and analog-to-digital converters, DC/DC converters, operational amplifiers, and oscillators are also being investigated for potential use in low temperature applications. An overview of the NASA Glenn Research Center Low Temperature Electronic Program will be presented in this paper. A description of the low temperature test facilities along with selected data obtained through in-house component and circuit testing will also be discussed. Ongoing research activities that are being performed in collaboration with various organizations will also be presented.

Patterson, Richard L.↗
DOE OSTI2023

Studies in pulse shape discrimination for an optimized ASIC design

The continued advancements of Silicon Photomultipliers (SiPMs) have made them viable photosensors for low recoil energy Pulse Shape Discrimination (PSD) between fast neutron and gamma interactions when coupled to an appropriate scintillator. At the same time, the large number of channels in a typical array calls for the development of low-cost and low-power electronics. A custom integrated circuit (ASIC) is an ideal solution for this purpose. To assess the requirements for such an ASIC, studies were performed using two scintillators, Stilbene and EJ-276, coupled to a 6 x 6 mm SiPM from Onsemi. We demonstrate that both scintillators are viable for performing PSD for interaction energies from 100 keV to several MeV while optimizing the integration periods used in the PSD metric. These measurements inform the design parameters of the ASIC under development.

Si-PMTs↗
DOE OSTI2026

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗
NASA NTRS2002

Cryogenic Electronics Being Developed for Space Operation

Planetary exploration missions and deep space probes require electrical power management and control systems that can operate efficiently and reliably in very low temperature environments. Presently, spacecraft operating in the cold environment of deep space carry a large number of radioisotope heating units to maintain the surrounding temperature of the onboard electronics at approximately 20 C. Electronics capable of operation at cryogenic temperatures would not only tolerate the hostile environment of deep space but also reduce system size and weight by eliminating or reducing the radioisotope heating units and their associate structures. Thereby, such electronics would reduce system development as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results because semiconductor and dielectric materials have better behavior and tolerance in their electrical and thermal properties at low temperatures. The Low Temperature Electronics Program at the NASA Glenn Research Center is focusing on the research and development of electrical components, circuits, and systems suitable for applications in the aerospace environment and in deep space exploration missions. Research is being conducted on devices and systems for reliable use down to cryogenic temperatures. Some of the commercial off-the-shelf as well as developed components that are being characterized include semiconductor switching devices, resistors, magnetics, and capacitors. Semiconductor devices and integrated circuits including digital-to-analog and analog-to-digital converters, dc-dc converters, operational amplifiers, and oscillators are also being investigated for potential use in low-temperature applications. For example, the output response of an advanced oscillator at room temperature and at -190 C is shown. Most oscillators can operate at temperatures down to only -55 C. It can be seen that, for this oscillator, the low temperature of -196 C changed the leading and trailing edges of the oscillator pulses by producing overshoot. The research and development efforts performed under the Low Temperature Electronics Program at Glenn are being carried out through collaboration with other Government agencies, industrial and aerospace companies, and academia. The program supports missions as well as technology development efforts at NASA's Goddard Space Flight Center and Langley Research Center, and the Jet Propulsion Laboratory.

Patterson, Richard L.↗
DOE OSTI2024

Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors

Dynamically field-programmable qubit arrays (DPQA) have recently emerged as a promising platform for quantum information processing. In DPQA, atomic qubits are selectively loaded into arrays of optical traps that can be reconfigured during the computation itself. Leveraging qubit transport and parallel, entangling quantum operations, different pairs of qubits, even those initially far away, can be entangled at different stages of the quantum program execution. Such reconfigurability and non-local connectivity present new challenges for compilation, especially in the layout synthesis step which places and routes the qubits and schedules the gates. In this paper, we consider a DPQA architecture that contains multiple arrays and supports 2D array movements, representing cutting-edge experimental platforms. Within this architecture, we discretize the state space and formulate layout synthesis as a satisfiability modulo theories problem, which can be solved by existing solvers optimally in terms of circuit depth. For a set of benchmark circuits generated by random graphs with complex connectivities, our compiler OLSQ-DPQA reduces the number of two-qubit entangling gates on small problem instances by 1.7x compared to optimal compilation results on a fixed planar architecture. To further improve scalability and practicality of the method, we introduce a greedy heuristic inspired by the iterative peeling approach in classical integrated circuit routing. Using a hybrid approach that combined the greedy and optimal methods, we demonstrate that our DPQA-based compiled circuits feature reduced scaling overhead compared to a grid fixed architecture, resulting in 5.1X less two-qubit gates for 90 qubit quantum circuits. These methods enable programmable, complex quantum circuits with neutral atom quantum computers, as well as informing both future compilers and future hardware choices.

Physics↗
NASA NTRSDate not supplied

A Brief Overview of Relevant Silicon Carbide Electronics and Sensor Development for Long Duration Venus Surface Exploration

This presentation concentrates on the potential of long duration Venus surface missions, and the role of Silicon Carbide (SiC) electronics and sensor advancements in such exploration. For example, SiC integrated circuit (IC) electronics have matured to a state where a simple long-life scientific probe is feasible for extended Venus surface operations. These electronics have been demonstrated for more than a year at 500˚C, and 60 days in high-fidelity simulated Venus surface conditions [1-2]. Further, high temperature chemical sensing technology, including SiC-based gas sensors, integrated with SiC electronics can enable future exploration of the Venus surface atmosphere [3]. Continued maturation of these high temperature electronics and sensors has been part of the Long-Lived In-Situ Solar System Explorer (LLISSE) project to provide an operational system for in situ exploration of the Venus surface up to 60 days [4]. A key focus of this work includes increasing the complexity and decreasing the power consumption of the ICs which will pave the way to enhanced capabilities, such as long-duration Venus seismic measurements and other mission capabilities currently under development. This is in parallel to work expanding the capabilities of the sensor technology to provide science measurements on the Venus surface. This presentation will give an overview of possible extended duration Venus surface exploration and some of the SiC-based technologies that can enable this exploration.

high temperature Venus surface electronics sensors↗
DOE OSTI2022

A MEMS Gyroscope for Reliable Long Duration Measurement While Drilling at 300°C

The 300°C Microelectromechanical system (MEMS) gyroscope project aims to contribute to DOE’s goal of increased geothermal drilling efficiency by 2025 through the development of a 300°C MEMS gyroscope for Measurement While Drilling (MWD). At the conclusion of the 2-year project, the team will develop a 300°C capable MEMS gyroscope containing GE’s patented Multi-Ring Gyroscope Transducer (MRGT) design, custom Silicon-On-Insulator (SOI) based frontend and feedback control electronics, and with demonstrated functionality and lifetime beyond 1000 hours. The project is divided into two budget periods with Go/No-Go decision at the end of the first budget period. The goal for the first budget period is to establish the feasibility of the MRGT and electronics design for meeting the 300°C performance requirements. The goal for the second budget period is to integrate the MRGT with the SOI-based application specific integrated circuit (ASIC) and demonstrate capability to operate at 300°C for 1000 hours. In Budget Period 1 we met the phase 1 goal. We successfully validated the combined MRG, electronics and packaging capability entitlement to achieving 0.5 degrees azimuth uncertainty while enabling operation at significantly higher temperatures than the state-of-the-art. In Budget Period 2, we successfully completed the integration of the MRGT and ASIC with associated high temperature, high reliability packaging to demonstrate the performance and functionality of the integrated gyroscope across the temperature range from room temperature to at 300°C. Furthermore, the team demonstrated operating life of >1,000 hours at 300°C, thus providing a validation of application-relevant lifetime capability.

15 GEOTHERMAL ENERGY↗
NASA NTRS2016

Open Source Radiation Hardened by Design Technology

The proposed technology allows use of the latest microcircuit technology with lowest power and fastest speed, with minimal delay and engineering costs, through new Radiation Hardened by Design (RHBD) techniques that do not require extensive process characterization, technique evaluation and re-design at each Moore's Law generation. The separation of critical node groups is explicitly parameterized so it can be increased as microcircuit technologies shrink. The technology will be open access to radiation tolerant circuit vendors. INNOVATION: This technology would enhance computation intensive applications such as autonomy, robotics, advanced sensor and tracking processes, as well as low power applications such as wireless sensor networks. OUTCOME / RESULTS: 1) Simulation analysis indicates feasibility. 2)Compact voting latch 65 nanometer test chip designed and submitted for fabrication -7/2016. INFUSION FOR SPACE / EARTH: This technology may be used in any digital integrated circuit in which a high level of resistance to Single Event Upsets is desired, and has the greatest benefit outside low earth orbit where cosmic rays are numerous.

Shuler, Robert↗
NASA NTRS2008

Inertial Orientation Trackers with Drift Compensation

A class of inertial-sensor systems with drift compensation has been invented for use in measuring the orientations of human heads (and perhaps other, similarly sized objects). These systems can be designed to overcome some of the limitations of prior orientation-measuring systems that are based, variously, on magnetic, optical, mechanical-linkage, and acoustical principles. The orientation signals generated by the systems of this invention could be used for diverse purposes, including controlling head-orientation-dependent virtual reality visual displays or enabling persons whose limbs are paralyzed to control machinery by means of head motions. The inventive concept admits to variations too numerous to describe here, making it necessary to limit this description to a typical system, the selected aspects of which are illustrated in the figure. A set of sensors is mounted on a bracket on a band or a cap that gently but firmly grips the wearer s head to be tracked. Among the sensors are three drift-sensitive rotationrate sensors (e.g., integrated-circuit angular- rate-measuring gyroscopes), which put out DC voltages nominally proportional to the rates of rotation about their sensory axes. These sensors are mounted in mutually orthogonal orientations for measuring rates of rotation about the roll, pitch, and yaw axes of the wearer s head. The outputs of these rate sensors are conditioned and digitized, and the resulting data are fed to an integrator module implemented in software in a digital computer. In the integrator module, the angular-rate signals are jointly integrated by any of several established methods to obtain a set of angles that represent approximately the orientation of the head in an external, inertial coordinate system. Because some drift is always present as a component of an angular position computed by integrating the outputs of angular-rate sensors, the orientation signal is processed further in a drift-compensator software module.

Foxlin, Eric M.↗
NASA NTRS2011

Architecture for a 1-GHz Digital RADAR

An architecture for a Direct RF-digitization Type Digital Mode RADAR was developed at GSFC in 2008. Two variations of a basic architecture were developed for use on RADAR imaging missions using aircraft and spacecraft. Both systems can operate with a pulse repetition rate up to 10 MHz with 8 received RF samples per pulse repetition interval, or at up to 19 kHz with 4K received RF samples per pulse repetition interval. The first design describes a computer architecture for a Continuous Mode RADAR transceiver with a real-time signal processing and display architecture. The architecture can operate at a high pulse repetition rate without interruption for an infinite amount of time. The second design describes a smaller and less costly burst mode RADAR that can transceive high pulse repetition rate RF signals without interruption for up to 37 seconds. The burst-mode RADAR was designed to operate on an off-line signal processing paradigm. The temporal distribution of RF samples acquired and reported to the RADAR processor remains uniform and free of distortion in both proposed architectures. The majority of the RADAR's electronics is implemented in digital CMOS (complementary metal oxide semiconductor), and analog circuits are restricted to signal amplification operations and analog to digital conversion. An implementation of the proposed systems will create a 1-GHz, Direct RF-digitization Type, L-Band Digital RADAR--the highest band achievable for Nyquist Rate, Direct RF-digitization Systems that do not implement an electronic IF downsample stage (after the receiver signal amplification stage), using commercially available off-the-shelf integrated circuits.

Mallik, Udayan↗
DOE OSTI2021

Bound States in the Continuum on a Silicon Chip with Dynamic Tuning

Expanding bound states in the continuum (BIC) beyond photonic crystal systems may enable broader applications benefiting from the unique properties of BIC states. We use photonic integrated circuit to realize a Fabry-Pérot BIC on a silicon chip. The devices consist of cascaded ring resonators with tunable resonance frequencies and phase delays. As a result, the BIC state is dynamically tuned with electrical I/O. We analyze the mechanism of the formation of BIC states in this waveguide system and point out the fundamental differences between the BIC states and electromagnetically induced transparency states in integrated photonics. The high transmission protected by the BIC state enables versatile optical filters, which are capable of independent control over switching, peak position, and quality factor. We also demonstrate the scalability of this platform. As a result, this integrated silicon photonic platform brings opportunities for practical BIC applications.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2011

Fault-Tolerant, Radiation-Hard DSP

Commercial digital signal processors (DSPs) for use in high-speed satellite computers are challenged by the damaging effects of space radiation, mainly single event upsets (SEUs) and single event functional interrupts (SEFIs). Innovations have been developed for mitigating the effects of SEUs and SEFIs, enabling the use of very-highspeed commercial DSPs with improved SEU tolerances. Time-triple modular redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW (very long instruction word) class of parallel processors. TTMR improves SEU rates substantially. SEFIs are solved by a SEFI-hardened core circuit, external to the microprocessor. It monitors the health of the processor, and if a SEFI occurs, forces the processor to return to performance through a series of escalating events. TTMR and hardened-core solutions were developed for both DSPs and reconfigurable field-programmable gate arrays (FPGAs). This includes advancement of TTMR algorithms for DSPs and reconfigurable FPGAs, plus a rad-hard, hardened-core integrated circuit that services both the DSP and FPGA. Additionally, a combined DSP and FPGA board architecture was fully developed into a rad-hard engineering product. This technology enables use of commercial off-the-shelf (COTS) DSPs in computers for satellite and other space applications, allowing rapid deployment at a much lower cost. Traditional rad-hard space computers are very expensive and typically have long lead times. These computers are either based on traditional rad-hard processors, which have extremely low computational performance, or triple modular redundant (TMR) FPGA arrays, which suffer from power and complexity issues. Even more frustrating is that the TMR arrays of FPGAs require a fixed, external rad-hard voting element, thereby causing them to lose much of their reconfiguration capability and in some cases significant speed reduction. The benefits of COTS high-performance signal processing include significant increase in onboard science data processing, enabling orders of magnitude reduction in required communication bandwidth for science data return, orders of magnitude improvement in onboard mission planning and critical decision making, and the ability to rapidly respond to changing mission environments, thus enabling opportunistic science and orders of magnitude reduction in the cost of mission operations through reduction of required staff. Additional benefits of COTS-based, high-performance signal processing include the ability to leverage considerable commercial and academic investments in advanced computing tools, techniques, and infra structure, and the familiarity of the science and IT community with these computing environments.

Czajkowski, David↗