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NASA NTRS2005

Human Factors and ISS Medical Systems: Highlights of Procedures and Equipment Findings

As part of the Space Human Factors Engineering Critical Questions Roadmap, a three year Technology Development Project (TDP) was funded by NASA Headquarters to examine emergency medical procedures on ISS. The overall aim of the emergency medical procedures project was to determine the human factors issues in the procedures, training, communications and equipment, and to recommend solutions that will improve the survival rate of crewmembers in the event of a medical emergency. Currently, each ISS crew remains on orbit for six month intervals. As there is not standing requirement for a physician crewmember, during such time, the maintenance of crew health is dependant on individual crewmembers. Further, in the event of an emergency, crew will need to provide prolonged maintenance care, as well as emergency treatment, to an injured crewmember while awaiting transport to Earth. In addition to the isolation of the crew, medical procedures must be carried out within the further limitations imposed by the physical environment of the space station. For example, in order to administer care on ISS without the benefit of gravity, the Crew Medical Officers (CMOs) must restrain the equipment required to perform the task, restrain the injured crewmember, and finally, restrain themselves. Both the physical environment and the physical space available further limit the technology that can be used onboard. Equipment must be compact, yet able to withstand high levels of radiation and function without gravity. The focus here is to highlight the human factors impacts from our three year project involving the procedures and equipment areas that have been investigated and provided valuable to ISS and provide groundwork for human factors requirements for medical applications for exploration missions.

Byrne, V. E.↗

NASA NTRS2008

Analysis of Single-Event Latchup Cross Section in 65 nm SRAMs

Single event latchup (SEL) in a 65 nm CMOS SRAM technology is observed and sensitivity is shown to be a strong function of lateral beam orientation, angle of incidence, and temperature. The significance of these results are discussed and the foundation for a predictive model of SEL is laid out for use with the MRED tool.

Hutson, J. M.↗

NASA NTRS2007

Radiation Test Challenges for Scaled Commerical Memories

As sub-100nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this talk, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art Flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are volatile. Due to their very high bit density, these device types are highly desirable for use in the natural space environment. In this presentation, we shall discuss these devices with emphasis on considerations for test and qualification methods required.

LaBel, Kenneth A.↗

NASA NTRS2008

Development and Operation of the Microshutter Array System

The microshutter array (MSA) is a key component in the James Webb Space Telescope Near Infrared Spectrometer (NIRSpec) instrument. The James Webb Space Telescope is the next generation of a space-borne astronomy platform that is scheduled to be launched in 2013. However, in order to effectively operate the array and meet the severe operational requirements associated with a space flight mission has placed enormous constraints on the microshutter array subsystem. This paper will present an overview and description of the entire microshutter subsystem including the microshutter array, the hybridized array assembly, the integrated CMOS electronics, mechanical mounting module and the test methodology and performance of the fully assembled microshutter subsystem. The NIRSpec is a European Space Agency (ESA) instrument requiring four fully assembled microshutter arrays, or quads, which are independently addressed to allow for the imaging of selected celestial objects onto the two 4 mega pixel IR detectors. Each microshutter array must have no more than approx.8 shutters which are failed in the open mode (depending on how many are failed closed) out of the 62,415 (365x171) total number of shutters per array. The driving science requirement is to be able to select up to 100 objects at a time to be spectrally imaged at the focal plane. The spectrum is dispersed in the direction of the 171 shutters so if there is an unwanted open shutter in that row the light from an object passing through that failed open shutter will corrupt the spectrum from the intended object.

Jhabvala, M. D.↗

NASA NTRS2006

Fault Tolerance Implementation within SRAM Based FPGA Designs based upon Single Event Upset Occurrence Rates

Emerging technology is enabling the design community to consistently expand the amount of functionality that can be implemented within Integrated Circuits (ICs). As the number of gates placed within an FPGA increases, the complexity of the design can grow exponentially. Consequently, the ability to create reliable circuits has become an incredibly difficult task. In order to ease the complexity of design completion, the commercial design community has developed a very rigid (but effective) design methodology based on synchronous circuit techniques. In order to create faster, smaller and lower power circuits, transistor geometries and core voltages have decreased. In environments that contain ionizing energy, such a combination will increase the probability of Single Event Upsets (SEUs) and will consequently affect the state space of a circuit. In order to combat the effects of radiation, the aerospace community has developed several "Hardened by Design" (fault tolerant) design schemes. This paper will address design mitigation schemes targeted for SRAM Based FPGA CMOS devices. Because some mitigation schemes may be over zealous (too much power, area, complexity, etc.. . .), the designer should be conscious that system requirements can ease the amount of mitigation necessary for acceptable operation. Therefore, various degrees of Fault Tolerance will be demonstrated along with an analysis of its effectiveness.

Berg, Melanie↗

NASA NTRS2008

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

At an earlier conference we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art CMOS technologies. In this presentation, we extend this discussion focusing on the following areas: (1) Device packaging, (2) Evolving physical single even upset mechanisms, (3) Device complexity, and (4) the goal of understanding the limitations and interpretation of radiation testing results.

LaBel, Kenneth A.↗

NASA NTRS2007

A One Chip Hardened Solution for High Speed SpaceWire System Implementations. Session: Components

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASIC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a router with 4 SpaceWire ports and two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, and a memory controller for additional external memory use. The SpaceWire cores are also reused in other ASICs under development. The SpaceWire ASIC is planned for use on the Geostationary Operational Environmental Satellites (GOES)-R, the Lunar Reconnaissance Orbiter (LRO) and other missions. Engineering and flight parts have been delivered to programs and users. This paper reviews the SpaceWire protocol and those elements of it that have been built into the current and next SpaceWire reusable cores and features within the core that go beyond the current standard and can be enabled or disabled by the user. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be reviewed and highlighted. Optional configurations within user systems and test boards will be shown. The physical implementation of the design will be described and test results from the hardware will be discussed. Application of this ASIC and other ASICs containing the SpaceWire cores and embedded microcontroller to Plug and Play and reconfigurable implementations will be described. Finally, the BAE Systems roadmap for SpaceWire developments will be updated, including some products already in design as well as longer term plans.

Marshall, Joseph R.↗

NASA NTRS2008

NASA Tech Briefs, November 2008

Topics covered include: Digital Phase Meter for a Laser Heterodyne Interferometer; Vision System Measures Motions of Robot and External Objects; Advanced Precipitation Radar Antenna to Measure Rainfall From Space; Wide-Band Radar for Measuring Thickness of Sea Ice; Vertical Isolation for Photodiodes in CMOS Imagers; Wide-Band Microwave Receivers Using Photonic Processing; L-Band Transmit/Receive Module for Phase-Stable Array Antennas; Microwave Power Combiner/Switch Utilizing a Faraday Rotator; Compact Low-Loss Planar Magic-T; Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines; Quasi-Optical Transmission Line for 94-GHz Radar; Next Generation Flight Controller Trainer System; Converting from DDOR SASF to APF; Converting from CVF to AAF; Documenting AUTOGEN and APGEN Model Files; Sequence History Update Tool; Extraction and Analysis of Display Data; MRO DKF Post-Processing Tool; Rig Diagnostic Tools; MRO Sequence Checking Tool; Science Activity Planner for the MER Mission; UAVSAR Flight-Planning System; Templates for Deposition of Microscopic Pointed Structures; Adjustable Membrane Mirrors Incorporating G-Elastomers; Hall-Effect Thruster Utilizing Bismuth as Propellant; High-Temperature Crystal-Growth Cartridge Tubes Made by VPS; Quench Crucibles Reinforced with Metal; Deep-Sea Hydrothermal-Vent Sampler; Mars Rocket Propulsion System; Two-Stage Passive Vibration Isolator; Improved Thermal Design of a Compression Mold; Enhanced Pseudo-Waypoint Guidance for Spacecraft Maneuvers; Altimetry Using GPS-Reflection/Occultation Interferometry; Thermally Driven Josephson Effect; Perturbation Effects on a Supercritical C7H16/N2 Mixing Layer; Gold Nanoparticle Labels Amplify Ellipsometric Signals; Phase Matching of Diverse Modes in a WGM Resonator; WGM Resonators for Terahertz-to-Optical Frequency Conversion; Determining Concentration of Nanoparticles from Ellipsometry; Microwave-to-Optical Conversion in WGM Resonators; Four-Pass Coupler for Laser-Diode-Pumped Solid-State Laser; Low-Resolution Raman-Spectroscopy Combustion Thermometry; Temperature Sensors Based on WGM Optical Resonators; Varying the Divergence of Multiple Parallel Laser Beams; Efficient Algorithm for Rectangular Spiral Search; Algorithm-Based Fault Tolerance Integrated with Replication; Targeting and Localization for Mars Rover Operations; Terrain-Adaptive Navigation Architecture; Self-Adjusting Hash Tables for Embedded Flight Applications; Schema for Spacecraft-Command Dictionary; Combined GMSK Communications and PN Ranging; System-Level Integration of Mass Memory; Network-Attached Solid-State Recorder Architecture; Method of Cross-Linking Aerogels Using a One-Pot Reaction Scheme; An Efficient Reachability Analysis Algorithm.

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NASA NTRS2008

NASA Tech Briefs, September 2008

Topics covered include: Nanotip Carpets as Antireflection Surfaces; Nano-Engineered Catalysts for Direct Methanol Fuel Cells; Capillography of Mats of Nanofibers; Directed Growth of Carbon Nanotubes Across Gaps; High-Voltage, Asymmetric-Waveform Generator; Magic-T Junction Using Microstrip/Slotline Transitions; On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz; Group-III Nitride Field Emitters; HEMT Amplifiers and Equipment for their On-Wafer Testing; Thermal Spray Formation of Polymer Coatings; Improved Gas Filling and Sealing of an HC-PCF; Making More-Complex Molecules Using Superthermal Atom/Molecule Collisions; Nematic Cells for Digital Light Deflection; Improved Silica Aerogel Composite Materials; Microgravity, Mesh-Crawling Legged Robots; Advanced Active-Magnetic-Bearing Thrust- Measurement System; Thermally Actuated Hydraulic Pumps; A New, Highly Improved Two-Cycle Engine; Flexible Structural-Health-Monitoring Sheets; Alignment Pins for Assembling and Disassembling Structures; Purifying Nucleic Acids from Samples of Extremely Low Biomass; Adjustable-Viewing-Angle Endoscopic Tool for Skull Base and Brain Surgery; UV-Resistant Non-Spore-Forming Bacteria From Spacecraft-Assembly Facilities; Hard-X-Ray/Soft-Gamma-Ray Imaging Sensor Assembly for Astronomy; Simplified Modeling of Oxidation of Hydrocarbons; Near-Field Spectroscopy with Nanoparticles Deposited by AFM; Light Collimator and Monitor for a Spectroradiometer; Hyperspectral Fluorescence and Reflectance Imaging Instrument; Improving the Optical Quality Factor of the WGM Resonator; Ultra-Stable Beacon Source for Laboratory Testing of Optical Tracking; Transmissive Diffractive Optical Element Solar Concentrators; Delaying Trains of Short Light Pulses in WGM Resonators; Toward Better Modeling of Supercritical Turbulent Mixing; JPEG 2000 Encoding with Perceptual Distortion Control; Intelligent Integrated Health Management for a System of Systems; Delay Banking for Managing Air Traffic; and Spline-Based Smoothing of Airfoil Curvatures.

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NASA NTRS2009

Alternative Packaging for Back-Illuminated Imagers

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Pain, Bedabrata↗

NASA NTRS2008

Making a Back-Illuminated Imager with Back-Side Contact and Alignment Markers

A design modification and a fabrication process that implements the modification have been conceived to solve two problems encountered in the development of back-illuminated, back-sidethinned complementary metal oxide/ semiconductor (CMOS) image-detector integrated circuits. The two problems are (1) how to form metal electrical-contact pads on the back side that are electrically connected through the thickness in proper alignment with electrical contact points on the front side and (2) how to provide alignment keys on the back side to ensure proper registration of backside optical components (e.g., microlenses and/or color filters) with the front-side pixel pattern. The essence of the design modification is to add metal plugs that extend from the desired front-side locations through the thickness and protrude from the back side of the substrate. The plugs afford the required front-to-back electrical conduction, and the protrusions of the plugs serve as both the alignment keys and the bases upon which the back-side electrical-contact pads can be formed.

Pain, Bedabrata↗

NASA NTRS2008

NASA Tech Briefs, August 2008

Customizable Digital Receivers for Radar Two-Camera Acquisition and Tracking of a Flying Target Visual Data Analysis for Satellites A Data Type for Efficient Representation of Other Data Types Hand-Held Ultrasonic Instrument for Reading Matrix Symbols Broadband Microstrip-to-Coplanar Strip Double-Y Balun A Topographical Lidar System for Terrain-Relative Navigation Programmable Low-Voltage Circuit Breaker and Tester Electronic Switch Arrays for Managing Microbattery Arrays Topics covered include: Lower-Dark-Current, Higher-Blue-Response CMOS Imagers; Fabricating Large-Area Sheets of Single-Layer Graphene by CVD; Support for Diagnosis of Custom Computer Hardware; Providing Goal-Based Autonomy for Commanding a Spacecraft; Dynamic Method for Identifying Collected Sample Mass; Optimal Planning and Problem-Solving; Attitude-Control Algorithm for Minimizing Maneuver Execution Errors; Grants Document-Generation System; Heat-Storage Modules Containing LiNO3 3H2O and Graphite Foam; Precipitation-Strengthened, High-Temperature, High-Force Shape Memory Alloys; Improved Relief Valve Would Be Less Susceptible to Failure; Safety Modification of Cam-and-Groove Hose Coupling; Using Composite Materials in a Cryogenic Pump; Using Electronic Noses to Detect Tumors During Neurosurgery; Producing Newborn Synchronous Mammalian Cells; Smaller, Lower-Power Fast-Neutron Scintillation Detectors; Rotationally Vibrating Electric-Field Mill; Estimating Hardness from the USDC Tool-Bit Temperature Rise; Particle-Charge Spectrometer; Automated Production of Movies on a Cluster of Computers; FIDO-Class Development Rover; and Tone-Based Command of Deep Space Probes Using Ground Antennas.

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NASA NTRS2008

High-Density, High-Bandwidth, Multilevel Holographic Memory

A proposed holographic memory system would be capable of storing data at unprecedentedly high density, and its data transfer performance in both reading and writing would be characterized by exceptionally high bandwidth. The capabilities of the proposed system would greatly exceed even those of a state-of-the art memory system, based on binary holograms (in which each pixel value represents 0 or 1), that can hold .1 terabyte of data and can support a reading or writing rate as high as 1 Gb/s. The storage capacity of the state-of-theart system cannot be increased without also increasing the volume and mass of the system. However, in principle, the storage capacity could be increased greatly, without significantly increasing the volume and mass, if multilevel holograms were used instead of binary holograms. For example, a 3-bit (8-level) hologram could store 8 terabytes, or an 8-bit (256-level) hologram could store 256 terabytes, in a system having little or no more size and mass than does the state-of-the-art 1-terabyte binary holographic memory. The proposed system would utilize multilevel holograms. The system would include lasers, imaging lenses and other beam-forming optics, a block photorefractive crystal wherein the holograms would be formed, and two multilevel spatial light modulators in the form of commercially available deformable-mirror-device spatial light modulators (DMDSLMs) made for use in high speed input conversion of data up to 12 bits. For readout, the system would also include two arrays of complementary metal oxide/semiconductor (CMOS) photodetectors matching the spatial light modulators. The system would further include a reference-beam sterring device (equivalent of a scanning mirror), containing no sliding parts, that could be either a liquid-crystal phased-array device or a microscopic mirror actuated by a high-speed microelectromechanical system. Time-multiplexing and the multilevel nature of the DMDSLM would be exploited to enable writing and reading of multilevel holograms. The DMDSLM would also enable transfer of data at a rate of 7.6 Gb/s or perhaps somewhat higher.

Chao, Tien-Hsin↗

NASA NTRS2009

FPGA-Based Networked Phasemeter for a Heterodyne Interferometer

A document discusses a component of a laser metrology system designed to measure displacements along the line of sight with precision on the order of a tenth the diameter of an atom. This component, the phasemeter, measures the relative phase of two electrical signals and transfers that information to a computer. Because the metrology system measures the differences between two optical paths, the phasemeter has two inputs, called measure and reference. The reference signal is nominally a perfect square wave with a 50- percent duty cycle (though only rising edges are used). As the metrology system detects motion, the difference between the reference and measure signal phases is proportional to the displacement of the motion. The phasemeter, therefore, counts the elapsed time between rising edges in the two signals, and converts the time into an estimate of phase delay. The hardware consists of a circuit board that plugs into a COTS (commercial, off-the- shelf) Spartan-III FPGA (field-programmable gate array) evaluation board. It has two BNC inputs, (reference and measure), a CMOS logic chip to buffer the inputs, and an Ethernet jack for transmitting reduced-data to a PC. Two extra BNC connectors can be attached for future expandability, such as external synchronization. Each phasemeter handles one metrology channel. A bank of six phasemeters (and two zero-crossing detector cards) with an Ethernet switch can monitor the rigid body motion of an object. This device is smaller and cheaper than existing zero-crossing phasemeters. Also, because it uses Ethernet for communication with a computer, instead of a VME bridge, it is much easier to use. The phasemeter is a key part of the Precision Deployable Apertures and Structures strategic R&D effort to design large, deployable, segmented space telescopes.

Rao, Shanti↗

NASA NTRS2007

Toward a III-V Multijunction Space Cell Technology on Si

High efficiency compound semiconductor solar cells grown on Si substrates are of growing interest in the photovoltaics community for both terrestrial and space applications. As a potential substrate for III-V compound photovoltaics, Si has many advantages over traditional Ge and GaAs substrates that include higher thermal conductivity, lower weight, lower material costs, and the potential to leverage the extensive manufacturing base of the Si industry. Such a technology that would retain high solar conversion efficiency at reduced weight and cost would result in space solar cells that simultaneously possess high specific power (W/kg) and high power density (W/m2). For terrestrial solar cells this would result in high efficiency III-V concentrators with improved thermal conductivity, reduced cost, and via the use of SiGe graded interlayers as active component layers the possibility of integrating low bandgap sub-cells that could provide for extremely high conversion efficiency.1 In addition to photovoltaics, there has been an historical interest in III-V/Si integration to provide optical interconnects in Si electronics, which has become of even greater relevance recently due to impending bottlenecks in CMOS based circuitry. As a result, numerous strategies to integrate GaAs with Si have been explored with the primary issue being the approx.4% lattice mismatch between GaAs and Si. Among these efforts, relaxed, compositionally-graded SiGe buffer layers where the substrate lattice constant is effectively tuned from Si to that of Ge so that a close lattice match to subsequent GaAs overlayers have shown great promise. With this approach, threading dislocation densities (TDDs) of approx.1 x 10(exp 6)/sq cm have been uniformly achieved in relaxed Ge layers on Si,5 leading to GaAs on Si with minority carrier lifetimes greater than 10 ns,6 GaAs single junction solar cells on Si with efficiencies greater than 18%,7 InGaAs CW laser diodes on Si,8 and room temperature GaInP red laser diodes on Si.9 Here we report on the first high performance dual junction GaInP/GaAs solar cells grown on Si using this promising SiGe engineered substrate approach.

Ringel, S. A.↗

NASA NTRS2009

Multi-Modulator for Bandwidth-Efficient Communication

A modulator circuit board has recently been developed to be used in conjunction with a vector modulator to generate any of a large number of modulations for bandwidth-efficient radio transmission of digital data signals at rates than can exceed 100 Mb/s. The modulations include quadrature phaseshift keying (QPSK), offset quadrature phase-shift keying (OQPSK), Gaussian minimum-shift keying (GMSK), and octonary phase-shift keying (8PSK) with square-root raised-cosine pulse shaping. The figure is a greatly simplified block diagram showing the relationship between the modulator board and the rest of the transmitter. The role of the modulator board is to encode the incoming data stream and to shape the resulting pulses, which are fed as inputs to the vector modulator. The combination of encoding and pulse shaping in a given application is chosen to maximize the bandwidth efficiency. The modulator board includes gallium arsenide serial-to-parallel converters at its input end. A complementary metal oxide/semiconductor (CMOS) field-programmable gate array (FPGA) performs the coding and modulation computations and utilizes parallel processing in doing so. The results of the parallel computation are combined and converted to pulse waveforms by use of gallium arsenide parallel-to-serial converters integrated with digital-to-analog converters. Without changing the hardware, one can configure the modulator to produce any of the designed combinations of coding and modulation by loading the appropriate bit configuration file into the FPGA.

Gray, Andrew↗

NASA NTRS2009

NASA Tech Briefs, September 2009

opics covered include: Filtering Water by Use of Ultrasonically Vibrated Nanotubes; Computer Code for Nanostructure Simulation; Functionalizing CNTs for Making Epoxy/CNT Composites; Improvements in Production of Single-Walled Carbon Nanotubes; Progress Toward Sequestering Carbon Nanotubes in PmPV; Two-Stage Variable Sample-Rate Conversion System; Estimating Transmitted-Signal Phase Variations for Uplink Array Antennas; Board Saver for Use with Developmental FPGAs; Circuit for Driving Piezoelectric Transducers; Digital Synchronizer without Metastability; Compact, Low-Overhead, MIL-STD-1553B Controller; Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM; Differential InP HEMT MMIC Amplifiers Embedded in Waveguides; Improved Aerogel Vacuum Thermal Insulation; Fluoroester Co-Solvents for Low-Temperature Li+ Cells; Using Volcanic Ash to Remove Dissolved Uranium and Lead; High-Efficiency Artificial Photosynthesis Using a Novel Alkaline Membrane Cell; Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays; Micro-Horn Arrays for Ultrasonic Impedance Matching; Improved Controller for a Three-Axis Piezoelectric Stage; Nano-Pervaporation Membrane with Heat Exchanger Generates Medical-Grade Water; Micro-Organ Devices; Nonlinear Thermal Compensators for WGM Resonators; Dynamic Self-Locking of an OEO Containing a VCSEL; Internal Water Vapor Photoacoustic Calibration; Mid-Infrared Reflectance Imaging of Thermal-Barrier Coatings; Improving the Visible and Infrared Contrast Ratio of Microshutter Arrays; Improved Scanners for Microscopic Hyperspectral Imaging; Rate-Compatible LDPC Codes with Linear Minimum Distance; PrimeSupplier Cross-Program Impact Analysis and Supplier Stability Indicator Simulation Model; Integrated Planning for Telepresence With Time Delays; Minimizing Input-to-Output Latency in Virtual Environment; Battery Cell Voltage Sensing and Balancing Using Addressable Transformers; Gaussian and Lognormal Models of Hurricane Gust Factors; Simulation of Attitude and Trajectory Dynamics and Control of Multiple Spacecraft; Integrated Modeling of Spacecraft Touch-and-Go Sampling; Spacecraft Station-Keeping Trajectory and Mission Design Tools; Efficient Model-Based Diagnosis Engine; and DSN Simulator.

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NASA NTRS2009

Differential InP HEMT MMIC Amplifiers Embedded in Waveguides

Monolithic microwave integrated-circuit (MMIC) amplifiers of a type now being developed for operation at frequencies of hundreds of gigahertz contain InP high-electron-mobility transistors (HEMTs) in a differential configuration. The differential configuration makes it possible to obtain gains greater than those of amplifiers having the single-ended configuration. To reduce losses associated with packaging, the MMIC chips are designed integrally with, and embedded in, waveguide packages, with the additional benefit that the packages are compact enough to fit into phased transmitting and/or receiving antenna arrays. Differential configurations (which are inherently balanced) have been used to extend the upper limits of operating frequencies of complementary metal oxide/semiconductor (CMOS) amplifiers to the microwave range but, until now, have not been applied in millimeter- wave amplifier circuits. Baluns have traditionally been used to transform from single-ended to balanced configurations, but baluns tend to be lossy. Instead of baluns, finlines are used to effect this transformation in the present line of development. Finlines have been used extensively to drive millimeter- wave mixers in balanced configurations. In the present extension of the finline balancing concept, finline transitions are integrated onto the affected MMICs (see figure). The differential configuration creates a virtual ground within each pair of InP HEMT gate fingers, eliminating the need for inductive vias to ground. Elimination of these vias greatly reduces parasitic components of current and the associated losses within an amplifier, thereby enabling more nearly complete utilization of the full performance of each transistor. The differential configuration offers the additional benefit of multiplying (relative to the single-ended configuration) the input and output impedances of each transistor by a factor of four, so that it is possible to use large transistors that would otherwise have prohibitively low impedances. Yet another advantage afforded by the virtual ground of the differential configuration is elimination of the need for a ground plane and, hence, elimination of the need for back-side metallization of the MMIC chip. In turn, elimination of the back-side metallization simplifies fabrication, reduces parasitic capacitances, and enables mounting of the MMIC in the electric-field plane ("E-plane") of a waveguide. E-plane mounting is consistent with (and essential for the utility of) the finline configuration, in which transmission lines lie on a dielectric sheet in the middle of a broad side of the waveguide. E-plane mounting offers a combination of low loss and ease of assembly because no millimeter-wave wire bonds or transition substrates are required. Moreover, because there is no ground plane behind the MMIC, the impedance for the detrimental even (single-ended) mode is high, suppressing coupling to that mode. Still another advantage of E-plane mounting is that the fundamental waveguide mode is inherently differential, eliminating the need for a balun to excite the differential mode.

Kangaslahti, Pekka↗