Results for “Parallel and high performance computing” — Page 54

NASA NTRS2007

A Microfabricated Involute-Foil Regenerator for Stirling Engines

A segmented involute-foil regenerator has been designed, microfabricated and tested in an oscillating-flow rig with excellent results. During the Phase I effort, several approximations of parallel-plate regenerator geometry were chosen as potential candidates for a new microfabrication concept. Potential manufacturers and processes were surveyed. The selected concept consisted of stacked segmented-involute-foil disks (or annular portions of disks), originally to be microfabricated from stainless-steel via the LiGA (lithography, electroplating, and molding) process and EDM (electric discharge machining). During Phase II, re-planning of the effort led to test plans based on nickel disks, microfabricated via the LiGA process, only. A stack of nickel segmented-involute-foil disks was tested in an oscillating-flow test rig. These test results yielded a performance figure of merit (roughly the ratio of heat transfer to pressure drop) of about twice that of the 90% random fiber currently used in small ~ 100 W Stirling space-power convertors in the Reynolds Number range of interest (50-100). A Phase III effort is now underway to fabricate and test a segmented-involute-foil regenerator in a Stirling convertor. Though funding limitations prevent optimization of the Stirling engine geometry for use with this regenerator, the Sage computer code will be used to help evaluate the engine test results. Previous Sage Stirling model projections have indicated that a segmented-involute-foil regenerator is capable of improving the performance of an optimized involute-foil engine by 6-9%; it is also anticipated that such involute-foil geometries will be more reliable and easier to manufacture with tight-tolerance characteristics, than random-fiber or wire-screen regenerators. Beyond the near-term Phase III regenerator fabrication and engine testing, other goals are (1) fabrication from a material suitable for high temperature Stirling operation (up to 850 C for current engines; up to 1200 C for a potential engine-cooler for a Venus mission), and (2) reduction of the cost of the fabrication process to make it more suitable for terrestrial applications of segmented involute foils. Past attempts have been made to use wrapped foils to approximate the large theoretical figures of merit projected for parallel plates. Such metal wrapped foils have never proved very successful, apparently due to the difficulties of fabricating wrapped-foils with uniform gaps and maintaining the gaps under the stress of time-varying temperature gradients during start-up and shut-down, and relatively-steady temperature gradients during normal operation. In contrast, stacks of involute-foil disks, with each disk consisting of multiple involute-foil segments held between concentric circular ribs, have relatively robust structures. The oscillating-flow rig tests of the segmented-involute-foil regenerator have demonstrated a shift in regenerator performance strongly in the direction of the theoretical performance of ideal parallel-plate regenerators.

Tew, Roy↗

DOE OSTI2020

Lagrangian simulations of spray interaction with a surface using a stochastic multi-regime impingement model

Modeling of spray impingement upon the piston or cylinder surface is important for hydrocarbon emission and soot predictions in high-fidelity simulation of internal combustion engines with direct injections. Due to the complexity of the physical process of spray impingement, current computational models heavily rely on the empirical studies which involve large uncertainties. A computational model is presented for spray impingement on solid walls in general computational fluid dynamics (CFD) simulations. The model adopts the Marmanis-Thoroddsen theory for determining the number of secondary droplets and a stochastic method for calculating the velocities of the secondary droplets. The numerical methods and parallel implementation of the impingement model are presented in detail. The model is implemented in Grit, which is a recently developed CPU/GPU performance-portable Lagrangian particle library, for accelerating spray simulations. The model and its implementation are tested for examples of spray impingements on flat and smooth surfaces with different impingement angles.

Ge, Wenjun↗

NASA NTRS2007

A Microfabricated Involute-Foil Regenerator for Stirling Engines

A segmented involute-foil regenerator has been designed, microfabricated and tested in an oscillating-flow rig with excellent results. During the Phase I effort, several approximations of parallel-plate regenerator geometry were chosen as potential candidates for a new microfabrication concept. Potential manufacturers and processes were surveyed. The selected concept consisted of stacked segmented-involute-foil disks (or annular portions of disks), originally to be microfabricated from stainless-steel via the LiGA (lithography, electroplating, and molding) process and EDM. During Phase II, re-planning of the effort led to test plans based on nickel disks, microfabricated via the LiGA process, only. A stack of nickel segmented-involute-foil disks was tested in an oscillating-flow test rig. These test results yielded a performance figure of merit (roughly the ratio of heat transfer to pressure drop) of about twice that of the 90 percent random fiber currently used in small approx.100 W Stirling space-power convertors-in the Reynolds Number range of interest (50 to 100). A Phase III effort is now underway to fabricate and test a segmented-involute-foil regenerator in a Stirling convertor. Though funding limitations prevent optimization of the Stirling engine geometry for use with this regenerator, the Sage computer code will be used to help evaluate the engine test results. Previous Sage Stirling model projections have indicated that a segmented-involute-foil regenerator is capable of improving the performance of an optimized involute-foil engine by 6 to 9 percent; it is also anticipated that such involute-foil geometries will be more reliable and easier to manufacture with tight-tolerance characteristics, than random-fiber or wire-screen regenerators. Beyond the near-term Phase III regenerator fabrication and engine testing, other goals are (1) fabrication from a material suitable for high temperature Stirling operation (up to 850 C for current engines; up to 1200 C for a potential engine-cooler for a Venus mission), and (2) reduction of the cost of the fabrication process to make it more suitable for terrestrial applications of segmented involute foils. Past attempts have been made to use wrapped foils to approximate the large theoretical figures of merit projected for parallel plates. Such metal wrapped foils have never proved very successful, apparently due to the difficulties of fabricating wrapped-foils with uniform gaps and maintaining the gaps under the stress of time-varying temperature gradients during start-up and shut-down, and relatively-steady temperature gradients during normal operation. In contrast, stacks of involute-foil disks, with each disk consisting of multiple involute-foil segments held between concentric circular ribs, have relatively robust structures. The oscillating-flow rig tests of the segmented-involute-foil regenerator have demonstrated a shift in regenerator performance strongly in the direction of the theoretical performance of ideal parallel-plate regenerators.

Tew, Roy↗

NASA NTRS2002

Turbopump Performance Improved by Evolutionary Algorithms

The development of design optimization technology for turbomachinery has been initiated using the multiobjective evolutionary algorithm under NASA's Intelligent Synthesis Environment and Revolutionary Aeropropulsion Concepts programs. As an alternative to the traditional gradient-based methods, evolutionary algorithms (EA's) are emergent design-optimization algorithms modeled after the mechanisms found in natural evolution. EA's search from multiple points, instead of moving from a single point. In addition, they require no derivatives or gradients of the objective function, leading to robustness and simplicity in coupling any evaluation codes. Parallel efficiency also becomes very high by using a simple master-slave concept for function evaluations, since such evaluations often consume the most CPU time, such as computational fluid dynamics. Application of EA's to multiobjective design problems is also straightforward because EA's maintain a population of design candidates in parallel. Because of these advantages, EA's are a unique and attractive approach to real-world design optimization problems.

Oyama, Akira↗

DOE OSTI2022

Towards Superior Software Portability with SHAD and HPX C++ Libraries

As hardware architectures and software stacks complexity grows, development productivity, performance and software portability, quickly evolve from desirable features to actual needs. SHAD, the Scalable High-performance Algorithms and Data-structures C++ library is designed to mitigate these issues: it provides general purpose building blocks as well as high-level custom utilities, and offers a shared-memory programming abstraction which facilitates the programming of complex systems, scaling up to High Performance Computing clusters. SHAD’s portability is achieved through an abstract runtime interface, which decouples the upper layers of the library and hides the low level details of the underlying architecture. This layer enables SHAD to interface with different runtime/threading systems, e.g. Intel TBB and Global Memory and Threading (GMT). However, current backends targeting distributed systems, rely on a centralized controller which may possibly limit scalability up to hundreds of nodes and creates a network hot spot due to all to one communication for synchronization, and possibly resulting in degraded performance at high process counts. In this research, we explore HPX, the C++ standard library for parallelism and concurrency, as an additional backend in support of the SHAD library, and present the methodologies in support of local and remote task executions in SHAD with respect to HPX. Finally, we evaluate the proposed system by comparing against existing backends of SHAD and analyzing their performance on C++ Standard Template Library algorithms.

Wu, Nanmiao↗

DOE OSTI2025

ChatHPC: Building the Foundations for a Productive and Trustworthy AI-Assisted HPC Ecosystem

ChatHPC democratizes large language models for the high-performance computing (HPC) community by providing the infrastructure, ecosystem, and knowledge needed to apply modern generative AI technologies to rapidly create specific capabilities for critical HPC components while using relatively modest computational resources. Our divide-and-conquer approach focuses on creating a collection of reliable, highly specialized, and optimized AI assistants for HPC based on the cost-effective and fast Code Llama fine-tuning processes and expert supervision. We target major components of the HPC software stack, including programming models, runtimes, I/O, tooling, and math libraries. Thanks to AI, ChatHPC provides a more productive HPC ecosystem by boosting important tasks related to portability, parallelization, optimization, scalability, and instrumentation, among others. With relatively small datasets (on the order of KB), the AI assistants, which are created in a few minutes by using one node with two NVIDIA H100 GPUs and the ChatHPC library, can create new capabilities with Meta’s 7-billion parameter Code Llama base model to produce high-quality software with a level of trustworthiness of up to 90% higher than the 1.8-trillion parameter OpenAI ChatGPT-4o model for critical programming tasks in the HPC software stack.

Young, Aaron [ORNL] (ORCID:0000000254484667)↗

DOE OSTI2023

UPC++ v1.0 Programmer’s Guide (Rev. 2023.9.0)

UPC++ is a C++ library that supports Partitioned Global Address Space (PGAS) programming. It is designed for writing efficient, scalable parallel programs on distributed-memory parallel computers. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). The UPC++ control model is single program, multiple-data (SPMD), with each separate constituent process having access to local memory as it would in C++. The PGAS memory model additionally provides one-sided RMA communication to a global address space, which is allocated in shared segments that are distributed over the processes. UPC++ also features Remote Procedure Call (RPC) communication, making it easy to move computation to operate on data that resides on remote processes. UPC++ was designed to support exascale high-performance computing, and the library interfaces and implementation are focused on maximizing scalability. In UPC++, all communication operations are syntactically explicit, which encourages programmers to consider the costs associated with communication and data movement. Moreover, all communication operations are asynchronous by default, encouraging programmers to seek opportunities for overlapping communication latencies with other useful work. UPC++ provides expressive and composable abstractions designed for efficiently managing aggressive use of asynchrony in programs. Together, these design principles are intended to enable programmers to write applications using UPC++ that perform well even on hundreds of thousands of cores.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

UPC++ v1.0 Programmer’s Guide (Revision 2022.3.0)

UPC++ is a C++ library that supports Partitioned Global Address Space (PGAS) programming. It is designed for writing efficient, scalable parallel programs on distributed-memory parallel computers. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). The UPC++ control model is single program, multiple-data (SPMD), with each separate constituent process having access to local memory as it would in C++. The PGAS memory model additionally provides one-sided RMA communication to a global address space, which is allocated in shared segments that are distributed over the processes. UPC++ also features Remote Procedure Call (RPC) communication, making it easy to move computation to operate on data that resides on remote processes. UPC++ was designed to support exascale high-performance computing, and the library interfaces and implementation are focused on maximizing scalability. In UPC++, all communication operations are syntactically explicit, which encourages programmers to consider the costs associated with communication and data movement. Moreover, all communication operations are asynchronous by default, encouraging programmers to seek opportunities for overlapping communication latencies with other useful work. UPC++ provides expressive and composable abstractions designed for efficiently managing aggressive use of asynchrony in programs. Together, these design principles are intended to enable programmers to write applications using UPC++ that perform well even on hundreds of thousands of cores.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2023

UPC++ v1.0 Programmer’s Guide, Revision 2023.3.0

UPC++ is a C++ library that supports Partitioned Global Address Space (PGAS) programming. It is designed for writing efficient, scalable parallel programs on distributed-memory parallel computers. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). The UPC++ control model is single program, multiple-data (SPMD), with each separate constituent process having access to local memory as it would in C++. The PGAS memory model additionally provides one-sided RMA communication to a global address space, which is allocated in shared segments that are distributed over the processes. UPC++ also features Remote Procedure Call (RPC) communication, making it easy to move computation to operate on data that resides on remote processes. UPC++ was designed to support exascale high-performance computing, and the library interfaces and implementation are focused on maximizing scalability. In UPC++, all communication operations are syntactically explicit, which encourages programmers to consider the costs associated with communication and data movement. Moreover, all communication operations are asynchronous by default, encouraging programmers to seek opportunities for overlapping communication latencies with other useful work. UPC++ provides expressive and composable abstractions designed for efficiently managing aggressive use of asynchrony in programs. Together, these design principles are intended to enable programmers to write applications using UPC++ that perform well even on hundreds of thousands of cores.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

UPC++ v1.0 Programmer’s Guide, Revision 2022.9.0

UPC++ is a C++ library that supports Partitioned Global Address Space (PGAS) programming. It is designed for writing efficient, scalable parallel programs on distributed-memory parallel computers. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). The UPC++ control model is single program, multiple-data (SPMD), with each separate constituent process having access to local memory as it would in C++. The PGAS memory model additionally provides one-sided RMA communication to a global address space, which is allocated in shared segments that are distributed over the processes. UPC++ also features Remote Procedure Call (RPC) communication, making it easy to move computation to operate on data that resides on remote processes. UPC++ was designed to support exascale high-performance computing, and the library interfaces and implementation are focused on maximizing scalability. In UPC++, all communication operations are syntactically explicit, which encourages programmers to consider the costs associated with communication and data movement. Moreover, all communication operations are asynchronous by default, encouraging programmers to seek opportunities for overlapping communication latencies with other useful work. UPC++ provides expressive and composable abstractions designed for efficiently managing aggressive use of asynchrony in programs. Together, these design principles are intended to enable programmers to write applications using UPC++ that perform well even on hundreds of thousands of cores.

97 MATHEMATICS AND COMPUTING↗

NASA NTRSDate not supplied

Analysis of the Amplitude Response of a Two-Point and a Two-Line/Multi-Point Focused Laser Differential Interferometer

Experiments were performed with two different focused laser differential interferometer (FLDI) instruments to assess the amplitude response of each instrument to a traveling shock-wave generated by a laser spark. The first FLDI instrument generated two measurement points, with each measurement point providing sensitivity to density fluctuations induced by the shockwave. By performing a cross-correlation between the signals obtained from each measurement point, the phase velocity of density fluctuations can be obtained. The second FLDI instrument generated two measurement lines that are oriented either parallel or orthogonal to the shockwave direction of travel with the resulting interference pattern sampled at multiple equally-spaced points along each line. As a result, this instrument provides density fluctuation measurement capability at multiple points simultaneously. When the measurement lines are oriented parallel to the shockwave direction of travel, the phase velocity, rate of change of the phase velocity, and acceleration of density fluctuations traveling along each line can be obtained by performing a cross-correlation between points along a single line. When the measurement lines are oriented orthogonal to the shockwave direction of travel, the spatially-varying phase velocity can be obtained by performing a cross-correlation between points at the same relative location on each measurement line. Computations of the shockwave generated by the laser spark are used to simulate the response of each instrument and are compared to the experimental results. High-speed Schlieren imaging has also been performed and is compared with the FLDI measurements and computational results.

Focused Laser Differential Interferometer↗

NASA NTRS1991

System and component design and test of a 10 hp, 18,000 rpm AC dynamometer utilizing a high frequency AC voltage link, part 1

Hard and soft switching test results conducted with one of the samples of first generation MOS-controlled thyristor (MCTs) and similar test results with several different samples of second generation MCT's are reported. A simple chopper circuit is used to investigate the basic switching characteristics of MCT under hard switching and various types of resonant circuits are used to determine soft switching characteristics of MCT under both zero voltage and zero current switching. Next, operation principles of a pulse density modulated converter (PDMC) for three phase (3F) to 3F two-step power conversion via parallel resonant high frequency (HF) AC link are reviewed. The details for the selection of power switches and other power components required for the construction of the power circuit for the second generation 3F to 3F converter system are discussed. The problems encountered in the first generation system are considered. Design and performance of the first generation 3F to 3F power converter system and field oriented induction moter drive based upon a 3 kVA, 20 kHz parallel resonant HF AC link are described. Low harmonic current at the input and output, unity power factor operation of input, and bidirectional flow capability of the system are shown via both computer and experimental results. The work completed on the construction and testing of the second generation converter and field oriented induction motor drive based upon specifications for a 10 hp squirrel cage dynamometer and a 20 kHz parallel resonant HF AC link is discussed. The induction machine is designed to deliver 10 hp or 7.46 kW when operated as an AC-dynamo with power fed back to the source through the converter. Results presented reveal that the proposed power level requires additional energy storage elements to overcome difficulties with a peak link voltage variation problem that limits reaching to the desired power level. The power level test of the second generation converter after the addition of extra energy storage elements to the HF link are described. The importance of the source voltage level to achieve a better current regulation for the source side PDMC is also briefly discussed. The power levels achieved in the motoring mode of operation show that the proposed power levels achieved in the generating mode of operation can also be easily achieved provided that no mechanical speed limitation were present to drive the induction machine at the proposed power level.

Lipo, Thomas A.↗

NASA NTRS1993

Computational Controls Workstation: Algorithms and hardware

The Computational Controls Workstation provides an integrated environment for the modeling, simulation, and analysis of Space Station dynamics and control. Using highly efficient computational algorithms combined with a fast parallel processing architecture, the workstation makes real-time simulation of flexible body models of the Space Station possible. A consistent, user-friendly interface and state-of-the-art post-processing options are combined with powerful analysis tools and model databases to provide users with a complete environment for Space Station dynamics and control analysis. The software tools available include a solid modeler, graphical data entry tool, O(n) algorithm-based multi-flexible body simulation, and 2D/3D post-processors. This paper describes the architecture of the workstation while a companion paper describes performance and user perspectives.

Venugopal, R.↗

NASA NTRS1981

RAMP - A fault tolerant distributed microcomputer structure for aircraft navigation and control

Design methodologies for realizing future high authority autoflight control systems are being investigated, taking into account also the study of distributed microcomputer architectures. Attention is given to the redundant asynchronous microprocessor (RAMP) structure. RAMP comprises a connected network of microcomputers which has as input command and sensor information, and which generates servo information to drive actuators, and thrust linkages. Tolerance to hardware failures is achieved by static redundancy. Results of a failed microcomputer are simply rejected. This is done in lieu of dynamic redundancy wherein the distributed computer system performs real time fault detection and reconfiguration of the system. Attention is given to the RAMP network structure and operation, flight control with parallel asynchronous computers, and intermittent fault tolerance.

Dunn, W. R.↗

DOE OSTI2025

Performance Portability Evaluation of Fluid-Structure Interaction Simulations on Heterogeneous Platforms

The rapid proliferation of heterogeneous programming languages and multi-vendor hardware has underscored the critical need to evaluate the performance portability of scientific applications. In this work, we present the systematic porting and optimization of a massively parallel fluid-structure interaction code across multiple heterogeneous programming frameworks for deployment on leadership-class supercomputers from major vendors. Our analysis focuses on at-scale performance for simulations involving hundreds of millions of deformable cells, executed on a combination of CPUs and GPUs spanning thousands of nodes on exascale machines. We benchmark the performance of each implementation, highlighting the trade-offs inherent in adopting diverse programming models. Key insights regarding the portability of CUDA on multi-vendor platforms, the superior multi-core CPU performance from SYCL, and architectural considerations on performance optimization are distilled from our experience, offering guidance to other users of high performance computing based on our findings.

Martin, Aristotle [Duke University]↗

DOE OSTI2024

Modeling performance of data collection systems for high-energy physics

Exponential increases in scientific experimental data are outpacing silicon technology progress, necessitating heterogeneous computing systems—particularly those utilizing machine learning (ML)—to meet future scientific computing demands. The growing importance and complexity of heterogeneous computing systems require systematic modeling to understand and predict the effective roles for ML. We present a model that addresses this need by framing the key aspects of data collection pipelines and constraints and combining them with the important vectors of technology that shape alternatives, computing metrics that allow complex alternatives to be compared. For instance, a data collection pipeline may be characterized by parameters such as sensor sampling rates and the overall relevancy of retrieved samples. Alternatives to this pipeline are enabled by development vectors including ML, parallelization, advancing CMOS, and neuromorphic computing. By calculating metrics for each alternative such as overall F1 score, power, hardware cost, and energy expended per relevant sample, our model allows alternative data collection systems to be rigorously compared. We apply this model to the Compact Muon Solenoid experiment and its planned high luminosity-large hadron collider upgrade, evaluating novel technologies for the data acquisition system (DAQ), including ML-based filtering and parallelized software. The results demonstrate that improvements to early DAQ stages significantly reduce resources required later, with a power reduction of 60% and increased relevant data retrieval per unit power (from 0.065 to 0.31 samples/kJ). However, we predict that further advances will be required in order to meet overall power and cost constraints for the DAQ.

Olin-Ammentorp, Wilkie (ORCID:0000000224729862)↗

DOE OSTI2021

O3BNN-R: An Out-Of-Order Architecture for High-Performance and Regularized BNN Inference

Binarized Neural Networks (BNN) have drawn tremendous attention due to significantly reduced computational complexity and memory demand. They have especially shown great potential in cost- and power-restricted domains, such as IoT and smart edge-devices, where reaching a certain accuracy bar is often sufficient, and real-time is highly desired.In this work, we demonstrate that the highly-condensed BNN model can be shrunk significantly further by dynamically pruning irregular redundant edges. Based on two new observations on BNN-specific properties, an out-of-order (OoO) architecture – O3BNN-R, can curtail edge evaluation in cases where the binary output of a neuron can be determined early. Similar to Instruction-Level-Parallelism(ILP), these fine-grained, irregular, runtime pruning opportunities are traditionally presumed to be difficult to exploit. In order to increase the pruning opportunities, we also optimize the training process by adding 2 regularization items in the loss function (1) for pooling pruning and (2) for threshold pruning. We evaluate our design on an FPGA platform using three well-known networks, including VggNet-16, AlexNet for ImageNet, and a VGG-like network for Cifar-10.

Geng, Tong↗

DOE OSTI2021

Simulations of future particle accelerators: issues and mitigations

The ever increasing demands placed upon machine performance have resulted in the need for more comprehensive particle accelerator modeling. Computer simulations are key to the success of particle accelerators. Many aspects of particle accelerators rely on computer modeling at some point, sometimes requiring complex simulation tools and massively parallel supercomputing. Examples include the modeling of beams at extreme intensities and densities (toward the quantum degeneracy limit), and with ultra-fine control (down to the level of individual particles). In the future, adaptively tuned models might also be relied upon to provide beam measurements beyond the resolution of existing diagnostics. Much time and effort has been put into creating accelerator software tools, some of which are highly successful. However, there are also shortcomings such as the general inability of existing software to be easily modified to meet changing simulation needs. In this paper possible mitigating strategies are discussed for issues faced by the accelerator community as it endeavors to produce better and more comprehensive modeling tools. This includes lack of coordination between code developers, lack of standards to make codes portable and/or reusable, lack of documentation, among others.

43 PARTICLE ACCELERATORS↗