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Gyrator circuit consisting of dual operational amplifier and four resistors inverts impedance of capacitor to simulate inductor. Synthetic inductor has high Q factor, good stability, wide bandwidth, and easily determined value of inductance that is independent of frequency. It readily lends itself to integrated-circuit applications, including filter networks.
Application-specific-integrated-circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power, and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem, which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques, which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable, are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way that facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as a framework of software modules, templates, and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation.
The study of printed circuit discontinuities is necessary in order to design, for example, transitions between rectangular waveguides and printed circuits. New developments with respect to the analytical approaches to this problem are discussed. A summary of the progress in the experimental approach is presented. The accurate solution for the modes in various millimeter-wave waveguides is essential in the analysis of many integrated circuit components, such as filters and impedance transformers. Problems associated with the numerical computation of these modes in two frequently used waveguide forms, namely, the finline and microstrip, are presented. The spectral domain method of formulation, with a moment method solution, is considered. This approach can be readily extended to analyze an arbitrary configuration of dielectric and metallized regions in a shielded enclosure. Galerkin's method is used, where the testing and basic functions are the same. It is shown that the mode functions, or eigenfunctions, are more sensitive to errors than the phase constants, or eigenvalues. The approximate mode functions do not satisfy the orthogonality relationship well, resulting in difficulties when these modal solutions are used to form an approximate Green's function or are used in a mode matching analysis.
A process for directly integrating photoconductive lead sulfide (PbS) infrared detector material with silicon MOS integrated circuits has been developed primarily for application in long (greater than 10,000 detector elements) linear arrays for pushbroom scanning applications. The processing technology is based on the conventional PMOS and CMOS technologies with a variation in the metallization. Results and measurements on a fully integrated eight-element multiplexer are shown.
Abstract The quantum noise of light, attributed to the random arrival time of photons from a coherent light source, fundamentally limits optical phase sensors. An engineered source of squeezed states suppresses this noise and allows phase detection sensitivity beyond the quantum noise limit (QNL). We need ways to use quantum light within deployable quantum sensors. Here we present a photonic integrated circuit in thin-film lithium niobate that meets these requirements. We use the second-order nonlinearity to produce a squeezed state at the same frequency as the pump light and realize circuit control and sensing with electro-optics. Using 26.2 milliwatts of optical power, we measure (2.7 ± 0.2)% squeezing and apply it to increase the signal-to-noise ratio of phase measurement. We anticipate that photonic systems like this, which operate with low power and integrate all of the needed functionality on a single die, will open new opportunities for quantum optical sensing.
The need for both robust and unambiguous electronic designs is a direct requirement of the astonishing growth in design and manufacturing capability during recent years. In order to manage the plethora of designs, and have the design data both interchangeable and interoperable, the Very High Speed Integrated Circuits (VHSIC) program is developing two major standards for the electronic design community. The VHSIC Hardware Description Language (VHDL) is designed to be the lingua franca for transmission of design data between designers and their environments. The Engineering Information System (EIS) is designed to ease the integration of data betweeen diverse design automation systems. This paper describes the rationale for the necessity for these two standards and how they provide a synergistic expressive capability across the macrocosm of design environments.
The design and construction of a simple ASCII analyzer is described. It was built to interface directly to a Hewlett-Packard 1602A logic state analyzer but the circuitry could easily be configured to operate with any logic analyzer. The design of the ASCII analyzer allows the use of all the trace and delay functions for the HF-1602A. The ASCII analyzer circuit utilizes two universal Asynchronous Receiver/Transmitters (UAR/Ts) to simultaneously examine both the transmit and receive serial data lines. Baud rates from 300 to 9600 bits per second are selectable with the externally mounted DIP switch. The unit requires no external power supply connection and all of the integrated circuits are CMOS for low power consumption.
The James Webb Space Telescope's (JWST) Near Infrared Spectrograph (NIRSpec) incorporates two 5 micron cutoff (lambda(sub co) = 5 microns) 2048x2048 pixel Teledyne HgCdTe HAWAII-2RG sensor chip assemblies. These detector arrays, and the two Teledyne SIDECAR application specific integrated circuits that control them, are operated in space at T approx. 37 K. In this article, we provide a brief introduction to NIRSpec, its detector subsystem (DS), detector readout in the space radiation environment, and present a snapshot of the developmental status of the NIRSpec DS as integration and testing of the engineering test unit begins.
With the advent of monolithic microwave integrated circuit (MMIC) technology, the phased array has become a key component in the design of advanced antenna systems. Array-fed antennas are used extensively in today's multiple beam satellite antennas. A computer program based on a very efficient numerical technique for calculating the radiated power (Romberg integration), directivity, and radiation pattern of a phased array is described. The formulation developed is very general, and takes into account arbitrary element polarization, E- and H-plane element pattern, element location, and complex element excitation. For comparison purposes sample cases have been presented. Excellent agreement has been obtained for all cases. Also included are a user guide and a copy of the computer program.
A new millimeter-wave package architecture with supporting electrical, mechanical and material science experiment and analysis is presented. This package is well suited for discrete devices, monolithic microwave integrated circuits (MMIC's) and multichip module (MCM) applications. It has low-loss wide-band RF transitions which are necessary to overcome manufacturing tolerances leading to lower per unit cost Potential applications of this new packaging architecture which go beyond the standard requirements of device protection include integration of antennas, compatibility to photonic networks and direct transitions to waveguide systems. Techniques for electromagnetic analysis, thermal control and hermetic sealing were explored. Three dimensional electromagnetic analysis was performed using a finite difference time-domain (FDTD) algorithm and experimentally verified for millimeter-wave package input and output transitions. New multi-material system concepts (AlN, Cu, and diamond thin films) which allow excellent surface finishes to be achieved with enhanced thermal management have been investigated. A new approach utilizing block copolymer coatings was employed to hermetically seal packages which met MIL STD-883.
Mathematical model yields estimates of upper and lower bounds on rates of single-event upsets (SEU's) in logic circuits. SEU's are reversible changes in logic states, caused by single high-energy ions. Energetic ions passed through device along tracks perpendicular to surface, to determine parameters of model. Used to estimate rates caused by ions of various energies incident at arbitrary angles. Useful in design of integrated circuits as high-density memories for minimal susceptibility to bit errors.
Over the last few years, considerable progress have been made in the development of techniques for fabricating high-quality superconducting circuits, and this success, together with major advances in the theoretical understanding of quantum detection and mixing at millimeter and submillimeter wavelengths, has made the development of CAD techniques for superconducting nonlinear circuits an important new enterprise. For example, arrays of quasioptical mixers are now being manufactured, where the antennas, matching networks, filters and superconducting tunnel junctions are all fabricated by depositing niobium and a variety of oxides on a single quartz substrate. There are no adjustable tuning elements on these integrated circuits, and therefore, one must be able to predict their electrical behavior precisely. This requirement, together with a general interest in the generic behavior of devices such as direct detectors and harmonic mixers, has lead us to develop a range of CAD tools for simulating the large-signal, small-signal, and noise behavior of superconducting tunnel junction circuits.
Higher levels of integration through the use of GaAs and silicon MMIC devices, a die-cast housing, and the reduction of the number of subassemblies has enabled a large reduction of the size and weight of the electronics package for commercial and military satellite communications. This paper presents an electronics architecture and hardware that utilizes many new integrated circuits and design techniques, and allows flexibility for future satellite frequency changes and expansion. Key features of the radio are extended C-band, InSat, Defense Satellite Communications System (DSCS), and Ku-band coverage options; 70 (or 140) MHz transponder bandwidth or L-band block bandwidth IFs; integrated RS-232 control through local handheld terminal or remote computer; remote control of crystal reference oscillator for aging and temperature compensation; integrated 2 or 5 watt solid-state power amplifiers (SSPA); optional integrated solid-state booster amplifiers to 40 watts; optional external amplifiers to 100 watts; integral beacon tracking with second integrated downcoverter for antenna positioning; radio, including low-noise block converter (LNB) and SSPA, weighs 8.5 kg and measures 32 x 23 x 16.5 cm; environmentally ruggedized for -40 to +60 C; O-ring sealed for waterproofing; passive (convection) cooling; and simple cabling and installation, with a single cable between radio and LNB, and two cables between radio and IF interface. The small size and light weight of the radio make it ideal for mounting on stabilized antenna platforms (gyroscopic or servo). Several input power options (110 or 220 VAC; +48, +12, or -24 VDC) facilitate operation on multiple platforms.
Ribbon waveguides made of alumina or of semiconductors (Si, InP, or GaAs) have been proposed as low-loss transmission lines for coupling electronic components and circuits that operate at frequencies from 30 to 1,000 GHz. In addition to low losses (and a concomitant ability to withstand power levels higher than would otherwise be possible), the proposed ribbon waveguides would offer the advantage of compatibility with the materials and structures now commonly incorporated into integrated circuits. Heretofore, low-loss transmission lines for this frequency range have been unknown, making it necessary to resort to designs that, variously, place circuits and components to be coupled in proximity of each other and/or provide for coupling via free space through bulky and often lossy optical elements. Even chip-to-chip interconnections have been problematic in this frequency range. Metal wave-guiding structures (e.g., microstriplines and traditional waveguides) are not suitable for this frequency range because the skin depths of electromagnetic waves in this frequency range are so small as to give rise to high losses. Conventional rod-type dielectric waveguide structures are also not suitable for this frequency range because dielectric materials, including ones that exhibit ultralow losses at lower frequencies, exhibit significant losses in this frequency range. Unlike microstripline structures or metallic waveguides, the proposed ribbon waveguides would be free of metal and would therefore not be subject to skin-depth losses. Moreover, although they would be made of materials that are moderately lossy in the frequency range of interest, the proposed ribbon waveguides would cause the propagating electromagnetic waves to configure themselves in a manner that minimizes losses.
Including a one year No-Cost Extension, The University of California, Davis has been funded since 2020 to advance innovative millimeter-wave diagnostics for fusion plasma research. This work includes: (1) Developing and applying cutting-edge System-on-Chip millimeter wave Integrated Circuit (IC) technology for Electron Cyclotron Emission Imaging (ECEI) and Microwave Imaging Reflectometry (MIR) on the DIII-D tokamak and the NSTX-U spherical tokamak. (2) Development of radiation-hardened millimeter-wave chip for diagnostics in harsh environments, utilizing wide bandgap Gallium Nitride (GaN) semiconductors. (3) Integrating forward-modeling synthetic diagnostics to enable advanced, real-time plasma prediction and feedback control. Originally planned as a three-year program (2020–2023), the project was granted a one-year no-cost extension, extending its duration through the end of 2024.
In a modified configuration of a coaxial probe feed for a layered printed-circuit antenna (e.g., a microstrip antenna), the outer conductor of the coaxial cable extends through the thickness of at least one dielectric layer and is connected to both the ground-plane conductor and a radiator-plane conductor. This modified configuration simplifies the incorporation of such radio-frequency integrated circuits as power dividers, filters, and low-noise amplifiers. It also simplifies the design and fabrication of stacked antennas with aperture feeds.
This white paper has a technical focus meant to provide background to those unfamiliar with the challenges of high temperature electronics, and an understanding of why new surface mission concepts are now viable for Venus and other applications. It describes that, for the first time, high temperature electronics have been developed to enable a paradigm change in extended duration Venus surface exploration. This white paper concentrates on the advances made in Silicon Carbide (SiC) integrated circuit (IC) electronics that have matured to a state where a simple long-life scientific probe is feasible for Venus surface operations. These electronics have been demonstrated for more than a year at 500˚C, 60 days in high-fidelity simulated Venus surface conditions chamber, and have been integrated and demonstrated with prototype long-lived scientific observation sensor technology. Continued maturation of these needed high temperature electronics and sensors is ongoing in the Long-Lived In-Situ Solar System Explorer (LLISSE) project to provide an operational system including sensor control and operation, signal processing, power management, and communications in the early part of the 2020’s. A key focus of this work includes increasing the complexity and decreasing the power consumption of the ICs which will pave the way to enhanced capabilities, such as long-duration Venus seismic measurements. Other IC development efforts include high temperature memory, terrestrial based characterization of volcanic magma, and development of a simple microprocessor. This electronics has also shown to have exceptionally high radiation tolerance, and thus have relevance for a broad range of solar system exploration. Although presently at the level of complexity of 1970-1980 silicon-based electronics, such electronics can enable breakthroughs in Venus planetary exploration akin to 1970s-launched planetary exploration successes (such as Viking and Voyager).
A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.