A Survey of Constrained Gaussian Process Regression: Approaches and Implementation Challenges.
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Submitting a poster for the LDRD poster session. Please see the attachment for details.
In a three-phase, four-wire electrical distribution system, a zig-zag transformer and at least one Cascade Multilevel Modular Inverter (CMMI) is coupled between the distribution system and the neutral. A controller modulates the states of the H-bridges in the CMMI to build an AC waveform. The voltage is chosen by the controller in order to control an equivalent impedance that draws an appropriate neutral current through the transformer. This neutral current is generally chosen to cancel the neutral current sensed in the line. The chosen neutral current may be based on a remotely sensed imbalance, rather than on a local value, determined by the power utility as a critical load point in the system. The desired injection current is then translated by the controller into a desired zero-sequence reactive impedance, based on measurement of the local terminal voltage, allowing the controller to regulate the current without generating or consuming real power.
Systems, apparatuses, and methods for compacting multiple groups of micro-operations into individual cache lines of a micro-operation cache are disclosed. A processor includes at least a decode unit and a micro-operation cache. When a new group of micro-operations is decoded and ready to be written to the micro-operation cache, the micro-operation cache determines which set is targeted by the new group of micro-operations. If there is a way in this set that can store the new group without evicting any existing group already stored in the way, then the new group is stored into the way with the existing group(s) of micro-operations. Metadata is then updated to indicate that the new group of micro-operations has been written to the way. Additionally, the micro-operation cache manages eviction and replacement policy at the granularity of micro-operation groups rather than at the granularity of cache lines.
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