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At least 973 records · Page 54

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NASA NTRS1995

A digital boxcar integrator for IMS spectra

When trying to detect or quantify a signal at or near the limit of detectability, it is invariably embeded in the noise. This statement is true for nearly all detectors of any physical phenomena and the limit of detectability, hopefully, occurs at very low signal-to-noise levels. This is particularly true of IMS (Ion Mobility Spectrometers) spectra due to the low vapor pressure of several chemical compounds of great interest and the small currents associated with the ionic detection process. Gated Integrators and Boxcar Integrators or Averagers are designed to recover fast, repetitive analog signals. In a typical application, a time 'Gate' or 'Window' is generated, characterized by a set delay from a trigger or gate pulse and a certain width. A Gated Integrator amplifies and integrates the signal that is present during the time the gate is open, ignoring noise and interference that may be present at other times. Boxcar Integration refers to the practice of averaging the output of the Gated Integrator over many sweeps of the detector. Since any signal present during the gate will add linearly, while noise will add in a 'random walk' fashion as the square root of the number of sweeps, averaging N sweeps will improve the 'Signal-to-Noise Ratio' by a factor of the square root of N.

Cohen, Martin J.↗

NASA NTRS2009

High-Sensitivity GaN Microchemical Sensors

Systematic studies have been performed on the sensitivity of GaN HEMT (high electron mobility transistor) sensors using various gate electrode designs and operational parameters. The results here show that a higher sensitivity can be achieved with a larger W/L ratio (W = gate width, L = gate length) at a given D (D = source-drain distance), and multi-finger gate electrodes offer a higher sensitivity than a one-finger gate electrode. In terms of operating conditions, sensor sensitivity is strongly dependent on transconductance of the sensor. The highest sensitivity can be achieved at the gate voltage where the slope of the transconductance curve is the largest. This work provides critical information about how the gate electrode of a GaN HEMT, which has been identified as the most sensitive among GaN microsensors, needs to be designed, and what operation parameters should be used for high sensitivity detection.

Son, Kyung-ah↗

NASA NTRS2006

Four-Quadrant Analog Multipliers Using G4-FETs

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Mojarradi, Mohammad↗

NASA NTRS2018

Development of Possible Go-Around Criteria for Transport Aircraft

This paper adds data to help with the development of possible go-around criteria for transport category aircraft. Presently, airline procedures state that pilots make a go-around decision using multiple criteria at 1000 or 500 ft above the ground, or so-called gates. An experiment conducted on three level-D full-flight simulators investigated the conditions from which pilots cannot successfully recover from an unstable approach and make a normal landing. In addition, pilots' perceptions of risk under these various unstable approach conditions and resulting landings were assessed. Six crews, comprised of a captain and a first officer from the same airline, participated in each simulator. Both the captain and the first officer flew approaches and landings from 55 different initial conditions with varying gate heights, localizer deviations, glideslope deviations, reference-speed deviations, and rate of descents. The initial condition at the starting gate mainly affected longitudinal touchdown deviation and rate of descent at touchdown, with reference-speed deviation having the most significant effect. Results show little difference in touchdown performance for conditions from the 300-ft and 500-ft gates. Conditions at the 100-ft gate introduced significant differences in touchdown performance. Reference-speed and localizer deviation at the starting gate had the strongest influences on perceived risk and go-around decision. In line with other studies, these findings suggest that a 300-ft go-around gate might be acceptable. More research is required to investigate the effects of environmental and runway variables before possible go-around criteria for transport category aircraft can be defined.

GO-AROUNDS↗

DOE OSTI2020

Dimer interaction in the Hv1 proton channel

The voltage-gated proton channel Hv1 is a member of the voltage-gated ion channel superfamily, which stands out in design: It is a dimer of two voltage-sensing domains (VSDs), each containing a pore pathway, a voltage sensor (S4), and a gate (S1) and forming its own ion channel. Opening of the two channels in the dimer is cooperative. Part of the cooperativity is due to association between coiled-coil domains that extend intracellularly from the S4s. Interactions between the transmembrane portions of the subunits may also contribute, but the nature of transmembrane packing is unclear. Using functional analysis of a mutagenesis scan, biochemistry, and modeling, we find that the subunits form a dimer interface along the entire length of S1, and also have intersubunit contacts between S1 and S4. These interactions exert a strong effect on gating, in particular on the stability of the open state. Our results suggest that gating in Hv1 is tuned by extensive VSD–VSD interactions between the gates and voltage sensors of the dimeric channel.

59 BASIC BIOLOGICAL SCIENCES↗

DOE OSTI2025

Noise-aware circuit compilations for a continuously parameterized two-qubit gateset

State-of-the-art noisy-intermediate-scale quantum processors are currently implemented across a variety of hardware platforms, each with their own distinct gatesets. As such, circuit compilation should not only be aware of but also deeply connect to the native gateset and noise properties of each. Trapped-ion processors are one such platform that provides a gateset that can be continuously parameterized across both one- and two-qubit gates. Here we use the Quantum Scientific Computing Open User Testbed to study noise-aware compilations focused on continuously parameterized two-qubit 𝑍⁢𝑍 gates (based on the Mølmer-Sørensen interaction) using $\scriptsize{SUPERSTAQ}$, a quantum software platform for hardware-aware circuit compiler optimizations. We discuss the realization of 𝑍⁢𝑍 gates with arbitrary angle on the all-to-all connected trapped-ion system. Then we discuss a variety of different compiler optimizations that innately target these 𝑍⁢𝑍 gates and their noise properties. These optimizations include moving from a restricted maximally entangling gateset to a continuously parameterized one, swap mirroring to further reduce the total entangling angle of the operations, focusing the heaviest 𝑍⁢𝑍 angle participation on the best-performing gate pairs, and circuit approximation to remove the least impactful 𝑍⁢𝑍 gates. We demonstrate these compilation approaches on the hardware with randomized quantum volume circuits, observing the potential to realize a larger quantum volume as a result of these optimizations. Using differing yet complementary analysis techniques, we observe the distinct improvements in system performance provided by these noise-aware compilations and study the role of stochastic and coherent error channels for each compilation choice.

Noise↗

DOE OSTI2023

Neutral-atom entanglement using adiabatic Rydberg dressing

Here we revisit the implementation of a two-qubit entangling gate, the Mølmer-Sørensen gate, using the adiabatic Rydberg dressing paradigm for neutral atoms as studied in [A. Mitra et al., Phys. Rev. A 101, 030301(R) (2020)]. We study the implementation of rapid adiabatic passage using a two-photon transition, which does not require the use of an ultraviolet laser, and can be implemented using only amplitude modulation of one field with all laser frequencies fixed. We find that entangling gate fidelities, comparable to the one-photon excitation, are achievable with the two-photon excitation. Moreover, we address how the adiabatic dressing protocol can be used to implement entangling gates outside the regime of a perfect Rydberg blockade. We show that, by using adiabatic dressing, we can achieve scaling of the gate fidelity set by the fundamental limits to entanglement generated by the Rydberg interactions while simultaneously retaining a limited population in the doubly excited Rydberg state. This allows for fast high-fidelity gates for atoms separated beyond the blockade radius.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2025

Fast superconducting qubit control with subharmonic drives

Increasing the fidelity of single-qubit gates requires a combination of faster pulses and increased qubit coherence. However, these requirements can be contradictory. Additionally, increasing the drive power can heat the qubit’s environment and degrade coherence. In this work, we circumvent this issue and achieve rapid gates by pumping a transmon’s native Kerr at approximately one third of the qubit’s resonant frequency. The subharmonic Rabi rate of the process is proportional to applied drive amplitude cubed, allowing for rapid gates. In addition, we demonstrate that filtering can be used to protect the qubit’s coherence while performing rapid gates. Single qubit gates as short as 37.4 ns are demonstrated with fidelity of 99.91%. We present theoretical calculations indicating that drive induced multi-photon decay will not limit qubit lifetime; calculated power absorption also indicates that this technique could reduce cryostat heating for fast gates, a vital requirement for large-scale quantum computers.

Xia, Mingkang [Univ. of Pittsburgh, PA (United Sta↗

DOE OSTI2021

Timing characterization of fast hCMOS sensors

We describe a method of analyzing gate profile data for ultrafast x-ray imagers that allows pixel-by-pixel determination of temporal sensitivity in the presence of substantial background oscillations. With this method, systematic timing errors in gate width and gate arrival time of up to 1 ns (in a 2 ns wide gate) can be removed. In-sensor variations in gate arrival and gate width are observed, with variations in each up to 0.5 ns. This method can be used to estimate the coarse timing of the sensor, even if errors up to several ns are present.

Benedetti, L. R. (ORCID:0000000160502983)↗

DOE OSTI2023

Structural basis for severe pain caused by mutations in the voltage sensors of sodium channel NaV1.7

Voltage-gated sodium channels in peripheral nerves conduct nociceptive signals from nerve endings to the spinal cord. Mutations in voltage-gated sodium channel NaV1.7 are responsible for a number of severe inherited pain syndromes, including inherited erythromelalgia (IEM). Here, we describe the negative shifts in the voltage dependence of activation in the bacterial sodium channel NaVAb as a result of the incorporation of four different IEM mutations in the voltage sensor, which recapitulate the gain-of-function effects observed with these mutations in human NaV1.7. Crystal structures of NaVAb with these IEM mutations revealed that a mutation in the S1 segment of the voltage sensor facilitated the outward movement of S4 gating charges by widening the pathway for gating charge translocation. In contrast, mutations in the S4 segments modified hydrophobic interactions with surrounding amino acid side chains or membrane phospholipids that would enhance the outward movement of the gating charges. These results provide key structural insights into the mechanisms by which these IEM mutations in the voltage sensors can facilitate outward movements of the gating charges in the S4 segment and cause hyperexcitability and severe pain in IEM. Our work gives new insights into IEM pathogenesis at the near-atomic level and provides a molecular model for mutation-specific therapy of this debilitating disease.

60 APPLIED LIFE SCIENCES↗

DOE OSTI2021

Simulating non-native cubic interactions on noisy quantum machines

As a milestone for general-purpose computing machines, we demonstrate that quantum processors can be programed to efficiently simulate dynamics that are not native to the hardware. Moreover, on noisy devices without error correction, we show that simulation results are significantly improved when the quantum program is compiled using modular gates instead of a restricted set of standard gates. We demonstrate the general methodology by solving a cubic interaction problem, which appears in nonlinear optics, gauge theories, as well as plasma and fluid dynamics. To encode the non-native Hamiltonian evolution, we decompose the Hilbert space into a direct sum of invariant subspaces in which the nonlinear problem is mapped to a finite-dimensional Hamiltonian simulation problem. Furthermore, in a three-states example, the resultant unitary evolution is realized by a product of approximately 20 standard gates, using which approximately ten simulation steps can be carried out on state-of-the-art quantum hardware before results are corrupted by decoherence. In comparison, the simulation depth is improved by more than an order of magnitude when the unitary evolution is realized as a single cubic gate, which is compiled directly using optimal control. Alternatively, parametric gates may also be compiled by interpolating control pulses. Modular gates thus obtained provide high-fidelity building blocks for quantum Hamiltonian simulations.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2024

Block encodings of discrete subgroups on a quantum computer

We introduce a block encoding method for mapping discrete subgroups to qubits on a quantum computer. This method is applicable to general discrete groups, including crystal-like subgroups such as BI of S U ( 2 ) and V of S U ( 3 ) . We detail the construction of primitive gates—the inversion gate, the group multiplication gate, the trace gate, and the group Fourier gate—utilizing this encoding method for BT and for the first time BI group. We also provide resource estimations to extract the gluon viscosity. The inversion gates for BT and BI are benchmarked on the quantum computer with estimated fidelities of 40 − 4 + 5 % and 4 − 3 + 5 % , respectively. Published by the American Physical Society 2024

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2023

Charge per Micro-Pulse Calculation for Ideal Lujan and WNR beams

A complete redesign of the LANSCE front-end is currently under development for the Los Alamos Modernization Project (LAMP). This includes the replacement of the traditional Cockroft-Walton injection system to the newer radiofrequency quadrupole (RFQ) standard. LANSCE accelerates both H- and H+ beams and therefore requires an unconventional application for RFQ systems. A new facility could consider using an independent RFQ for each beam species. However, with the tight space of the LANSCE injector facility, it would prove difficult to instrument. Our initial studies have shown that a single RFQ could be used. The negatively- and positively-charged direct current (DC) beams are shaped, bunched, and accelerated out of phase to each other, with very little interaction. This would work for all possible H+ beam gates and most H- Beam gates. However, a challenge arises with the Weapons Neutron Research (WNR) beam structure that requires the acceleration of bunched beams at higher charge density per pulse. The Long Bunch Enable Gate (LBEG) used for the Lujan center is the best example of a standard injector beam gate. The beam gate, or Macro-Pulse (MP), is 625-us long, separated by at least 8.3 ms. A chopper is used to dice the MP into 1750 mini-Pulses (mP), which are 290-ns wide. After chopping, the MP contains 100,000 micro-Pulses (uP), which are generated by the linac acceleration structure modulated at 201.25 MHz; that is, the micro-Pulses are separated 5 ns apart from each other. The H+ beam structure will be very similar once a chopper is added to its transport. However, the Multi-Pulse Enable Gate (MPEG) used for WNR is significantly different in structure. In this case, the mP is chopped to be only 35-ns wide. This width is then rotated into a single 201.25 MHz RF bucket using the Low Frequency Buncher (LFB). This is proving difficult for the RFQ design in the LAMP upgrade. We began investigating the amount of current sent to WNR for two reasons. Firstly, we wanted to find a solution to avoid using the Low Frequency Buncher to simplify the LAMP RFQ design. It is simple to inject and accelerate a 35 mA DC beam in the LAMP RFQ (this is done in numerous accelerator facilities). However, injecting a short bunch with a larger current (once compressed to 5 ns to meet the RFQ frequency) may be difficult. Second, we have a technique called PSR2WNR in which we do not employ the Low Frequency Buncher, but rather accumulate 5 LBEG uP (5 ns) in the PSR and deliver the accumulated beam to WNR every 1.8 us. As a result, we could provide to WNR with five accumulated LBEG uPs every shot. The goal here is to create a rapid kicker with a frequency response of 555 kHz. DARHT-II and other accelerator facilities have constructed kickers of this type for other uses, and our engineers consider this technology as feasible.

43 PARTICLE ACCELERATORS↗

DOE OSTI2023

Design and Development of a Particle Flow Control Mechanism for Particle-Based CSP System Applications

Within particle-based Concentrated Solar Power Systems (CSP), particles are the heat transfer medium, and therefore, the heat transfer effectiveness of these systems is reliant on their ability to effectively control particle mass flow rate. The vast majority of approaches for particle flow control in high temperature CSP is based on a slide-gate approach where a gate is linearly actuated across a tear-drop shaped opening. The slide-gate mechanism has a sensitivity of 0.354 g/s-mm, which is defined as the mass flow rate over the position of the gate. In the present work, we have designed and tested a new particle flow control mechanism with the potential for faster response times and different sensitivities than a slide gate approach enabling more control of particle flow. The new device enables flow control through moving jaws diagonally to change the outlet area. The new devices sensitivity value follows a quadratic curved as compared to the slide-gate’s linear slope over the same jaw movement. A larger sensitivity value is directly related to a quicker response time when utilizing the same actuator.

14 SOLAR ENERGY↗

DOE OSTI2024

Development of a Particle Flow Control Mechanism

The next generation of Concentrated Solar Power (CSP) systems are utilizing solid particles as the heat transfer medium. The state-of-the-art particle flow control mechanism currently utilized is the slide-gate mechanism which functions by linearly actuating a gate across a tear-drop shaped opening. The sensitivity, which is a measure of the change in mass flow rate per unit movement of the slide-gate, is 0.354 g/s-mm[1]. The slide-gate’s main shortcomings include particle lodging and particle leakage between the plates, and difficulty actuating under the pressure from the particles. The goal of a new device is to minimize or eliminate these flaws. The new proposed device functions similar to a chuck mechanism in a drill where a rotation of an outer ring produces a change in outlet area through moving “jaws” diagonally. This mechanism aims to solve the issues of the slide-gate by having the jaws on the outside of the particle flow volume to reduce the probability of particle lodging, and the jaw tips are designed to overlap as they actuate to reduce particle leakage. Additionally, the vertical orientation of the device as well as the inclined movement of the jaws allows for easier actuation of the device under pressure. Experiments involving 3D printed prototypes have been carried out, producing a max mass flowrate of about 50 g/s and a sensitivity curve with the equation 𝑦 (𝑔/𝑠) = 0.0851𝑥^2(𝑔/𝑠−𝑚𝑚2) +3.6993𝑥(𝑔/𝑠−𝑚𝑚). These experiments validated the device’s capability to address the shortcomings of the slide-gate. Currently, an aluminum model of the device is being tested at room temperature, and a stainless-steel model is being developed to be tested at 700oC, which is the expected operating temperature of the CSP system. Furthermore, simulations are on-going to predict the mass flowrate of different device configurations at room and high temperatures.

14 SOLAR ENERGY↗

NASA NTRS1985

Fault models

A major problem in the qualification of integrated circuit cells and in the development of adequate tests for the circuits is to lack of information on the nature and density of fault models. Some of this information is being obtained from the test structures. In particular, the Pinhole Array Capacitor is providing values for the resistance of gate oxide shorts, and the Addressable Inverter Matrix is providing values for parameter distributions such as noise margins. Another CMOS fault mode, that of the open-gated transistor, is examined and the state of the transistors assessed. Preliminary results are described for a number of open-gated structures such as transistors, inverters, and NAND gates. Resistor faults are applied to various CMOS gates and the time responses are noted. The critical value for the resistive short to upset the gate response was determined.

Sayah, H. R.↗

NASA NTRS1989

Microwave field effect transistor

Electrodes of a high power, microwave field effect transistor are substantially matched to external input and output networks. The field effect transistor includes a metal ground plane layer, a dielectric layer on the ground plane layer, a gallium arsenide active region on the dielectric layer, and substantially coplanar spaced source, gate, and drain electrodes having active segments covering the active region. The active segment of the gate electrode is located between edges of the active segments of the source and drain electrodes. The gate and drain electrodes include inactive pads remote from the active segments. The pads are connected directly to the input and output networks. The source electrode is connected to the ground plane layer. The space between the electrodes and the geometry of the electrodes extablish parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the gate electrode and between the output network and the drain electrode. Many of the devices are connected in parallel and share a common active region, so that each pair of adjacent devices shares the same source electrodes and each pair of adjacent devices shares the same drain electrodes. The gate electrodes for the parallel devices are formed by a continuous stripe that extends between adjacent devices and is connected at different points to the common gate pad.

Huang, Ho-Chung↗

NASA NTRS1999

Integrating Partial Polarization into a Metal-Ferroelectric-Semiconductor Field Effect Transistor Model

The ferroelectric channel in a Metal-Ferroelectric-Semiconductor Field Effect Transistor (MFSFET) can partially change its polarization when the gate voltage near the polarization threshold voltage. This causes the MFSFET Drain current to change with repeated pulses of the same gate voltage near the polarization threshold voltage. A previously developed model [11, based on the Fermi-Dirac function, assumed that for a given gate voltage and channel polarization, a sin-le Drain current value would be generated. A study has been done to characterize the effects of partial polarization on the Drain current of a MFSFET. These effects have been described mathematically and these equations have been incorporated into a more comprehensive mathematical model of the MFSFET. The model takes into account the hysteresis nature of the MFSFET and the time dependent decay as well as the effects of partial polarization. This model defines the Drain current based on calculating the degree of polarization from previous gate pulses, the present Gate voltage, and the amount of time since the last Gate volta-e pulse.

MacLeod, Todd C.↗