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At least 955 records · Page 53

Symbiosis in cell evolution: Life and its environment on the early earth

The book treats cell evolution from the viewpoint of the serial endosymbiosis theory of the origin of organelles. Following a brief outline of the symbiotic theory, which holds that eukaryotes evolved by the association of free-living bacteria with a host prokaryote, the diversity of life is considered, and five kingdoms of organisms are distinguished: the prokaryotic Monera and the eukaryotic Protoctista, Animalia, Fungi and Plantae. Symbiotic and traditional direct filiation theories of cell evolution are compared. Recent observations of cell structure and biochemistry are reviewed in relation to early cell evolution, with attention given to the geological context for the origin of eukaryotic cells, the origin of major bacterial anaerobic pathways, the relationship between aerobic metabolism and atmospheric oxygen, criteria for distinguishing symbiotic organelles from those that originated by differentiation, and the major classes of eukaryotic organelles: mitochondria, cilia, microtubules, the mitotic and meiotic apparatuses, and pastids. Cell evolution during the Phanerozoic is also discussed with emphasis on the effects of life on the biosphere

Margulis, L.↗

Labeling Solar-Cell Modules

Photocopying machine produces durable identification label. Process used for double glass photovoltaic-cell modules. Matrix of cells sandwiched between thin, flexible glass mats and covered above and below by protective sheets of glass. Label contains such information as manufacturer, model number, voltage and power ratings, and serial number. May also contain electrical-shock hazard warning and identification of positive and negative terminals. Method saves expense of procuring and applying conventional labels.

Watson, E. G.↗

The VLSI design of a single chip Reed-Solomon encoder

A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

Truong, T. K.↗

RS-232 communications analyzer module for HP-1602A logic analyzer

The design and construction of a simple ASCII analyzer is described. It was built to interface directly to a Hewlett-Packard 1602A logic state analyzer but the circuitry could easily be configured to operate with any logic analyzer. The design of the ASCII analyzer allows the use of all the trace and delay functions for the HF-1602A. The ASCII analyzer circuit utilizes two universal Asynchronous Receiver/Transmitters (UAR/Ts) to simultaneously examine both the transmit and receive serial data lines. Baud rates from 300 to 9600 bits per second are selectable with the externally mounted DIP switch. The unit requires no external power supply connection and all of the integrated circuits are CMOS for low power consumption.

Yost, S. R.↗

Thematic mapper protoflight model preshipment review data package. Volume 4: Appendix. Part A: Multiplexer data book 2

Final performance test data for the thematic mapper flight model multiplexer are presented in tables. Aspects covered include A/D thresholds for bands 5, 6, and 7; cross talk; the thermistor; bilevel commands signal parameters; A/D threshold ambient, voltage margin low bus; serial data and bit clock parameters; and the wire check. Tests were conducted at ambient temperature.

Source record↗

Distributed multiport memory architecture

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

Kohl, W. H.↗

Using radar image simulation to assess relative geometric distortions inherent in radar imagery

A unique method for observing the relative contributions of backscatter and propagation effects is afforded by radar image simulation. Digital terrain data are used in modeling radar image formation. Backscatter and propagation effects are modeled separately. These are incorporated serially and the image expression of each is noted. Sequences of images are presented illustrating these effects over a range of slopes and angles of incidence. The conclusions reached are that at angles of incidence that are smaller than the average slope of the terrain in a region, propagation phenomena predominate. As the angle of incidence increases beyond this, the radar image portrays an increasingly faithful representation of the backscatter from the ground. It is also demonstrated that digital simulation affords an important tool for evaluating complex interactions between the ground and radar, for training users in radar image interpretation, and for selecting optimum sensor parameters for particular applications.

Kaupp, V. H.↗

The identification of the variation of atherosclerosis plaques by invasive and non-invasive methods

Computer-enhanced visualization of coronary arteries and lesions within them is discussed, comparing invasive and noninvasive methods. Trial design factors in computer lesions assessment are briefly discussed, and the use of the computer edge-tracking technique in that assessment is described. The results of a small pilot study conducted on serial cineangiograms of men with premature atherosclerosis are presented. A canine study to determine the feasibility of quantifying atherosclerosis from intravenous carotid angiograms is discussed. Comparative error for arterial and venous injection in the canines is determined, and the mode of processing the films to achieve better visualization is described. The application of the computer edge-tracking technique to an ultrasound image of the human carotid artery is also shown and briefly discussed.

Selzer, R. H.↗

Design and performance of the Stratospheric Aerosol and Gas Experiment II (SAGE II) instrument

Design and performance data are analyzed for the Stratospheric Aerosol and Gas Experiment II (SAGE II) instrument, which has been developed for the NASA Earth Radiation Budget Satellite (ERBS). SAGE II is designed to monitor globally, from 70 degrees S to 70 degrees N latitude, the vertical distribution of stratospheric aerosols, ozone, water vapor, and nitrogen dioxide by measuring the extinction of solar radiation through the earth's atmosphere during the ERBS observatory solar occultations. A flat scanning mirror reflects solar radiation into a Cassegrain type telescope, which forms a solar image on the entrance slit of a grating spectrometer. The instantaneous-field-of-view of the SAGE II is scanned along the vertical solar diameter by the elevation scan mirror. The optical system is contained within an azimuth gimbal which tracks the solar radiometric centroid during the data event, while the spectrometer isolates seven spectral wavelengths from 0.385-1.02 micrometers. The seven channels of the spectrometer use silicon photodiode dedectors operated in the photovoltaic mode. The detector outputs are multiplexed into a serial data stream for readout by the ERBS telemetry system, with each output being sampled 64 times per second and digitized to 12 bit resolution.

Zaun, N. H.↗

Reed-Solomon Encoder

Report presents mathematical principles of Berlekamp bit serial multiplier algorithm and its application to design of very-large-scale integrated (VLSI) encoders for Reed-Solomon error-correcting codes. Structure made readily on single chip of negatively doped channel metal oxide semiconductor.

Troung, T. K.↗

Feasibility study for a generalized gate logic software simulator

Unit-delay simulation, event driven simulation, zero-delay simulation, simulation techniques, 2-valued versus multivalued logic, network initialization, gate operations and alternate network representations, parallel versus serial mode simulation fault modelling, extension of multiprocessor systems, and simulation timing are discussed. Functional level networks, gate equivalent circuits, the prototype BDX-930 network model, fault models, identifying detected faults for BGLOSS are discussed. Preprocessor tasks, postprocessor tasks, executive tasks, and a library of bliss coded macros for GGLOSS are also discussed.

Mcgough, J. G.↗

Rodent CNS neuron development: Timing of cell birth and death

Data obtained from a staged series of single paired injections of tritiated thymidine to pregnant Wistar rats or C57B16/j mice on selected embryonic days and several postnatal times are reported. All injected specimens were allowed to come to term, each litter culled to six pups and specimens were sacrificed on PN28, with fixation and embedding for paraffin and plastic embedding. The results are derived from serial paraffin sections of PN28 animals exposed to autoradiographic processing and plotted with respect to heavily labelled cell nuclei present in the selected brain stem nuclei and sensory ganglia. Counts from each time sample/structure are totalled and the percentage of cells in the total labelled population/structure represented by each injection time interval plotted.

Keefe, J. R.↗

Algorithms for solving large sparse systems of simultaneous linear equations on vector processors

Very efficient algorithms for solving large sparse systems of simultaneous linear equations have been developed for serial processing computers. These involve a reordering of matrix rows and columns in order to obtain a near triangular pattern of nonzero elements. Then an LU factorization is developed to represent the matrix inverse in terms of a sequence of elementary Gaussian eliminations, or pivots. In this paper it is shown how these algorithms are adapted for efficient implementation on vector processors. Results obtained on the CYBER 200 Model 205 are presented for a series of large test problems which show the comparative advantages of the triangularization and vector processing algorithms.

David, R. E.↗

The vectorization of a ray tracing program for image generation

Ray tracing is a widely used method for producing realistic computer generated images. Ray tracing involves firing an imaginary ray from a view point, through a point on an image plane, into a three dimensional scene. The intersections of the ray with the objects in the scene determines what is visible at the point on the image plane. This process must be repeated many times, once for each point (commonly called a pixel) in the image plane. A typical image contains more than a million pixels making this process computationally expensive. A traditional ray tracing program processes one ray at a time. In such a serial approach, as much as ninety percent of the execution time is spent computing the intersection of a ray with the surface in the scene. With the CYBER 205, many rays can be intersected with all the bodies im the scene with a single series of vector operations. Vectorization of this intersection process results in large decreases in computation time. The CADLAB's interest in ray tracing stems from the need to produce realistic images of mechanical parts. A high quality image of a part during the design process can increase the productivity of the designer by helping him visualize the results of his work. To be useful in the design process, these images must be produced in a reasonable amount of time. This discussion will explain how the ray tracing process was vectorized and gives examples of the images obtained.

Plunkett, D. J.↗

MST radar transmitter control and monitor system

A generalized transmitter control and monitor card was developed using the Intel 8031 (8051 family) microprocessor. The design was generalized so that this card can be utilized for virtually any control application with only firmware changes. The block diagram appears in Figure 2. The card provides for local control using a 16 key keypad (up to 64 keys are supported). The local display is four digits of 7 segment LEDs. The display can indicate the status of all major system parameters and provide voltage readout for the analog signal inputs. The card can be populated with only the chips required for a given application. Fully populated, the card has two RS-232 serial ports for computer communications. It has a total of 48 TTL parallel lines that can define as either inputs or outputs in groups of four. A total of 32 analog inputs with a 0-5 volt range are supported. In addition, a real-time clock/calendar is available if required. A total of 16 k bytes of ROM and 16 k bytes of RAM is available for programming. This card can be the basis of virtually any monitor or control system with appropriate software.

Brosnahan, J. W.↗

The VAX/VMS device driver and user operation program for the Midwestern Astronomical Data Reduction and Analysis Facility PDS microdensitometer

The Midwestern astronomical data reduction and analysis facility (MADRAF) PDS microdensitometer which was the first astronomical PDS which was provided with a Motorola 6800 microprocessor control/interface and will be interfaced to a 32-bit instruction computer operating in a multiuser environment is outlined. Command and response handshaking are handled on an RS 232 serial line while data transfer occurs on a dedicated Direct Memory Access line. This set of conditions necessitated the creation of a specialized device for the system. The general outline of this software is discussed. The availability of an extraordinarily powerful computer opened the possibility of a user operating program of great versatility with diverse data destinations and formats, automatic documentation, and an extensive set of utilities which facilitate operations.

Anderson, C. M.↗

Memory-based parallel data output controller

A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.

Stattel, R. J.↗

Research in the design of high-performance reconfigurable systems

An initial design for the Bit Processor (BP) referred to in prior reports as the Processing Element or PE has been completed. Eight BP's, together with their supporting random-access memory, a 64 k x 9 ROM to perform addition, routing logic, and some additional logic, constitute the components of a single stage. An initial stage design is given. Stages may be combined to perform high-speed fixed or floating point arithmetic. Stages can be configured into a range of arithmetic modules that includes bit-serial one or two-dimensional arrays; one or two dimensional arrays fixed or floating point processors; and specialized uniprocessors, such as long-word arithmetic units. One to eight BP's represent a likely initial chip level. The Stage would then correspond to a first-level pluggable module. As both this project and VLSI CAD/CAM progress, however, it is expected that the chip level would migrate upward to the stage and, perhaps, ultimately the box level. The BP RAM, consisting of two banks, holds only operands and indices. Programs are at the box (high-level function) and system level. At the system level initial effort has been concentrated on specifying the tools needed to evaluate design alternatives.

Slotnick, D. L.↗