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At least 955 records · Page 53

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NASA NTRS1989

Docking mechanism for spacecraft

A system is presented for docking a space vehicle to a space station where a connecting tunnel for in-flight transfer of personnel is required. Cooperable coupling mechanisms include docking rings on the space vehicle and space station. The space station is provided with a tunnel structure, a retraction mechanism, and a docking ring. The vehicle coupling mechanism is designed to capture the station coupling mechanism, arrest relative spacecraft motions while limiting loads to acceptable levels, and then realign the spacecraft for final docking and tunnel interconnection. The docking ring of the space vehicle coupling mechanism is supported by linear attentuator actuator devices, each of which is controlled by a control system which receives loading information signals and attenuator stroke information signals from each device and supplies output signals for controlling its linear actuation to attenuate impact loading or to realign the spacecraft for final docking and tunnel interconnection. The retraction mechanism is used to draw the spacecraft together after initial contact and coupling. Tunnel trunnions, cooperative with the latches on the space vehicle constitute the primary structural tie between the spacecraft in final docked configuration.

Lange, Gregory A.↗

NASA NTRS1989

Fault tolerant hypercube computer system architecture

A fault-tolerant multiprocessor computer system of the hypercube type comprising a hierarchy of computers of like kind which can be functionally substituted for one another as necessary is disclosed. Communication between the working nodes is via one communications network while communications between the working nodes and watch dog nodes and load balancing nodes higher in the structure is via another communications network separate from the first. A typical branch of the hierarchy reporting to a master node or host computer comprises, a plurality of first computing nodes; a first network of message conducting paths for interconnecting the first computing nodes as a hypercube. The first network provides a path for message transfer between the first computing nodes; a first watch dog node; and a second network of message connecting paths for connecting the first computing nodes to the first watch dog node independent from the first network, the second network provides an independent path for test message and reconfiguration affecting transfers between the first computing nodes and the first switch watch dog node. There is additionally, a plurality of second computing nodes; a third network of message conducting paths for interconnecting the second computing nodes as a hypercube. The third network provides a path for message transfer between the second computing nodes; a fourth network of message conducting paths for connecting the second computing nodes to the first watch dog node independent from the third network. The fourth network provides an independent path for test message and reconfiguration affecting transfers between the second computing nodes and the first watch dog node; and a first multiplexer disposed between the first watch dog node and the second and fourth networks for allowing the first watch dog node to selectively communicate with individual ones of the computing nodes through the second and fourth networks; as well as, a second watch dog node operably connected to the first multiplexer whereby the second watch dog node can selectively communicate with individual ones of the computing nodes through the second and fourth networks. The branch is completed by a first load balancing node; and a second multiplexer connected between the first load balancing node and the first and second watch dog nodes, allowing the first load balancing node to selectively communicate with the first and second watch dog nodes.

Madan, Herb S.↗

NASA NTRS1988

The 30-GHz monolithic receive module

The fourth year progress is described on a program to develop a 27.5 to 30 GHz GaAs monolithic receive module for spaceborne-communication antenna feed array applications, and to deliver submodules for experimental evaluation. Program goals include an overall receive module noise figure of 5 dB, a 30 dB RF to IF gain with six levels of intermediate gain control, a five bit phase shifter, and a maximum power consumption of 250 mW. Submicron gate length single and dual gate FETs are described and applied in the development of monolithic gain control amplifiers and low noise amplifiers. A two-stage monolithic gain control amplifier based on ion implanted dual gate MESFETs was designed and fabricated. The gain control amplifier has a gain of 12 dB at 29 GHz with a gain control range of over 13 dB. A two-stage monolithic low noise amplifier based on ion implanted MESFETs which provides 7 dB gain with 6.2 dB noise figure at 29 GHz was also developed. An interconnected receive module containing LNA, gain control, and phase shifter submodules was built using the LNA and gain control ICs as well as a monolithic phase shifter developed previously under this program. The design, fabrication, and evaluation of this interconnected receiver is presented. Progress in the development of an RF/IF submodule containing a unique ion implanted diode mixer diode and a broadband balanced mixer monolithic IC with on-chip IF amplifier and the initial design of circuits for the RF portion of a two submodule receiver are also discussed.

Bauhahn, P.↗

NASA NTRS1990

Multiprocessor architecture: Synthesis and evaluation

Multiprocessor computed architecture evaluation for structural computations is the focus of the research effort described. Results obtained are expected to lead to more efficient use of existing architectures and to suggest designs for new, application specific, architectures. The brief descriptions given outline a number of related efforts directed toward this purpose. The difficulty is analyzing an existing architecture or in designing a new computer architecture lies in the fact that the performance of a particular architecture, within the context of a given application, is determined by a number of factors. These include, but are not limited to, the efficiency of the computation algorithm, the programming language and support environment, the quality of the program written in the programming language, the multiplicity of the processing elements, the characteristics of the individual processing elements, the interconnection network connecting processors and non-local memories, and the shared memory organization covering the spectrum from no shared memory (all local memory) to one global access memory. These performance determiners may be loosely classified as being software or hardware related. This distinction is not clear or even appropriate in many cases. The effect of the choice of algorithm is ignored by assuming that the algorithm is specified as given. Effort directed toward the removal of the effect of the programming language and program resulted in the design of a high-level parallel programming language. Two characteristics of the fundamental structure of the architecture (memory organization and interconnection network) are examined.

Standley, Hilda M.↗

NASA NTRS1991

Burst-Compression And -Expansion For TDMA Communication

Burst-compression and -expansion technique enables interconnection of users transmitting and receiving data at rates asynchronous with respect to clocks within ground terminals of satellite-switched, time-division-multiple-access (TDMA) communication network. Matrix switch aboard satellite routes bursts of data from source users received on uplink antennas to downlink antennas illuminating ground areas containing destination users. TDMA ground terminal compresses streams of data from source users into rapid bursts for transmission and reexpands bursts of received data into slower streams of data for delivery to destination users. Greater flexibility in interconnecting widely dispersed users achieved by use of hopping beams.

Budinger, James M.↗

NASA NTRS1990

Distributed computing system with dual independent communications paths between computers and employing split tokens

This is a distributed computing system providing flexible fault tolerance; ease of software design and concurrency specification; and dynamic balance of the loads. The system comprises a plurality of computers each having a first input/output interface and a second input/output interface for interfacing to communications networks each second input/output interface including a bypass for bypassing the associated computer. A global communications network interconnects the first input/output interfaces for providing each computer the ability to broadcast messages simultaneously to the remainder of the computers. A meshwork communications network interconnects the second input/output interfaces providing each computer with the ability to establish a communications link with another of the computers bypassing the remainder of computers. Each computer is controlled by a resident copy of a common operating system. Communications between respective ones of computers is by means of split tokens each having a moving first portion which is sent from computer to computer and a resident second portion which is disposed in the memory of at least one of computer and wherein the location of the second portion is part of the first portion. The split tokens represent both functions to be executed by the computers and data to be employed in the execution of the functions. The first input/output interfaces each include logic for detecting a collision between messages and for terminating the broadcasting of a message whereby collisions between messages are detected and avoided.

Rasmussen, Robert D.↗

NASA NTRS1991

Thermal cycle testing of Space Station Freedom solar array blanket coupons

Lewis Research Center is presently conducting thermal cycle testing of solar array blanket coupons that represent the baseline design for Space Station Freedom. Four coupons were fabricated as part of the Photovoltaic Array Environment Protection (PAEP) Program, NAS 3-25079, at Lockheed Missile and Space Company. The objective of the testing is to demonstrate the durability or operational lifetime of the solar array welded interconnect design within the durability or operational lifetime of the solar array welded interconnect design within a low earth orbit (LEO) thermal cycling environment. Secondary objectives include the observation and identification of potential failure modes and effects that may occur within the solar array blanket coupons as a result of thermal cycling. The objectives, test articles, test chamber, performance evaluation, test requirements, and test results are presented for the successful completion of 60,000 thermal cycles.

Scheiman, David A.↗

NASA NTRS1990

Experience with abstract notation one

The development of computer science has produced a vast number of machine architectures, programming languages, and compiler technologies. The cross product of these three characteristics defines the spectrum of previous and present data representation methodologies. With regard to computer networks, the uniqueness of these methodologies presents an obstacle when disparate host environments are to be interconnected. Interoperability within a heterogeneous network relies upon the establishment of data representation commonality. The International Standards Organization (ISO) is currently developing the abstract syntax notation one standard (ASN.1) and the basic encoding rules standard (BER) that collectively address this problem. When used within the presentation layer of the open systems interconnection reference model, these two standards provide the data representation commonality required to facilitate interoperability. The details of a compiler that was built to automate the use of ASN.1 and BER are described. From this experience, insights into both standards are given and potential problems relating to this development effort are discussed.

Harvey, James D.↗

NASA NTRS1991

Science network resources: Distributed systems

The Master Directory, which is overview information about whole data sets, is outlined. The data system environment is depicted. The question is explored of what is a prototype international directory including purpose and features. Advantages of on-line directories are listed. Interconnected directory assumptions are given. A description of given of DIF (Directory Interchange Format), which is an exchange file for directory information, along with information content of DIF and directories. The directory population status is given in a percentage viewgraph. The present and future directory interconnections status at GSFC is also listed.

Cline, Neal↗

NASA NTRS1990

Single event induced transients in I/O devices - A characterization

The results of single-event upset (SEU) testing performed to evaluate the parametric transients, i.e., amplitude and duration, in several I/O devices, and the impact of these transients are discussed. The failure rate of these devices is dependent on the susceptibility of interconnected devices to the resulting transient change in the output of the I/O device. This failure rate, which is a function of the susceptibility of the interconnected device as well as the SEU response of the I/O device itself, may be significantly different from an upset rate calculated without taking these factors into account. The impact at the system level is discussed by way of an example.

Newberry, D. M.↗

NASA NTRS1990

Optimized testing of meshes

Efficient testing techniques for two-dimensional mesh interconnection networks are presented. The tests cover faults in the arbitration logic of the switches; this includes an examination of fault detection in the data paths, routing, and control circuitry, including the conflict resolution capabilities of mesh interconnection networks using topological test methods. The proposed methods are not implementation specific and can be applied to any design with a mesh topology. The topology and behavior of the network are described and definitions are presented. The fault model is defined and parallel testing methods for the entire network are given.

Malek, Miroslaw↗

NASA NTRS1991

Time variant analysis of large scale constrained rotorcraft systems dynamics - An exploitation of IBM-3090 vector-processor's pipe-lining feature

A generalized algorithmic procedure is presented for handling the constraints in transmissions, which are treated as a multibody system of interconnected rigid/flexible bodies. The type of constraints are classified based on the interconnection of the bodies, assuming one or more points of contact to exist between them. The method is explained through flow charts and configuration/interaction tables. A significant increase in speed of execution is achieved by vectorizing the developed code in computationally intensive areas. The study of an example consisting of two meshing disks rotating at high angular velocity is carried out. The dynamic behavior of the constraint forces associated with the generalized coordinates of the system are plotted by selecting various modes. Applications are intended for the study of dynamic and subsequent prediction of constraint forces at the gear teeth contacting points in helicopter transmissions with the aim of improving performance dependability.

Amirouche, F. M. L.↗

NASA NTRS1990

Custom CMOS Reed Solomon coder for the Hubble Space Telescope

A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.

Whitaker, S.↗

NASA NTRS1992

Flexible, Thin-Film Solar-Cell Blanket

Much of available area used to absorb solar energy. Proposed blanket of solar photovoltaic cells mounted on exterior surface of equipment it powers. Readily conforms to irregular shapes. Does not require separate supporting structure and saves space. Not added on to equipment but constitutes an integral part of it. Interconnection wiring deposited on sheet photolithographically or by other suitable masking/fabrication methods. Complete blanket, including cells and interconnections, fabricated as rigid unit directly on, and supported by, nonplanar surface to be covered.

Stella, Paul M.↗

NASA NTRS1991

A Large-Grain Mapping Approach for Multiprocessor Systems Through Data Flow Model Ph.D. Thesis

A large-grain level mapping method is presented of numerical oriented applications onto multiprocessor systems. The method is based on the large-grain data flow representation of the input application and it assumes a general interconnection topology of the multiprocessor system. The large-grain data flow model was used because such representation best exhibits inherited parallelism in many important applications, e.g., CFD models based on partial differential equations can be presented in large-grain data flow format, very effectively. A generalized interconnection topology of the multiprocessor architecture is considered, including such architectural issues as interprocessor communication cost, with the aim to identify the 'best matching' between the application and the multiprocessor structure. The objective is to minimize the total execution time of the input algorithm running on the target system. The mapping strategy consists of the following: (1) large-grain data flow graph generation from the input application using compilation techniques; (2) data flow graph partitioning into basic computation blocks; and (3) physical mapping onto the target multiprocessor using a priority allocation scheme for the computation blocks.

Kim, Hwa-Soo↗

NASA NTRS1992

Artificial intelligence approach to planning the robotic assembly of large tetrahedral truss structures

An assembly planner for tetrahedral truss structures is presented. To overcome the difficulties due to the large number of parts, the planner exploits the simplicity and uniformity of the shapes of the parts and the regularity of their interconnection. The planning automation is based on the computational formalism known as production system. The global data base consists of a hexagonal grid representation of the truss structure. This representation captures the regularity of tetrahedral truss structures and their multiple hierarchies. It maps into quadratic grids and can be implemented in a computer by using a two-dimensional array data structure. By maintaining the multiple hierarchies explicitly in the model, the choice of a particular hierarchy is only made when needed, thus allowing a more informed decision. Furthermore, testing the preconditions of the production rules is simple because the patterned way in which the struts are interconnected is incorporated into the topology of the hexagonal grid. A directed graph representation of assembly sequences allows the use of both graph search and backtracking control strategies.

Homemdemello, Luiz S.↗

NASA NTRS1992

Superconductivity devices: Commercial use of space

High T sub C superconducting thick film were prepared by a screen printing process. Y-based (YBa2Cu3O(7-x) superconducting thick film were printed on 211/Al2O3, SNT/Al2O3, and YSZ substrates. Because of poor adhesion of the superconductor thick films to 211/Al2O3 and SNT/Al2O3 substrates, relatively low T sub C and J sub C values were obtained from the films printed on these substrates. Critical temperatures (T sub C) of YBa2Cu3O(7-x) thick films deposited on 211/Al2O3 and SNT/Al2O3 substrates were about 80 K. The critical current densities (J sub C) of these films were less than 2 A/sq cm. Higher T sub C and J sub C YBa2Cu3O(7-x) thick films were printed on YSZ substrates. A YBa2Cu3O(7-x) thick film with T sub C=86.4 and J sub C= 50.4 A/sq cm was prepared by printing the film on YSZ substrate and firing at 990 C for 10 minutes. Multiple-lead samples were also prepared on the YSZ substrates. The multiple-lead samples showed lower T sub C and/or J sub C values than those of the plain samples. The electrical properties of YBa2Cu3O(7-x) thick films were determined by the microstructures of the films. The YBa2Cu3O(7-x) thick films printed on the YSZ substrates, which had the best properties among the films printed on the three different kinds of substrates, had the highest density and the best particle interconnection. The YBa2Cu3O(7-x) thick films with preferred orientation in (001) direction were obtained on the YSZ substrates. Cracks, which retard the properties of the films, were found from the films deposited on the YSZ substrates. Currently, a MSZ (Magnesium Stabilized Zirconia) substrate, which had higher thermal expansion coefficient than the YSZ substrate, is used as substrate for the YBa2Cu3O(7-x) thick film in order to eliminate the cracks on the film. Bi-based superconductor thick films were printed on polycrystalline MgO and YSZ substrates. Interactions between BSCCO thick films and the YSZ substrates were observed. Various buffer layer materials were applied onto the substrates in order to avoid the interactions between the BSCCO thick films and the ZrO2-based substrates. So far, a BSCCO printed on MgO substrate with T Sub C=89K was obtained. The J sub C of the film was lower than 0.1 A/sq cm by reason of poor interconnectivity of the BSCCO particles.

Haertling, Gene↗

NASA NTRS1993

Scalable Optical-Fiber Communication Networks

Scalable arbitrary fiber extension network (SAFEnet) is conceptual fiber-optic communication network passing digital signals among variety of computers and input/output devices at rates from 200 Mb/s to more than 100 Gb/s. Intended for use with very-high-speed computers and other data-processing and communication systems in which message-passing delays must be kept short. Inherent flexibility makes it possible to match performance of network to computers by optimizing configuration of interconnections. In addition, interconnections made redundant to provide tolerance to faults.

Chow, Edward T.↗