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At least 955 records · Page 53
All sourcesNASA NTRSDOE OSTI
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1998

Computational Modeling of Semiconductor Dynamics at Femtosecond Time Scales

The Interchange No. NCC2-5149 deals with the emerging technology of photonic (or optoelectronic) integrated circuits (PICs or OEICs). In PICs, optical and electronic components are grown together on the same chip. To build such devices and subsystems, one needs to model the entire chip. PICs are useful for building components for integrated optical transmitters, integrated optical receivers, optical data storage systems, optical interconnects, and optical computers. For example, the current commercial rate for optical data transmission is 2.5 gigabits per second, whereas the use of shorter pulses to improve optical transmission rates would yield an increase of 400 to 1000 times. The improved optical data transmitters would be used in telecommunications networks and computer local-area networks. Also, these components can be applied to activities in space, such as satellite to satellite communications, when the data transmissions are made at optical frequencies. The research project consisted of developing accurate computer modeling of electromagnetic wave propagation in semiconductors. Such modeling is necessary for the successful development of PICs. More specifically, these computer codes would enable the modeling of such devices, including their subsystems, such as semiconductor lasers and semiconductor amplifiers in which there is femtosecond pulse propagation. Presently, there are no computer codes that could provide this modeling. Current codes do not solve the full vector, nonlinear, Maxwell's equations, which are required for these short pulses and also current codes do not solve the semiconductor Bloch equations, which are required to accurately describe the material's interaction with femtosecond pulses. The research performed under NCC2-5149 solves the combined Maxwell's and Bloch's equations.

Agrawal, Govind P.↗
DOE OSTI2025

A virtual Frisch-grid geometry-based CZT gamma detector for in-field radioisotope identification

Here, we present a Virtual Frisch-Grid geometry-based CZT gamma detector developed for identifying different radioisotopes over an energy range from a few keV up to 2 MeV, and useful for efficient characterization of CZT crystals. The detector is built with a 3 x 3 matrix of CZT crystals, each measuring approximately 6 mm x 6 mm x 15 mm. The charge generated within the sensor’s active volume is read out via an anode connected directly to the AVG3_Dev integrated circuit. A current signal induced by charge drift is collected on side pads of the crystals, enabling reconstruction of a 3D interaction position. This paper discusses the design, development, and performance of the standalone, mobile detector system, which integrates the AVG3_Dev readout IC developed at Brookhaven National Laboratory, a high-speed FPGA-based with per-channel digital signal processing, and embedded system capabilities. The device is compact, battery-powered, and supports wireless data streaming, making it suitable for field operations for radioisotope identification.

47 OTHER INSTRUMENTATION↗
NASA NTRS2006

Neuro-Prosthetic Implants With Adjustable Electrode Arrays

Brushlike arrays of electrodes packaged with application-specific integrated circuits (ASICs) are undergoing development for use as electronic implants especially as neuro-prosthetic devices that might be implanted in brains to detect weak electrical signals generated by neurons. These implants partly resemble the ones reported in Integrated Electrode Arrays for Neuro-Prosthetic Implants (NPO-21198), NASA Tech Briefs, Vol. 27, No. 2 (February 2003), page 48. The basic idea underlying both the present and previously reported implants is that the electrodes would pick up signals from neurons and the ASICs would amplify and otherwise preprocess the signals for monitoring by external equipment. The figure presents a simplified and partly schematic view of an implant according to the present concept. Whereas the electrodes in an implant according to the previously reported concept would be microscopic wires, the electrodes according to the present concept are in the form of microscopic needles. An even more important difference would be that, unlike the previously reported concept, the present concept calls for the inclusion of microelectromechanical actuators for adjusting the depth of penetration of the electrodes into brain tissue. The prototype implant now under construction includes an array of 100 electrodes and corresponding array of electrode contact pads formed on opposite faces of a plate fabricated by techniques that are established in the art of microelectromechanical systems (MEMS). A mixed-signal ASIC under construction at the time of reporting the information for this article will include 100 analog amplifier channels (one amplifier per electrode). On one face of the mixed-signal ASIC there will be a solder-bump/micro-pad array that will have the same pitch as that of the electrode array, and that will be used to make the electrical and mechanical connections between the electrode array and the ASIC. Once the electrode array and the ASIC are soldered together, the remaining empty space between them will be filled with a biocompatible epoxy, the remaining exposed portions of the ASIC will be covered with micromachined plates for protection against corrosive bodily fluids, and then the ASIC and its covering micromachined plates will be coated with parylene

Whitacre, Jay↗
NASA NTRSDate not supplied

Science Yield Estimates and Sensitivities With the AstroPIC Integrated Photonic Coronagraph for the Habitable Worlds Observatory

The Habitable Worlds Observatory (HWO) flagship has a goal to survey ~100 of the nearest stellar systems and their habitable zones in order to detector and spectroscopically characterize ~25 potentially “Earth-like planets” (or “Exoearths”). The HWO telescope will feature a >6-m diameter aperture and a coronagraph that will suppress starlight by ten orders of magnitude to enable the detection and characterization of Earth analogues in the habitable zone. Three Exploratory Analytic Cases (EACs) are currently considering different aperture configurations for HWO including on-axis and off-axis apertures and both different hexagonal and keystone segmentation configurations. Photonic Integrated Circuits (PICs) offer a path to miniaturize traditional, bulk optics coronagraph functionality reducing risk margins and increasing mission science exoearth yields for the HWO mission. We have developed a simulation pipeline that enables evaluation of the AstroPIC photonic integrated coronagraph through to estimates mission yields. We present sensitivities to aberrations for different types of segmentation and low-order aberrations for HWO EACs demonstrating that AstroPIC is suitable for both on-axis and off-axis configurations. We perform a parametric sweep of the exoearth science yield sensitivities in terms of key coronagraph parameters including coronagraphic end-to-end throughput, inner working angle, robustness to aberrations, and bandwidth. We consider both a hybrid and a pure photonic architecture; a pure integrated photonic architecture provides the greatest potential in science yield improvements, although a hybrid PIC limited in its numbers of modes can provide complementary science to a traditional, bulk-optic coronagraph and increasing the estimated science yield when operated jointly.

Photonics↗
NASA NTRS2012

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Suarez, George↗
DOE OSTI2026

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗
DOE OSTI2025

Design of Digital Acquisition for Beam Current Monitor

As a part of the Proton Improvement Plan II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, Turner [Fermilab] (ORCID:0009000348159256)↗
NASA NTRS1986

Long-Term Electronic Timer

Timing circuit turns on power source on command, then turns it off again after preset interval. In comparison with prior devices, unit consumes little power and is smaller, lighter in weight, and less complicated. Timer includes oscillator and counter in integrated circuit. Timing interval equals oscillator period multiplied by number of cycles to be counted.

Temple, G.↗
DOE OSTI2023

A novel approach to interface high-Q Fabry–Pérot resonators with photonic circuits

The unique benefits of Fabry–Pérot resonators as frequency-stable reference cavities and as an efficient interface between atoms and photons make them an indispensable resource for emerging photonic technologies. To bring these performance benefits to next-generation communications, computation, and time-keeping systems, it will be necessary to develop strategies to integrate compact Fabry–Pérot resonators with photonic integrated circuits. In this paper, we demonstrate a novel reflection cancellation circuit that utilizes a numerically optimized multi-port polarization-splitting grating coupler to efficiently interface high-finesse Fabry–Pérot resonators with a silicon photonic circuit. This circuit interface produces a spatial separation of the incident and reflected waves, as required for on-chip Pound–Drever–Hall frequency locking, while also suppressing unwanted back reflections from the Fabry–Pérot resonator. Using inverse design principles, we design and fabricate a polarization-splitting grating coupler that achieves 55% coupling efficiency. This design realizes an insertion loss of 5.8 dB for the circuit interface and more than 9 dB of back reflection suppression, and we demonstrate the versatility of this system by using it to interface several reflective off-chip devices.

Optics↗
NASA NTRS2009

Differential InP HEMT MMIC Amplifiers Embedded in Waveguides

Monolithic microwave integrated-circuit (MMIC) amplifiers of a type now being developed for operation at frequencies of hundreds of gigahertz contain InP high-electron-mobility transistors (HEMTs) in a differential configuration. The differential configuration makes it possible to obtain gains greater than those of amplifiers having the single-ended configuration. To reduce losses associated with packaging, the MMIC chips are designed integrally with, and embedded in, waveguide packages, with the additional benefit that the packages are compact enough to fit into phased transmitting and/or receiving antenna arrays. Differential configurations (which are inherently balanced) have been used to extend the upper limits of operating frequencies of complementary metal oxide/semiconductor (CMOS) amplifiers to the microwave range but, until now, have not been applied in millimeter- wave amplifier circuits. Baluns have traditionally been used to transform from single-ended to balanced configurations, but baluns tend to be lossy. Instead of baluns, finlines are used to effect this transformation in the present line of development. Finlines have been used extensively to drive millimeter- wave mixers in balanced configurations. In the present extension of the finline balancing concept, finline transitions are integrated onto the affected MMICs (see figure). The differential configuration creates a virtual ground within each pair of InP HEMT gate fingers, eliminating the need for inductive vias to ground. Elimination of these vias greatly reduces parasitic components of current and the associated losses within an amplifier, thereby enabling more nearly complete utilization of the full performance of each transistor. The differential configuration offers the additional benefit of multiplying (relative to the single-ended configuration) the input and output impedances of each transistor by a factor of four, so that it is possible to use large transistors that would otherwise have prohibitively low impedances. Yet another advantage afforded by the virtual ground of the differential configuration is elimination of the need for a ground plane and, hence, elimination of the need for back-side metallization of the MMIC chip. In turn, elimination of the back-side metallization simplifies fabrication, reduces parasitic capacitances, and enables mounting of the MMIC in the electric-field plane ("E-plane") of a waveguide. E-plane mounting is consistent with (and essential for the utility of) the finline configuration, in which transmission lines lie on a dielectric sheet in the middle of a broad side of the waveguide. E-plane mounting offers a combination of low loss and ease of assembly because no millimeter-wave wire bonds or transition substrates are required. Moreover, because there is no ground plane behind the MMIC, the impedance for the detrimental even (single-ended) mode is high, suppressing coupling to that mode. Still another advantage of E-plane mounting is that the fundamental waveguide mode is inherently differential, eliminating the need for a balun to excite the differential mode.

Kangaslahti, Pekka↗
NASA NTRS1989

Monolithic Microwave Switching Matrix

Gallium arsenide integrated-circuit chip switches any of three microwave input signals to any of three output ports. Measuring 4.9 mm on side, chip contains nine field-effect transistor (FET) crosspoint switches. Housed in custom-designed package with standard connectors for easy integration into system. FET's on chip operated as passive switches and consume no static power and insignificant amounts of switching power. Chip module cascades with similar modules into large arrays handling as many as 100 inputs and 100 outputs. Applications include switching and routing vast amounts of data between computers at extremely high speed. On communications satellite, chip switches microwave signals to and from Earth stations and other satellites.

Fujikawa, Gene↗
NASA NTRS1995

Semiconductor/High-Tc-Superconductor Hybrid ICs

Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

Burns, Michael J.↗
NASA NTRS2010

Demonstration of a Submillimeter-Wave HEMT Oscillator Module at 330 GHz

In this work, radial transitions have been successfully mated with a HEMT-based MMIC (high-electron-mobility-transistor-based monolithic microwave integrated circuit) oscillator circuit. The chip has been assembled into a WR2.2 waveguide module for the basic implementation with radial E-plane probe transitions to convert the waveguide mode to the MMIC coplanar waveguide mode. The E-plane transitions have been directly integrated onto the InP substrate to couple the submillimeter-wave energy directly to the waveguides, thus avoiding wire-bonds in the RF path. The oscillator demonstrates a measured 1.7 percent DC-RF efficiency at the module level. The oscillator chip uses 35-nm-gate-length HEMT devices, which enable the high frequency of oscillation, creating the first demonstration of a packaged waveguide oscillator that operates over 300 GHz and is based on InP HEMT technology. The oscillator chip is extremely compact, with dimensions of only 1.085 x 320 sq mm for a total die size of 0.35 sq mm. This fully integrated, waveguide oscillator module, with an output power of 0.27 mW at 330 GHz, can provide low-mass, low DC-power-consumption alternatives to existing local oscillator schemes, which require high DC power consumption and large mass. This oscillator module can be easily integrated with mixers, multipliers, and amplifiers for building high-frequency transmit and receive systems at submillimeter wave frequencies. Because it requires only a DC bias to enable submillimeter wave output power, it is a simple and reliable technique for generating power at these frequencies. Future work will be directed to further improving the applicability of HEMT transistors to submillimeter wave and terahertz applications. Commercial applications include submillimeter-wave imaging systems for hidden weapons detection, airport security, homeland security, and portable low-mass, low-power imaging systems

Radisic, Vesna↗
DOE OSTI2023

Programmable photonic integrated meshes for modular generation of optical entanglement links

Abstract Large-scale generation of quantum entanglement between individually controllable qubits is at the core of quantum computing, communications, and sensing. Modular architectures of remotely-connected quantum technologies have been proposed for a variety of physical qubits, with demonstrations reported in atomic and all-photonic systems. However, an open challenge in these architectures lies in constructing high-speed and high-fidelity reconfigurable photonic networks for optically-heralded entanglement among target qubits. Here we introduce a programmable photonic integrated circuit (PIC), realized in a piezo-actuated silicon nitride (SiN)-in-oxide CMOS-compatible process, that implements an N × N Mach–Zehnder mesh (MZM) capable of high-speed execution of linear optical transformations. The visible-spectrum photonic integrated mesh is programmed to generate optical connectivity on up to N = 8 inputs for a range of optically-heralded entanglement protocols. In particular, we experimentally demonstrated optical connections between 16 independent pairwise mode couplings through the MZM, with optical transformation fidelities averaging 0.991 ± 0.0063. The PIC’s reconfigurable optical connectivity suffices for the production of 8-qubit resource states as building blocks of larger topological cluster states for quantum computing. Our programmable PIC platform enables the fast and scalable optical switching technology necessary for network-based quantum information processors.

47 OTHER INSTRUMENTATION↗
NASA NTRS1981

SEM analysis of ionizing radiation effects in an analog to digital converter /AD571/

The considered investigation is concerned with the study of the total-dose degradation mechanisms in an IIL analog to digital (A/D) converter. The A/D converter is a 10 digit device having nine separate functional units on the chip which encompass several hundred transistors and circuit elements. It was the objective of the described research to find the radiation sensitive elements by a systematic search of the devices on the LSI chip. The employed technique using a scanning electron microscope to determine the functional blocks of an integrated circuit which are sensitive to ionizing radiation and then progressively zeroing in on the soft components within those blocks, proved extremely successful on the AD571. Four functional blocks were found to be sensitive to radiation, including the Voltage Reference, DAC, IIL Clock, and IIL SAR.

Gauthier, M. K.↗