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At least 955 records · Page 53
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Universal topological quantum computation with strongly correlated Majorana edge modes

Abstract Majorana-based quantum gates are not complete for performing universal topological quantum computation while Fibonacci-based gates are difficult to be realized electronically and hardly coincide with the conventional quantum circuit models. In reference Hu and Kane (2018 Phys. Rev. Lett. 120 066801), it has been shown that a strongly correlated Majorana edge mode in a chiral topological superconductor can be decomposed into a Fibonacci anyon τ and a thermal operator anyon ɛ in the tricritical Ising model. The deconfinement of τ and ɛ via the interaction between the fermion modes yields the anyon collisions and gives the braiding of either τ or ɛ . With these braidings, the complete members of a set of universal gates, the Pauli gates, the Hadamard gate and extra phase gates for one-qubit as well as controlled-NOT (CNOT) gate for two-qubits, are topologically assembled. Encoding quantum information and reading out the computation results can be carried out through electric signals. With the sparse-dense mixed encodings, we set up the quantum circuit where the CNOT gate turns out to be a probabilistic gate and design the corresponding devices with thin films of the chiral topological superconductor. As an example of the universal topological quantum computing, we show the application to Shor’s integer factorization algorithm.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS1974

High isolation RF signal selection switches

A selection switch with high isolation between RF signal input terminals is achieved with a gated Schmitt trigger circuit feeding into a control NAND gate in each signal switching channel. The control NAND gates of the separate signal channels are coupled to an output terminal by a single NAND gate. The schmitt trigger circuits and all gates are implemented with Schottky transistor-transistor logic circuits having input clamping diodes. Each Schmitt trigger circuit includes two cascaded NAND gates and a feedback isolation Schottky diode between one input terminal connected to receive an RF input and another input terminal connected to receive a feedback signal from the second of the two cascaded NAND gates. Both NAND gates of the Schmitt trigger circuits are enabled by the same switch control signal which enables the control gates.

Hanna, M. F.↗
DOE OSTI2021

Extraction of intrinsic contact resistance in organic thin-film transistors with single channel length and high capacitance density

Accurate characterization of the intrinsic contact resistance is important for the optimization of organic thin-film transistors (OTFTs), especially in devices with high gate capacitance density. This study reports on a method for the extraction of the intrinsic, or gate-voltage independent, contact resistance from OTFTs. In contrast to the transfer length method (TLM), this method can be applied to devices with a single geometry. The method is an extension of the previously reported Y-function method and combines the model proposed by S. Luan et al. to analyze the effect of the gate voltage on the contact resistance. Here, this method is first applied to OTFTs with a bottom-gate top-contact geometry having varying gate capacitance density values. The intrinsic contact resistance is found to decrease with increased gate capacitance density with values ranging between 4 kΩcm and under 1 kΩcm when the gate capacitance is changed from 36.6 nF/cm 2 to 231.7 nF/cm 2 , respectively. These values are in good agreement with those obtained using TLM experiments. The new method is also shown to be applicable to OTFTs with top-gate bottom contact geometry.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Electrostatic modulation of the lateral carrier density profile in field effect devices with nonlinear dielectrics

The properties of two-dimensional (2D) electronic systems are often effectively controlled using electrostatic gating. The geometry of such field effect devices influences the effectiveness of the gate and the carrier density profile in the 2D device. Here, in this work, we analyze the gate-induced spatial variations in the lateral carrier density in patterned LaAlO 3 /SrTiO 3 devices. We model the electrostatics of the 2D interface using the Thomas-Fermi approximation and compute the gate-induced charge distribution at the interface. We show that the electric field lines generated by the gate are focused at the edges of the device, causing an increased depletion near its edges. This effect is accentuated in LaAlO 3 /SrTiO 3 due to the large, nonlinear dielectric constant of the substrate, and the large distance between the gate electrode and the interface. We experimentally demonstrate one consequence of this effect by directly imaging current distributions in gated heterostructures, finding that insulating regions nucleate at the edges of the device due to the gate. Our results suggest that device geometry and choice of dielectric materials control the charge distribution in 2D systems.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS1978

Field effect transistor and method of construction thereof

A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

Fletner, W. R.↗
NASA NTRS1993

Ultra low-noise charge coupled device

Special purpose CCD designed for ultra low-noise imaging and spectroscopy applications that require subelectron read noise floors, wherein a non-destructive output circuit operating near its 1/f noise regime is clocked in a special manner to read a single pixel multiple times. Off-chip electronics average the multiple values, reducing the random noise by the square-root of the number of samples taken. Noise floors below 0.5 electrons rms are possible in this manner. In a preferred embodiment of the invention, a three-phase CCD horizontal register is used to bring a pixel charge packet to an input gate adjacent a floating gate amplifier. The charge is then repeatedly clocked back and forth between the input gate and the floating gate. Each time the charge is injected into the potential well of the floating gate, it is sensed non-destructively. The floating gate amplifier is provided with a reference voltage of a fixed value and a pre-charge gate for resetting the amplifier between charge samples to a constant gain. After the charge is repeatedly sampled a selected number of times, it is transferred by means of output gates, back into the horizontal register, where it is clocked in a conventional manner to a diffusion MOSFET amplifier. It can then be either sampled (destructively) one more time or otherwise discarded.

Janesick, James R.↗
NASA NTRS2008

Scheme for Quantum Computing Immune to Decoherence

A constructive scheme has been devised to enable mapping of any quantum computation into a spintronic circuit in which the computation is encoded in a basis that is, in principle, immune to quantum decoherence. The scheme is implemented by an algorithm that utilizes multiple physical spins to encode each logical bit in such a way that collective errors affecting all the physical spins do not disturb the logical bit. The scheme is expected to be of use to experimenters working on spintronic implementations of quantum logic. Spintronic computing devices use quantum-mechanical spins (typically, electron spins) to encode logical bits. Bits thus encoded (denoted qubits) are potentially susceptible to errors caused by noise and decoherence. The traditional model of quantum computation is based partly on the assumption that each qubit is implemented by use of a single two-state quantum system, such as an electron or other spin-1.2 particle. It can be surprisingly difficult to achieve certain gate operations . most notably, those of arbitrary 1-qubit gates . in spintronic hardware according to this model. However, ironically, certain 2-qubit interactions (in particular, spin-spin exchange interactions) can be achieved relatively easily in spintronic hardware. Therefore, it would be fortunate if it were possible to implement any 1-qubit gate by use of a spin-spin exchange interaction. While such a direct representation is not possible, it is possible to achieve an arbitrary 1-qubit gate indirectly by means of a sequence of four spin-spin exchange interactions, which could be implemented by use of four exchange gates. Accordingly, the present scheme provides for mapping any 1-qubit gate in the logical basis into an equivalent sequence of at most four spin-spin exchange interactions in the physical (encoded) basis. The complexity of the mathematical derivation of the scheme from basic quantum principles precludes a description within this article; it must suffice to report that the derivation provides explicit constructions for finding the exchange couplings in the physical basis needed to implement any arbitrary 1-qubit gate. These constructions lead to spintronic encodings of quantum logic that are more efficient than those of a previously published scheme that utilizes a universal but fixed set of gates.

Williams, Colin↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS2005

SCB Quantum Computers Using iSWAP and 1-Qubit Rotations

Units of superconducting circuitry that exploit the concept of the single- Cooper-pair box (SCB) have been built and are undergoing testing as prototypes of logic gates that could, in principle, constitute building blocks of clocked quantum computers. These units utilize quantized charge states as the quantum information-bearing degrees of freedom. An SCB is an artificial two-level quantum system that comprises a nanoscale superconducting electrode connected to a reservoir of Cooper-pair charges via a Josephson junction. The logical quantum states of the device, .0. and .1., are implemented physically as a pair of charge-number states that differ by 2e (where e is the charge of an electron). Typically, some 109 Cooper pairs are involved. Transitions between the logical states are accomplished by tunneling of Cooper pairs through the Josephson junction. Although the two-level system contains a macroscopic number of charges, in the superconducting regime, they behave collectively, as a Bose-Einstein condensate, making possible a coherent superposition of the two logical states. This possibility makes the SCB a candidate for the physical implementation of a qubit. A set of quantum logic operations and the gates that implement them is characterized as universal if, in principle, one can form combinations of the operations in the set to implement any desired quantum computation. To be able to design a practical quantum computer, one must first specify how to decompose any valid quantum computation into a sequence of elementary 1- and 2-qubit quantum gates that are universal and that can be realized in hardware that is feasible to fabricate. Traditionally, the set of universal gates has been taken to be the set of all 1-qubit quantum gates in conjunction with the controlled-NOT (CNOT) gate, which is a 2-qubit gate. Also, it has been known for some time that the SWAP gate, which implements square root of the simple 2-qubit exchange interaction, is as computationally universal as is the CNOT operation.

Williams, Colin↗
DOE OSTI2020

Metal oxide semiconductor (MOS) controlled devices and methods of making the same

Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Metal oxide semiconductor (MOS) controlled devices and methods of making the same

Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device.The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.

Matocha, Kevin↗
DOE OSTI2024

Long‐Range Non‐Coulombic Coupling at the LaAlO 3 /SrTiO 3 Interface

The LaAlO 3 /SrTiO 3 interface hosts a plethora of gate‐tunable electronic phases. Gating of LaAlO 3 /SrTiO 3 interfaces is usually assumed to occur electrostatically. However, increasing evidence suggests that non‐local interactions can influence and, in some cases, dominate the coupling between applied gate voltages and electronic properties. Here, quasi‐1D ballistic electron waveguides are sketched at the LaAlO 3 /SrTiO 3 interface as a probe to understand how gate tunability varies as a function of spatial separation. Gate tunability measurements reveal the scaling law to be at odds with the pure electrostatic coupling observed in traditional semiconductor systems. The non‐Coulombic gating at the interface is attributed to a long‐range nanoelectromechanical coupling between the gate and electron waveguide, possibly mediated by the ferroelastic domains in SrTiO 3 . The long‐range interactions at the LaAlO 3 /SrTiO 3 interface add unexpected richness and complexity to this correlated electron system.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Multipartite Entanglement in Rabi-Driven Superconducting Qubits

The exploration of highly connected networks of qubits is invaluable for implementing various quantum algorithms and simulations, as it allows for entangling qubits with reduced circuit depth. Here, we demonstrate a multiqubit sideband tone-assisted Rabi-driven gate. Our scheme is inspired by the ion-qubit Mølmer-Sørensen gate and is mediated by a shared photonic mode and Rabi-driven superconducting qubits, which relaxes restrictions on qubit frequencies during fabrication and supports scalability. We achieve a two-qubit gate with a maximum state fidelity of 95% in 310 ns, a three-qubit gate with a state fidelity of 90.5% in 217 ns, and a four-qubit gate with a state fidelity of 66% in 200 ns. Furthermore, we develop a model of the gate that shows that the four-qubit gate is limited by shared resonator losses and the spread of qubit-resonator couplings, which must be addressed to reach high-fidelity operations.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2022

Methods and Results for Quantum Optimal Pulse Control on Superconducting Qubit Systems

The effective use of current Noisy Intermediate-Scale Quantum (NISQ) devices is often limited by the noise which is caused by interaction with the environment and affects the fidelity of quantum gates. In transmon qubit systems, the quantum gate fidelity can be improved by applying control pulses that can minimize the effects of the environmental noise. In this work, we employ physics-guided quantum optimal control strategies to design optimal pulses driving quantum gates on superconducting qubit systems. We test our results by conducting experiments on the IBM quantum hardware using their OpenPulse API. We compare the performance of our pulse-optimized quantum gates against the default quantum gates and show that the optimized pulses improve the fidelity of the quantum gates, in particular the single-qubit gates. Here we discuss the challenges we encountered in our work and point to possible future improvements.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Impact of dynamics, entanglement and Markovian noise on the fidelity of few-qubit digital quantum simulation

Quantum algorithms have been proposed to accelerate the simulation of the chaotic dynamical systems that are ubiquitous in the physics of plasmas. Quantum computers without error correction might even use noise to their advantage to calculate the Lyapunov exponent by measuring the Loschmidt echo fidelity decay rate. For the first time, digital Hamiltonian simulations of the quantum sawtooth map, performed on the IBM-Q quantum hardware platform, show that the fidelity decay rate of a digital quantum simulation increases during the transition from dynamical localization to chaotic diffusion in the map. The observed error per CNOT gate increases by $1.5{\times }$ as the dynamics varies from localized to diffusive, while only changing the phases of virtual RZ gates and keeping the overall gate count constant. A gate-based Lindblad noise model that captures the effective change in relaxation and dephasing errors during gate operation qualitatively explains the effect of dynamics on fidelity as being due to the localization and entanglement of the states created. Specifically, highly delocalized states that are entangled with random phases show an increased sensitivity to dephasing and, on average, a similar sensitivity to relaxation as localized states. In contrast, delocalized unentangled states show an increased sensitivity to dephasing but a lower sensitivity to relaxation. This gate-based Lindblad model is shown to be a useful benchmarking tool by estimating the effective Lindblad coherence times during CNOT gates and finding a consistent $2\unicode{x2013}3{\times }$ shorter $T_2$ time than reported for idle qubits. Thus, the interplay of the dynamics of a simulation with the noise processes that are active can strongly influence the overall fidelity decay rate.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2023

Benchmarking quantum logic operations relative to thresholds for fault tolerance

Contemporary methods for benchmarking noisy quantum processors typically measure average error rates or process infidelities. However, thresholds for fault-tolerant quantum error correction are given in terms of worst-case error rates—defined via the diamond norm—which can differ from average error rates by orders of magnitude. One method for resolving this discrepancy is to randomize the physical implementation of quantum gates, using techniques like randomized compiling (RC). In this work, we use gate set tomography to perform precision characterization of a set of two-qubit logic gates to study RC on a superconducting quantum processor. We find that, under RC, gate errors are accurately described by a stochastic Pauli noise model without coherent errors, and that spatially correlated coherent errors and non-Markovian errors are strongly suppressed. We further show that the average and worst-case error rates are equal for randomly compiled gates, and measure a maximum worst-case error of 0.0197(3) for our gate set. Our results show that randomized benchmarks are a viable route to both verifying that a quantum processor’s error rates are below a fault-tolerance threshold, and to bounding the failure rates of near-term algorithms, if—and only if—gates are implemented via randomization methods which tailor noise.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Toward Consistent High-Fidelity Quantum Learning on Unstable Devices via Efficient In-Situ Calibration

In the near-term noisy intermediate-scale quantum (NISQ) era, high noise will significantly reduce the fidelity of quantum computing. What's worse, recent works reveal that the noise on quantum devices is not stable, that is, the noise is dynamically changing over time. This leads to an imminent challenging problem: At run-time, is there a way to efficiently achieve a consistent high-fidelity quantum system on unstable devices? To study this problem, we take quantum learning (a.k.a., variational quantum algorithm) as a vehicle, which has a wide range of applications, such as combinatorial optimization and machine learning. A straightforward approach is to optimize a variational quantum circuit (VQC) with a parameter-shift approach on the target quantum device before using it; however, the optimization has an extremely high time cost, which is not practical at run-time. To address the pressing issue, in this paper, we proposed a novel quantum pulse-based noise adaptation framework, namely QuPAD. In the proposed framework, first, we identify that the CNOT gate is the fidelity bottleneck of the conventional VQC, and we employ a more robust parameterized multi-qubit gate (i.e., Rzx gate) to replace CNOT gate. Second, by benchmarking Rzx gate with different parameters, we build a fitting function for each coupling qubit pair, such that the deviation between the theoretic output of Rzx gate and its on-device output under a given pulse amplitude and duration can be efficiently predicted. On top of this, an evolutionary algorithm is devised to identify the pulse amplitude and duration of each Rzx gate (i.e., calibration) and find the quantum circuits with high fidelity. Experiments show that the runtime on quantum devices of QuPAD with 8–10 qubits is less than 15 minutes, which is up to 270 x faster than the parameter-shift approach. In addition, compared to the vanilla VQC as a baseline, QuPAD can achieve 59.33% accuracy gain on a classification task, and average 66.34% closer to ground state energy for molecular simulation.

Hu, Zhirui↗
DOE OSTI2026

Wind and Temperature Consensus at Horn Point, HU-Beltsville, Piney Run (Maryland) in support of CoURAGE

The Maryland Department of the Environment (MDE) operates a ground-based atmospheric profiling network consisting of collocated radar wind profilers (RWP) and radio acoustic sounding systems (RASS) as part of its Ambient Air Monitoring Program. This network provides continuous observations of wind and temperature structure in the lower troposphere to support air quality forecasting, regulatory analysis, and atmospheric research. The network currently includes three fixed sites across Maryland: Horn Point (HP, lower eastern shore) [38.587525°,-76.141006°], Howard University-Beltsville (HUB, central Maryland) [39.055277°, -76.878632°], and Piney Run (PR, western Maryland) [39.705950°, -79.012000°] The network is designed to capture regional variability in atmospheric transport and boundary-layer processes. These systems measure vertical profiles of horizontal wind speed and direction using Doppler radar techniques, with observations typically spanning from ~100 m above ground level up to approximately 2.5–4 km. Measurements are derived from the Doppler shift of backscattered electromagnetic signals, enabling retrieval of wind vectors at multiple altitudes with high temporal resolution (e.g., 30-minute averages reported every 6 minutes). Each radar wind profiler is paired with a Radio Acoustic Sounding System (RASS) to provide profiles of virtual temperature in the lower atmosphere (~100–200 m AGL) by measuring the propagation speed of acoustic waves. Together, the RWP/RASS system yields a coupled data set of thermodynamic and kinematic atmospheric structure, including additional parameters such as vertical velocity, radial velocity, signal-to-noise ratio, and spectral width for advanced analysis. There are two types of files for each station: wind data (files with a "w" prefix) and virtual temperature RASS data (files with a "t" prefix). The wind data files are in the format wYYDDD.cns, where YY is the 2-digit year and DDD is the day of the year. The RASS virtual temperature data files are in the format tYYDDD.cns. Each record has the following header structure: Line 1 : Station Name RASS files Line 2 : RASS rev DeTect_2.0, WINDS files Line 2 : WINDS rev ATI 5.1 Line 3 : N latitude, W longitude, and site elevation (m) Line 4 : Date and begin time of consensus: yy mm dd hh mn ss plus # minutes to add to get UTC Line 5 : Consensus averaging time (minutes); number of beams; number of range gates Line 6 : Number of records required to make consensus (num) total number of records (tot) and the consensus window size (m/s) in the format: num:tot (window) RASS files Line 7 : no. of coded cells, no. of spec, pulse width (ns), and inter-pulse period (µs), WINDS files Line 7 : No. of coded cells, no. of spectra, pulse width (ns), and inter-pulse period (µs), each with a pair of values: first value is for oblique beams, second for vertical RASS files Line 8 : Full scale Doppler value (m/s) Delay to first gate (ns) Number of gates Spacing of gates (ns), WINDS files Line 8 : Full scale Doppler velocity (m/s), oblique and vertical Vertical correction applied to oblique beams? (0 = no, 1 = yes) Delay to first gate (ns), oblique and vertical Number of gates, oblique and vertical Spacing of gates (ns), oblique and vertical Line 9 : Azimuth and elevation (9s indicate vertical beam not used) RASS files Line 10, values : HT = Height above ground (km), T = Uncorrected virtual temperature consensus (deg C), Tc = Corrected virtual temperature consensus (deg C), W = Vertical wind consensus (9s indicate vertical beam not used, w-component, positive upward, m/s), CNT = Number of records that made consensus (for the 3 values in same order), SNR = Average signal to noise ratio (dB) of records in consensus (same order) WINDS files Line 10, values : HT = Height above ground (km), SPD = Wind speed (m/s), DIR = Wind direction (deg E of N from N), RAD = Radial velocities for each beam (m/s) in order given in azimuth and elevation line (positive toward radar; 9s indicate vertical beam not used, CNT = Number of records that made consensus, SNR = Average signal to noise ratio (dB) of records in consensus

{"wind speed and direction",temperature}↗