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At least 955 records · Page 53

All sources NASA NTRS DOE OSTI

DOE OSTI2016

Adaptive runtime for a multiprocessing API

A computer-implemented method includes selecting a runtime for executing a program. The runtime includes a first combination of feature implementations, where each feature implementation implements a feature of an application programming interface (API). Execution of the program is monitored, and the execution uses the runtime. Monitor data is generated based on the monitoring. A second combination of feature implementations are selected, by a computer processor, where the selection is based at least in part on the monitor data. The runtime is modified by activating the second combination of feature implementations to replace the first combination of feature implementations.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2016

Adaptive runtime for a multiprocessing API

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

fftMPI, a library for performing 2d and 3d FFTs in parallel

The fftMPI library enables two and three dimensional Fast Fourier Transforms (FFTs) to be performed efficiently in parallel on a variety of platforms from desktop machines to supercomputers. It allows for flexibility in the initial distribution of the FFT grid across processors, as well as the final output. It handles the data communication and reordering necessary to perform multi-dimensional FFTs in parallel. It relies on open-source or vendor-provided libraries to perform one dimensional FFTs on a single processor. It uses MPI for inter-processor communication, which is a standard distributed memory message-passing library.

Plimpton, Steven↗

NASA NTRS2012

Lunar Reconnaissance Orbiter (LRO) Command and Data Handling Flight Electronics Subsystem

A document describes a high-performance, modular, and state-of-the-art Command and Data Handling (C&DH) system developed for use on the Lunar Reconnaissance Orbiter (LRO) mission. This system implements a complete hardware C&DH subsystem in a single chassis enclosure that includes a processor card, 48 Gbytes of solid-state recorder memory, data buses including MIL-STD-1553B, custom RS-422, SpaceWire, analog collection, switched power services, and interfaces to the Ka-Band and S-Band RF communications systems. The C&DH team capitalized on extensive experience with hardware and software with PCI bus design, SpaceWire networking, Actel FPGA design, digital flight design techniques, and the use of VxWorks for the real-time operating system. The resulting hardware architecture was implemented to meet the LRO mission requirements. The C&DH comprises an enclosure, a backplane, a low-voltage power converter, a single-board computer, a communications interface board, four data storage boards, a housekeeping and digital input/output board, and an analog data acquisition board. The interfaces between the C&DH and the instruments and avionics are connected through a SpaceWire network, a MIL-STD-1553 bus, and a combination of synchronous and asynchronous serial data transfers over RS-422 and LVDS (low-voltage differential-signaling) electrical interfaces. The C&DH acts as the spacecraft data system with an instrument data manager providing all software and internal bus scheduling, ingestion of science data, distribution of commands, and performing science operations in real time.

Nguyen, Quang↗

NASA NTRS1980

Preliminary study on the potential usefulness of array processor techniques for structural synthesis

The effects of the use of array processor techniques within the structural analyzer program, SPAR, are simulated in order to evaluate the potential analysis speedups which may result. In particular the connection of a Floating Point System AP120 processor to the PRIME computer is discussed. Measurements of execution, input/output, and data transfer times are given. Using these data estimates are made as to the relative speedups that can be executed in a more complete implementation on an array processor maxi-mini computer system.

Feeser, L. J.↗

DOE OSTI2016

CTF Preprocessor User's Manual

This document describes how a user should go about using the CTF pre- processor tool to create an input deck for modeling rod-bundle geometry in CTF. The tool was designed to generate input decks in a quick and less error-prone manner for CTF. The pre-processor is a completely independent utility, written in Fortran, that takes a reduced amount of input from the user. The information that the user must supply is basic information on bundle geometry, such as rod pitch, clad thickness, and axial location of spacer grids--the pre-processor takes this basic information and determines channel placement and connection information to be written to the input deck, which is the most time-consuming and error-prone segment of creating a deck. Creation of the model is also more intuitive, as the user can specify assembly and water-tube placement using visual maps instead of having to place them by determining channel/channel and rod/channel connections. As an example of the benefit of the pre-processor, a quarter-core model that contains 500,000 scalar-mesh cells was read into CTF from an input deck containing 200,000 lines of data. This 200,000 line input deck was produced automatically from a set of pre-processor decks that contained only 300 lines of data.

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

DOE OSTI2020

CTF User's Manual (V.4.2)

This document describes how a user should go about using the CTF pre-processor tool to create an input deck for modeling rod-bundle geometry in CTF. The tool was designed to generate input decks in a quick and less error-prone manner for CTF. The pre-processor is a completely independent utility, written in Fortran, that takes a reduced amount of input from the user. The information that the user must supply is basic information on bundle geometry, such as rod pitch, clad thickness, and axial location of spacer grids - the pre-processor takes this basic information and determines channel placement and connection information to be written to the input deck, which is the most time-consuming and error-prone segment of creating a deck. Creation of the model is also more intuitive, as the user can specify assembly and water-tube placement using visual maps instead of having to place them by determining channel/channel and rod/channel connections. As an example of the benefit of the pre-processor, a quarter-core model that contains 500,000 scalar-mesh cells was read into CTF from an input deck containing 200,000 lines of data. This 200,000 line input deck was produced automatically from a set of pre-processor decks that contained only 300 lines of data.

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

NASA NTRS1977

Conceptual design of an on-board optical processor with components

The specification of components for a spacecraft on-board optical processor was investigated. A space oriented application of optical data processing and the investigation of certain aspects of optical correlators were examined. The investigation confirmed that real-time optical processing has made significant advances over the past few years, but that there are still critical components which will require further development for use in an on-board optical processor. The devices evaluated were the coherent light valve, the readout optical modulator, the liquid crystal modulator, and the image forming light modulator.

Walsh, J. R.↗

NASA NTRS2009

Command and Service Module Communications

This viewgraph presentation examines Command and Service Module (CSM) Communications. The communication system's capabilities are defined, including CSM-Earth, CSM-Lunar Module and CSM-Extravehicular crewman communications. An overview is provided for S-band communications, including data transmission and receiving rates, operating frequencies and major system components (pre-modulation processors, unified S-band electronics, S-band power amplifier and S-band antennas). Additionally, data transmission rates, operating frequencies and the capabilities of VHF communications are described. Major VHF components, including transmitters and receivers, and the VHF multiplexer and antennas are also highlighted. Finally, communications during pre-launch, ascent, in-flight and entry are discussed. Overall, the CSM communication system was rated highly by flight controllers and crew. The system was mostly autonomous for both crew and flight controllers and no major issues were encountered during flight.

Interbartolo, Michael↗

NASA NTRS2020

NASA SpaceCube Intelligent Multi-Purpose System for Enabling Remote Sensing, Communication, and Navigation in Mission Architectures

New, innovative CubeSat mission concepts demand modern capabilities such as artificial intelligence and autonomy, constellation coordination, fault mitigation, and robotic servicing –all of which require vastly more processing resources than legacy systems are capable of providing. Enabling these domains within a scalable, configurable processing architecture is advantageous because it also allows for the flexibility to address varying mission roles, such as a command and data-handling system, a high-performance application processor extension, a guidance and navigation solution, or an instrument/sensor interface. This paper describes the NASA SpaceCube Intelligent Multi-Purpose System (IMPS), which allows mission developers to mix-and-match 1U (10 cm × 10 cm) CubeSat payloads configured for mission-specific needs. The central enabling component of the system architecture to address these concerns is the SpaceCube v3.0 Mini Processor. This single-board computer features the 20nm Xilinx Kintex UltraScale FPGA combined with a radiation-hardened FPGA monitor, and extensive IO to integrate and interconnect varying cards within the system. To unify the re-usable designs within this architecture, the CubeSat Card Standard was developed to guide design of 1U cards. This standard define spinout configurations, mechanical, and electrical specifications for 1U CubeSat cards, allowing the backplane and mechanical enclosure to be easily extended. NASA has developed several cards adhering to the standard (System-on-Chip, power card, etc.), which allows the flexibility to configure a payload from a common catalog of cards.

Advanced Avionics, Hybrid Processing, Data Process↗

NASA NTRS1985

Investigation of TM Band-to-band Registration Using the JSC Registration Processor

When the Thematic Mapper (TM) imagery was first received and displayed in the fall of 1982, its radiometric lucidity and geometric fidelity was judged far superior to the multispectral scanner (MSS) imagery. The MSS data from the LANDSAT series of satellites have served well as the mainstay of satellite imagery for the remote sensing community up to now. Therefore, there is great anticipation as to the utility of this new IM imagery to advance the field of remote sensing. The thematic mapper (TM) band to band registration accuracy evaluation was discussed. In particular, the band to band registration accuracies of the TM data in the subpixel region were evaluated using the Johnson Space Center (JSC) registration processor which is ideally suited for this task. The JSC registration processor was also used to register one acquisition to another acquisition of multitemporal TM data acquired over the same ground track. The approach and the rationale behind the task, the description of the data set, the evaluation results, and the preliminary conclusions are discussed.

Yao, S. S.↗

NASA NTRS2004

Scalable Multiprocessor for High-Speed Computing in Space

A report discusses the continuing development of a scalable multiprocessor computing system for hard real-time applications aboard a spacecraft. "Hard realtime applications" signifies applications, like real-time radar signal processing, in which the data to be processed are generated at "hundreds" of pulses per second, each pulse "requiring" millions of arithmetic operations. In these applications, the digital processors must be tightly integrated with analog instrumentation (e.g., radar equipment), and data input/output must be synchronized with analog instrumentation, controlled to within fractions of a microsecond. The scalable multiprocessor is a cluster of identical commercial-off-the-shelf generic DSP (digital-signal-processing) computers plus generic interface circuits, including analog-to-digital converters, all controlled by software. The processors are computers interconnected by high-speed serial links. Performance can be increased by adding hardware modules and correspondingly modifying the software. Work is distributed among the processors in a parallel or pipeline fashion by means of a flexible master/slave control and timing scheme. Each processor operates under its own local clock; synchronization is achieved by broadcasting master time signals to all the processors, which compute offsets between the master clock and their local clocks.

Lux, James↗

DOE OSTI2019

Low cost, hardened single board computer for command and data handling

A radiation hardened single board computer (SBC) includes a processor; static random-access memory (SRAM); non-volatile memory; a field programmable gate array (FPGA); and board-level physical layer interfaces.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1989

The influence of platform attitude dynamics on the Doppler frequency synthesis of SIR-B ocean data near Hurricane Josephine

The Space Shuttle Challenger was maneuvered into an SAR data-acquisition mode to capture a SIR-B scene of Hurricane Josephine, which presented itself as an unscheduled target of opportunity during NASA Mission 41-G during October 1984. Steeply sloped seas approaching 10 m in height were observed several hundred km in advance of the hurricane track. Mission attitude data indicate that the Shuttle pitch, roll, and yaw were unstable during the data take. The statistical clutterlock used by the ground SAR processor yields a Doppler frequency estimate that tracks the Shuttle yaw variation but is ambiguous with a single discontinuity equal to one multiple of the radar pulse repetition frequency. The SIR-B signal data have been compressed under several Doppler parameterizations to investigate the ambiguity of the clutterlock. Resultant ocean images are analyzed for their contrast and resolution properties.

Tilley, David G.↗

NASA NTRS2004

Data Relay Board with Protocol for High-Speed, Free-Space Optical Communications

In a free-space optical communication system, the mitigation of transient outages through the incorporation of error-control methods is of particular concern, the outages being caused by scintillation fades and obscurants. The focus of this innovative technology is the development of a data relay system for a reliable high-data-rate free-spacebased optical-transport network. The data relay boards will establish the link, maintain synchronous connection, group the data into frames, and provide for automatic retransmission (ARQ) of lost or erred frames. A certain Quality of Service (QoS) can then be ensured, compatible with the required data rate. The protocol to be used by the data relay system is based on the draft CCSDS standard data-link protocol Proximity-1, selected by orbiters to multiple lander assets in the Mars network, for example. In addition to providing data-link protocol capabilities for the free-space optical link and buffering the data, the data relay system will interface directly with user applications over Gigabit Ethernet and/or with highspeed storage resources via Fibre Channel. The hardware implementation is built on a network-processor-based architecture. This technology combines the power of a hardware switch capable of data switching and packet routing at Gbps rates, with the flexibility of a software- driven processor that can host highly adaptive and reconfigurable protocols used, for example, in wireless local-area networks (LANs). The system will be implemented in a modular multi-board fashion. The main hardware elements of the data relay system are the new data relay board developed by Rockwell Scientific, a COTS Gigabit Ethernet board for user interface, and a COTS Fibre Channel board that connects to local storage. The boards reside in a cPCI back plane, and can be housed in a VME-type enclosure.

Wright, Malcolm↗

NASA NTRS1989

Parallel asynchronous systems and image processing algorithms

A new hardware approach to implementation of image processing algorithms is described. The approach is based on silicon devices which would permit an independent analog processing channel to be dedicated to evey pixel. A laminar architecture consisting of a stack of planar arrays of the device would form a two-dimensional array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuronlike asynchronous pulse coded form through the laminar processor. Such systems would integrate image acquisition and image processing. Acquisition and processing would be performed concurrently as in natural vision systems. The research is aimed at implementation of algorithms, such as the intensity dependent summation algorithm and pyramid processing structures, which are motivated by the operation of natural vision systems. Implementation of natural vision algorithms would benefit from the use of neuronlike information coding and the laminar, 2-D parallel, vision system type architecture. Besides providing a neural network framework for implementation of natural vision algorithms, a 2-D parallel approach could eliminate the serial bottleneck of conventional processing systems. Conversion to serial format would occur only after raw intensity data has been substantially processed. An interesting challenge arises from the fact that the mathematical formulation of natural vision algorithms does not specify the means of implementation, so that hardware implementation poses intriguing questions involving vision science.

Coon, D. D.↗

DOE OSTI2017

Advanced Manufacturing for Thermal and Environmental Control Systems: Achieving National Energy Goals

This project was part of a regional initiative in the five counties of Central New York (CNY) that received funding from the U.S. Department of Energy (DOE) and four other federal agencies through the 2012 Advanced Manufacturing Jobs and Innovation Accelerator Challenge (AMJIAC). The CNY initiative was focused on cultivating the emergent regional cluster in “Advanced Manufacturing for Thermal and Environmental Control (AM-TEC).” As one component of the CNY AM-TEC initiative, the DOE-funded project supported five research & development seed projects that strategically targeted: 1) needs and opportunities of CNY AM-TEC companies, and 2) the goal of DOE’s Advanced Manufacturing Office (AMO) to reduce energy consumption by 50% across product life-cycles over 10 years. The project also sought to fulfill the AMO mission of developing and demonstrating new, energy-efficient processing and materials technologies at a scale adequate to prove their value to manufacturers and spur investment. The five seed projects demonstrated technologies and processes that can reduce energy intensity and improve production as well as use less energy throughout their lifecycles. The project was conducted over three years in two 18-month budget periods. During the first budget period, two projects proposed in the original AMJAIC application were successfully completed: Seed Project 1 focused on saving energy in heat transfer processes via development of nano structured surfaces to significantly increase heat flux; Seed Project 2 addressed saving energy in data centers via subzero cooling of the computing processors. Also during the first budget period, a process was developed and executed to select a second round of seed projects via a competitive request for proposals from regional companies and university collaborators. Applicants were encouraged to form industry-academic partnerships to leverage experience and resources of public and private sectors in the CNY region. Proposals were evaluated by a national panel of experts. Three projects were selected for awards and were completed successfully during the second budget period: Seed Project 3 focused on enabling self-powered furnaces to permit residents to shelter in place during power outages; Seed Project 4 addressed development of a novel method of controlling air conditioning systems that could enable flexible load matching in market segments not possible with existing technologies; and Seed Project 5 focused on the creation of smarter occupancy sensors to enable effective highly localized demand based ventilation.

30 DIRECT ENERGY CONVERSION↗

DOE OSTI2021

Vector send operation for message-based communication

Methods and systems for conducting vector send operations are provided. The processor of a sender node receives a request to perform a collective send operation (e.g., MPI_Broadcast) from a user application, requesting a copy of data in one or more send buffers by sent to each of a plurality of destinations in a destination vector. The processor invokes a vector send operation from a software communications library, placing a remote enqueue atomic send command for each destination node of the destination vector in an entry of a transmit data mover (XDM) command queue in a single call. The processor executes all of the commands in the XDM command queue and writes the data in the one or more send buffers into each receive queue of each destination identified in the destination vector.

Byrne, John L.↗