SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
A system for occluding a physical anomaly. One embodiment comprises a shape memory material body wherein the shape memory material body fits within the physical anomaly occluding the physical anomaly. The shape memory material body has a primary shape for occluding the physical anomaly and a secondary shape for being positioned in the physical anomaly.
A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.
A system for occluding a physical anomaly. One embodiment comprises a shape memory material body wherein the shape memory material body fits within the physical anomaly occluding the physical anomaly. The shape memory material body has a primary shape for occluding the physical anomaly and a secondary shape for being positioned in the physical anomaly.
A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.
MPI allows applications to treat processes as a logical collection of integer ranks for each MPI communicator, while internally translating these logical ranks into actual network addresses. In current MPI implementations the management and lookup of such network addresses use memory sizes that are proportional to the number of processes in each communicator. In this paper, we propose a new mechanism, called AV-Rankmap, for managing such translation. AV-Rankmap takes advantage of logical patterns in rank-address mapping that most applications naturally tend to have, and it exploits the fact that some parts of network address structures are naturally more performance critical than others. It uses this information to compress the memory used for network address management. We demonstrate that AV-Rankmap can achieve performance similar to or better than that of other MPI implementations while using significantly less memory.
A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.
Extremely fast pattern recognition capabilities are necessary to find and fit billions of tracks at the hardware trigger level produced every second anticipated at high luminosity LHC (HL-LHC) running conditions. Associative Memory (AM) based approaches for fast pattern recognition have been proposed as a potential solution to the tracking trigger. However, at the HL-LHC, there is much less time available and speed performance must be improved over previous systems while maintaining a comparable number of patterns. The Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project aims to achieve the target pattern density and performance goal using 3DIC technology. The first step taken in the VIPRAM work was the development of a 2D prototype (protoVIPRAM00) in which the associative memory building blocks were designed to be compatible with the 3D integration. In this paper, we present the results from extensive performance studies of the protoVIPRAM00 chip in both realistic HL-LHC and extreme conditions. Results indicate that the chip operates at the design frequency of 100 MHz with perfect correctness in realistic conditions and conclude that the building blocks are ready for 3D stacking. We also present performance boundary characterization of the chip under extreme conditions.
Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.
Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.
In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.
A memory device receives a plurality of read commands and/or write commands in parallel. The memory device transmits data corresponding to respective read commands on respective portions of a data bus and receives data corresponding to respective write commands on respective portions of the data bus. The memory device includes I/O logic to receive the plurality of read commands in parallel, to transmit the data corresponding to the respective read commands on respective portions of the data bus, and to receive the data corresponding to the respective write commands on respective portions of the data bus.
A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.
Systems, apparatuses, and methods for sorting memory pages in a multi-level heterogeneous memory architecture. The system may classify pages into a first “hot” category or a second “cold” category. The system may attempt to place the “hot” pages into the memory level(s) closest to the systems' processor cores. The system may track parameters associated with each page, with the parameters including number of accesses, types of accesses, power consumed per access, temperature, wearability, and/or other parameters. Based on these parameters, the system may generate a score for each page. Then, the system may compare the score of each page to a threshold. If the score of a given page is greater than the threshold, the given page may be designated as “hot”. If the score of the given page is less than the threshold, the given page may be designated as “cold”.
A method and apparatus for performing memory prefetching includes determining whether to initiate prefetching. Upon a determination to initiate prefetching, a first memory row is determined as a suitable prefetch candidate, and it is determined whether a particular set of one or more cachelines of the first memory row is to be prefetched.
Methods and memory circuits for altering a magnetic direction of a magnetic memory cell using picosecond electric current pulses are disclosed. One method includes directing a first electric current pulse through the magnetic memory cell that includes a ferrimagnetic material layer to heat the ferrimagnetic material layer to toggle a magnetic direction of the ferrimagnetic material layer from a first magnetic direction to a second magnetic direction.
Convolutional Neural Networks (CNN) are being actively explored for safetycritical applications such as autonomous vehicles and aerospace, where it is essential to ensure the reliability of inference results in the presence of possible memory faults. Traditional methods such as error correction codes (ECC) and Triple Modular Redundancy (TMR) are CNN-oblivious and incur substantial memory overhead and energy cost. This paper introduces in-place zero-space ECC assisted with a new training scheme weight distribution-oriented training. The new method provides the first known zero space cost memory protection for CNNs without compromising the reliability offered by traditional ECC.
A system for occluding a physical anomaly. One embodiment comprises a shape memory material body wherein the shape memory material body fits within the physical anomaly occluding the physical anomaly. The shape memory material body has a primary shape for occluding the physical anomaly and a secondary shape for being positioned in the physical anomaly.
Graph analytics has emerged as an important tool in the analysis of large scale data from diverse application domains such as social networks, cyber security and bioinformatics. Counting the number of triangles in a graph is a fundamental kernel with several applications such as detecting the community structure of a graph or in identifying important vertices in a graph. The ubiquity of massive datasets is driving the need to scale graph analytics on parallel systems. However, numerous challenges exist in efficiently parallelizing graph algorithms, especially on distributed-memory systems. Irregular memory accesses and communication patterns, low computation to communication ratios, and the need for frequent synchronization are some of the leading challenges. In this paper, we present TriC, our distributed-memory implementation of triangle counting in graphs using the Message Passing Interface (MPI), as a submission to the 2020 GraphChallenge competition. Using a set of synthetic and real-world inputs from the challenge, we demonstrate a speedup of up to 90x relative to previous work on 32 processor-cores of a NERSC Cori node. We also provide details from distributed runs with up to8192 processes along with strong scaling results. The observations presented in this work provide an understanding of the system-level bottlenecks at scale that specifically impact sparse-irregular workloads and will therefore benefit other efforts to parallelize graph algorithms.