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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 937 records · Page 52
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Controlling Infrastructure Costs: Right-Sizing the Mission Control Facility

Johnson Space Center's Mission Control Center is a space vehicle, space program agnostic facility. The current operational design is essentially identical to the original facility architecture that was developed and deployed in the mid-90's. In an effort to streamline the support costs of the mission critical facility, the Mission Operations Division (MOD) of Johnson Space Center (JSC) has sponsored an exploratory project to evaluate and inject current state-of-the-practice Information Technology (IT) tools, processes and technology into legacy operations. The general push in the IT industry has been trending towards a data-centric computer infrastructure for the past several years. Organizations facing challenges with facility operations costs are turning to creative solutions combining hardware consolidation, virtualization and remote access to meet and exceed performance, security, and availability requirements. The Operations Technology Facility (OTF) organization at the Johnson Space Center has been chartered to build and evaluate a parallel Mission Control infrastructure, replacing the existing, thick-client distributed computing model and network architecture with a data center model utilizing virtualization to provide the MCC Infrastructure as a Service. The OTF will design a replacement architecture for the Mission Control Facility, leveraging hardware consolidation through the use of blade servers, increasing utilization rates for compute platforms through virtualization while expanding connectivity options through the deployment of secure remote access. The architecture demonstrates the maturity of the technologies generally available in industry today and the ability to successfully abstract the tightly coupled relationship between thick-client software and legacy hardware into a hardware agnostic "Infrastructure as a Service" capability that can scale to meet future requirements of new space programs and spacecraft. This paper discusses the benefits and difficulties that a migration to cloud-based computing philosophies has uncovered when compared to the legacy Mission Control Center architecture. The team consists of system and software engineers with extensive experience with the MCC infrastructure and software currently used to support the International Space Station (ISS) and Space Shuttle program (SSP).

Martin, Keith↗
NASA NTRSDate not supplied

Next Steps: Laying the Groundwork for Bundle Protocol v7

Delay/Disruption Tolerant Networking (DTN) is a networking model and protocol suite that extends the terrestrial internet to the challenging communication environments of space. These environments are typically subject to frequent disruptions, which can cause delays or errors. DTN protects data transmission by wrapping data into bundles (similar to Internet Protocol packets), storing them until a connection can be established between two nodes (similar to terrestrial routers or computers), and forwarding them to their destinations. Bundle Protocol (BP) is responsible for generating those bundles and creates the transport layer of DTN, much like how Transmission Control Protocol (TCP) and User Datagram Protocol (UDP) create the transport layer of the Internet Protocol. BPv6 is the current, accepted version of the Bundle Protocol standard. However, recent missions and test implementations have revealed missing components and areas for improvement in the standard. Using lessons learned from NASA missions and gathering inspiration from the Internet Protocol, BPv7 is intended to be a more robust Bundle Protocol that improves upon its predecessor and increases the technology readiness level of the DTN architecture. The DTN Standard Interface Design team, a sub-team of the DTN Infusion Project at the Goddard Space Flight Center, worked to create a dictionary of terms for bundle components and functional decomposition of the protocol. These efforts aided in the standardization of BP interfaces, something missing from BPv6, and supported parallel network management and configuration work. This standardization will ultimately contribute to LunaNet (a lunar communications and navigation architecture that will bring networking, positioning, navigation, timing and science services to the Moon), the Solar System Internet (SSI), and expand crewed and uncrewed space exploration opportunities.

DTN↗
NASA NTRSDate not supplied

Next Steps: Laying the Groundwork for Bundle Protocol v7

Delay/Disruption Tolerant Networking (DTN) is a networking model and protocol suite that extends the terrestrial internet to the challenging communication environments of space. These environments are typically subject to frequent disruptions, which can cause delays or errors. DTN protects data transmission by wrapping data into bundles (similar to Internet Protocol packets), storing them until a connection can be established between two nodes (similar to terrestrial routers or computers), and forwarding them to their destinations. Bundle Protocol (BP) is responsible for generating those bundles and creates the transport layer of DTN, much like how Transmission Control Protocol (TCP) and User Datagram Protocol (UDP) create the transport layer of the Internet Protocol. BPv6 is the current, accepted version of the Bundle Protocol standard. However, recent missions and test implementations have revealed missing components and areas for improvement in the standard. Using lessons learned from NASA missions and gathering inspiration from the Internet Protocol, BPv7 is intended to be a more robust Bundle Protocol that improves upon its predecessor and increases the technology readiness level of the DTN architecture. The DTN Standard Interface Design team, a sub-team of the DTN Infusion Project at the Goddard Space Flight Center, worked to create a dictionary of terms for bundle components and functional decomposition of the protocol. These efforts aided in the standardization of BP interfaces, something missing from BPv6, and supported parallel network management and configuration work. This standardization will ultimately contribute to LunaNet (a lunar communications and navigation architecture that will bring networking, positioning, navigation, timing and science services to the Moon), the Solar System Internet (SSI), and expand crewed and uncrewed space exploration opportunities.

dtn↗
DOE OSTI2023

Model-parallel Fourier neural operators as learned surrogates for large-scale parametric PDEs

Fourier neural operators (FNOs) are a recently introduced neural network architecture for learning solution operators of partial differential equations (PDEs), which have been shown to perform significantly better than comparable deep learning approaches. Once trained, FNOs can achieve speed-ups of multiple orders of magnitude over conventional numerical PDE solvers. However, due to the high dimensionality of their input data and network weights, FNOs have so far only been applied to two-dimensional or small three-dimensional problems. To remove this limited problem-size barrier, we propose a model-parallel version of FNOs based on domain-decomposition of both the input data and network weights. Here, we demonstrate that our model-parallel FNO is able to predict time-varying PDE solutions of over 2.6 billion variables on Perlmutter using up to 512 A100 GPUs and show an example of training a distributed FNO on the Azure cloud for simulating multiphase CO 2 dynamics in the Earth’s subsurface.

58 GEOSCIENCES↗
DOE OSTI2024

Parallel computing for power system climate resiliency: Solving a large-scale stochastic capacity expansion problem with mpi-sppy

Here we propose a nodal stochastic generation and transmission expansion planning model that incorporates the output from high-resolution global climate models through load and generation availability scenarios. We implement our model in Pyomo and perform computational studies on a realistically-sized test case of the California electric grid in a high performance computing environment. We propose model reformulations and algorithm tuning to efficiently solve this large problem using a variant of the Progressive Hedging Algorithm. We utilize the parallelization capabilities and overall versatility of mpi-sppy, exploiting its hub-and-spoke architecture to concurrently obtain inner and outer bounds on an optimal expansion plan. Initial results show that instances with 360 representative days on a system with over 8,000 buses can be solved to within 5% of optimality in under 4 h of wall clock time, a first step towards solving a large-scale power system expansion planning problem across a wide range of climate-informed operational scenarios.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS2006

Acceleration of Stereo Correlation in Verilog

To speed up vision processing in low speed, low power devices, embedding FPGA hardware is becoming an effective way to add processing capability. FPGAs offer the ability to flexibly add parallel and/or deeply pipelined computation to embedded processors without adding significantly to the mass and power requirements of an embedded system. This paper will discuss the JPL stereo vision system, and describe how a portion of that system was accelerated by using custom FPGA hardware to process the computationally intensive portions of JPL stereo. The architecture described takes full advantage of the ability of an FPGA to use many small computation elements in parallel. This resulted in a 16 times speedup in real hardware over using a simple linear processor to compute image correlation and disparity.

machine vision↗
DOE OSTI2026

System-Level Efficiency Study of Modular DC/DC and Fuel Cell Stack Series–Parallel Configurations

This paper presents a system-level efficiency study of modular DC/DC converter and fuel cell stack configurations under series, parallel, and series–parallel connections. The investigation considers selected DC/DC converter topologies, including isolated and non-isolated architectures, boost, non-inverting buck-boost, and resonant converters, integrated with commercially available fuel cell stacks, including the Accelera FCE150, Ballard FCgen-HPS, and Toyota TFCM2. DC/DC converter modules are evaluated in modular configurations rated at 60 kW and 90 kW and two distinct output voltage ranges, specifically 580–730V and 780–930V, examining how different interconnection schemes impact overall system efficiency. The converters are evaluated under full load (100%), partial load (66%), and light load (33%) conditions, providing a comprehensive assessment of efficiency and operational characteristics across varying power demands. Approximately two-thousand efficiency data points are obtained from laboratory prototype–level component measurements and validated design evaluations across multiple converter topologies, modular configurations, voltage ranges, and load conditions, providing a robust dataset for comparative system-level efficiency analysis. The results highlight the effects of modularity and topology selection on system-level efficiency, offering a “playbook” framework for designers to select appropriate DC/DC converter arrangements and fuel cell stack connections for series, parallel, or hybrid configurations based on efficiency considerations.

DC/DC↗
NASA NTRS1992

Future directions in computing and CFD

In recent years CFD on massively parallel machines has become a reality. This paper summarizes some recent trends both in high performance computing, and in CFD using parallel machines. The long term computational requirements for accomplishing some of the large scale problems in computational aerosciences, and current hardware and architecture trends are discussed. Performance results obtained from the implementation of some CFD applications on the Connection Machine CM-2 and the Intel iPSC/860 at NASA Ames Research Center are presented. It is argued that only massively parallel machines will be able to meet these grand challenge requirements.

Bailey, F. R.↗
DOE OSTI2022

A Block-Based Triangle Counting Algorithm on Heterogeneous Environments

Triangle counting is a fundamental building block in graph algorithms. In this article, we propose a block-based triangle counting algorithm to reduce data movement during both sequential and parallel execution. Our block-based formulation makes the algorithm naturally suitable for heterogeneous architectures. The problem of partitioning the adjacency matrix of a graph is well-studied. Our task decomposition goes one step further: it partitions the set of triangles in the graph. By streaming these small tasks to compute resources, we can solve problems that do not fit on a device. We demonstrate the effectiveness of our approach by providing an implementation on a compute node with multiple sockets, cores and GPUs. The current state-of-the-art in triangle enumeration processes the Friendster graph in 2.1 seconds, not including data copy time between CPU and GPU. Using that metric, our approach is 20 percent faster. When copy times are included, our algorithm takes 3.2 seconds. This is 5.6 times faster than the fastest published CPU-only time.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

A Block-Based Triangle Counting Algorithm on Heterogeneous Environments

Triangle counting is a fundamental building block in graph algorithms. In this paper, we propose a block-based triangle counting algorithm to reduce data movement during both sequential and parallel execution. Our block-based formulation makes the algorithm naturally suitable for heterogeneous architectures. The problem of partitioning the adjacency matrix of a graph is well-studied. Our task decomposition goes one step further: it partitions the set of triangles in the graph. By streaming these small tasks to compute resources, we can solve problems that do not fit on a device. We demonstrate the effectiveness of our approach by providing an implementation on a compute node with multiple sockets, cores and GPUs. The current state-of-the-art in triangle enumeration processes the Friendster graph in 2.1 seconds, not including data copy time between CPU and GPU. Using that metric, our approach is 20 percent faster. When copy times are included, our algorithm takes 3.2 seconds. This is 5.6 times faster than the fastest published CPU-only time.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Robust Decentralized Secondary Control Scheme for Inverter-based Power Networks

Inverter-dominated microgrids are quickly becoming a key building block of future power systems. They rely on centralized controllers that can provide reliability and resiliency in extreme events. Nonetheless, communication failures due to cyber-physical attacks or natural disasters can make autonomous operation of islanded microgrids challenging. This paper examines a unified decentralized secondary control scheme that is robust to inverter clock synchronization errors and can be seamlessly applied to grid-following or grid-forming control architectures. The proposed scheme overcomes the well-known stability problem that arises from parallel operation of local integral controllers. Theoretical guarantees for stability are provided along with criteria to appropriately tune the secondary control gains to achieve good frequency regulation performance while ensuring fair power sharing. The efficacy of our approach is demonstrated through simulations on a 5-bus microgrid with four grid-forming inverters.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1987

Computer Sciences and Data Systems, volume 2

Topics addressed include: data storage; information network architecture; VHSIC technology; fiber optics; laser applications; distributed processing; spaceborne optical disk controller; massively parallel processors; and advanced digital SAR processors.

Source record↗
NASA NTRS1987

Real-time data compressor for Eos-class missions

A conceptual design for a real-time VLSI compressor capable of processing rate up to one gigabit per second is presented. This scheme is capable of providing a three-to-one distortion-free data reduction factor to both the High Resolution Imaging Spectrometer and processed SAR imaging data. The design uses a VLSI parallel/piplined architecture capable of processing at a real time rate. The design consists of a parallel array of VLSI compressor modules. Each module is built on a single customized VLSI chip using existing state-of-the-art semiconductor technology.

Lee, Jun-Ji↗
NASA NTRS1989

Force-reflective teleoperated system with shared and compliant control capabilities

The force-reflecting teleoperator breadboard is described. It is the first system among available Research and Development systems with the following combined capabilities: (1) The master input device is not a replica of the slave arm. It is a general purpose device which can be applied to the control of different robot arms through proper mathematical transformations. (2) Force reflection generated in the master hand controller is referenced to forces and moments measured by a six DOF force-moment sensor at the base of the robot hand. (3) The system permits a smooth spectrum of operations between full manual, shared manual and automatic, and full automatic (called traded) control. (4) The system can be operated with variable compliance or stiffness in force-reflecting control. Some of the key points of the system are the data handling and computing architecture, the communication method, and the handling of mathematical transformations. The architecture is a fully synchronized pipeline. The communication method achieves optimal use of a parallel communication channel between the local and remote computing nodes. A time delay box is also implemented in this communication channel permitting experiments with up to 8 sec time delay. The mathematical transformations are computed faster than 1 msec so that control at each node can be operated at 1 kHz servo rate without interpolation. This results in an overall force-reflecting loop rate of 200 Hz.

Szakaly, Z.↗
NASA NTRS1992

Projected NASA power requirements for space science and exploration missions

NASA's Office of Space Science and Applications has recently completed its long-range strategic plan which describes a number of exciting space science missions into the early 21st century. In parallel, NASA's new Office of Exploration has begun defining in more detail the architectures of the Space Exploration Initiative (SEI) for returning to the Moon and going to Mars. Both the space science missions and the SEI missions are dependent upon power sources and energy storage with strong requirements for reliability, long life, ease of assembly, autonomy, and light weight. This paper reviews the currently planned space science and SEI missions and focuses upon the power requirements with a view toward guiding technology developers and power designers.

Gary L Bennett↗
NASA NTRS1991

SPROC: A multiple-processor DSP IC

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Davis, R.↗
NASA NTRS2012

Characterization and Analysis of Triaxially Braided Polymer Composites under Static and Impact Loads

In order to design impact resistant aerospace components made of triaxially-braided polymer matrix composite materials, a need exists to have reliable impact simulation methods and a detailed understanding of the material behavior. Traditional test methods and specimen designs have yielded unrealistic material property data due to material mechanisms such as edge damage. To overcome these deficiencies, various alternative testing geometries such as notched flat coupons have been examined to alleviate difficulties observed with standard test methods. The results from the coupon level tests have been used to characterize and validate a macro level finite element-based model which can be used to simulate the mechanical and impact response of the braided composites. In the analytical model, the triaxial braid unit cell is approximated by using four parallel laminated composites, each with a different fiber layup, which roughly simulates the braid architecture. In the analysis, each of these laminated composites is modeled as a shell element. Currently, each shell element is considered to be a smeared homogeneous material. Simplified micromechanics techniques and lamination theory are used to determine the equivalent stiffness properties of each shell element, and results from the coupon level tests on the braided composite are used to back out the strength properties of each shell element. Recent improvements to the model include the incorporation of strain rate effects into the model. Simulations of ballistic impact tests have been carried out to investigate and verify the analysis approach.

Goldberg, Robert K.↗
NASA NTRS2018

Aladyn - Adaptive Neural Network Molecular Dynamics Simulation Code: Computational Materials Mini-Application

This report provides an overview and commands description of the Computational Materials mini-application, Aladyn. Aladyn is a simple molecular dynamics code written in FORTRAN 2008, which is designed to demonstrate the use of adaptive neural networks (ANNs) in atomistic simulations. The role of ANNs is to reproduce the very complex energy landscape resulting from the atomic interactions in materials with the accuracy of quantum mechanics-based energy calculations. The ANN is trained on a large set of atomic structures calculated using the density functional theory (DFT) method. The Aladyn code is being released to serve as a training testbed for students and professors in academia to explore possible optimization algorithms for parallel computing on multicore central processing unit (CPU) computers or computers utilizing many core architectures based on graphic processing units (GPUs). The effort is related to the High Performance Computing Incubator (HPCI) project at NASA Langley Research Center.

Yamakov, Vesselin I.↗