Results for “Integrated circuits” — Page 52

NASA NTRS1989

Optical detectors for GaAs MMIC integration: Technology assessment

Fiber optic links are being considered to transmit digital and analog signals in phased array antenna feed networks in space communications systems. The radiating elements in these arrays will be GaAs monolithic microwave integrated circuits (MMIC's) in numbers ranging from a few hundred to several thousand. If such optical interconnects are to be practical it appears essential that the associated components, including detectors, be monolithically integrated on the same chip as the microwave circuitry. The general issue of monolithic integration of microwave and optoelectronic components is addressed from the point of view of fabrication technology and compatibility. Particular attention is given to the fabrication technology of various types of GaAs optical detectors that are designed to operate at a wavelength of 830 nm.

Claspy, P. C.↗

NASA NTRS1989

Optical detectors for GaAs MMIC integration - Technology assessment

Fiber optic links are being considered to transmit digital and analog signals in phased array antenna feed networks in space communications systems. The radiating elements in these arrays will be GaAs monolithic microwave integrated circuits (MMIC's) in numbers ranging from a few hundred to several thousand. If such optical interconnects are to be practical it appears essential that the associated components, including detectors, be monolithically integrated on the same chip as the microwave circuitry. The general issue of monolithic integration of microwave and optoelectronic components is addressed from the point of view of fabrication technology and compatibility. Particular attention is given to the fabrication technology of various types of GaAs optical detectors that are designed to operate at a wavelength of 830 nm.

Claspy, P. C.↗

DOE OSTI2022

High-Density, Actively Multiplexed µECoG Array on Reinforced Silicone Substrate

Simultaneous interrogation of electrical signals from wide areas of the brain is vital for neuroscience research and can aid in understanding the mechanisms of brain function and treatments for neurological disorders. There emerges a demand for development of devices with highly conformal interfaces that can span large cortical regions, have sufficient spatial resolution, and chronic recording capability while keeping a small implantation footprint. In this work, we have designed 61 channel and 48 channel high-density, cortical, micro-electrocorticographic electrode arrays with 400 µm pitch on an ultra-soft but durable substrate. We have also developed a custom multiplexing integrated circuit (IC), methods for packaging the IC in a water-tight liquid crystal polymer casing, and a micro-bonding method for attaching the electronics package to the electrode array. With the integrated multiplexer, the number of external wire connections can be reduced to 16 wires, thereby diminishing the invasive footprint of the device. Both the electrode array and IC were tested in vivo in a rat model to demonstrate the ability to sense finely-localized electrophysiological signals.

Rachinskiy, Iakov↗

NASA NTRS1991

Ka-band MMIC microstrip array for high rate communications

In a recent technology assessment of alternative communication systems for the space exploration initiative (SEI), Ka-band (18 to 40 GHz) communication technology was identified to meet the mission requirements of telecommunication, navigation, and information management. Compared to the lower frequency bands, Ka-band antennas offer higher gain and broader bandwidths; thus, they are more suitable for high data rate communications. Over the years, NASA has played an important role in monolithic microwave integrated circuit (MMIC) phased array technology development, and currently, has an ongoing contract with Texas Instrument (TI) to develop a modular Ka-band MMIC microstrip subarray (NAS3-25718). The TI contract emphasizes MMIC integration technology development and stipulates using existing MMIC devices to minimize the array development cost. The objective of this paper is to present array component technologies and integration techniques used to construct the subarray modules.

Lee, R. Q.↗

NASA NTRS1991

Ka-band MMIC microstrip array for high rate communications

In a recent technology assessment of alternative communication systems for the space exploration initiative (SEI), Ka-band (18 to 40 GHz) communication technology was identified to meet the mission requirements of telecommunication, navigation, and information management. Compared to the lower frequency bands, Ka-band antennas offer higher gain and broader bandwidths; thus, they are more suitable for high data rate communications. Over the years, NASA has played an important role in monolithic microwave integrated circuit (MMIC) phased array technology development, and currently, has an ongoing contract with Texas Instrument (TI) to develop a modular Ka-band MMIC microstrip subarray (NAS3-25718). The TI contract emphasizes MMIC integration technology development and stipulates using existing MMIC devices to minimize the array development cost. The objective of this paper is to present array component technologies and integration techniques used to construct the subarray modules.

Lee, R. Q.↗

NASA NTRS2004

Digital circuits using universal logic gates

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Whitaker, Sterling R.↗

NASA NTRS2010

Update on Waveguide-Embedded Differential MMIC Amplifiers

There is an update on the subject matter of Differential InP HEMT MMIC Amplifiers Embedded in Waveguides (NPO-42857) NASA Tech Briefs, Vol. 33, No. 9 (September 2009), page 35. To recapitulate: Monolithic microwave integrated-circuit (MMIC) amplifiers of a type now being developed for operation at frequencies of hundreds of gigahertz contain InP high-electron-mobility transistors (HEMTs) in a differential configuration. The MMICs are designed integrally with, and embedded in, waveguide packages. The instant work does not mention InP HEMTs but otherwise reiterates part of the subject matter of the cited prior article, with emphasis on the following salient points: An MMIC is mounted in the electric-field plane ("E-plane") of a waveguide and includes a finline transition to each differential-amplifier stage. The differential configuration creates a virtual ground within each pair of transistor-gate fingers, eliminating the need for external radio-frequency grounding. This work concludes by describing a single-stage differential submillimeter-wave amplifier packaged in a rectangular waveguide and summarizing results of tests of this amplifier at frequencies of 220 and 305 GHz.

Kangaslahti, Pekka↗

DOE OSTI2023

The New Small Wheel electronics

The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that don't originate from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the “small” Thin Gap Chambers, with a total of 2.45 million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm 2 at the expected HL-LHC luminosity of $\mathcal{L}$= 7.5 × 10 34 cm -2 s -1 . The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.

47 OTHER INSTRUMENTATION↗

NASA NTRS2009

Waveguide Transition for Submillimeter-Wave MMICs

An integrated waveguide-to-MMIC (monolithic microwave integrated circuit) chip operating in the 300-GHz range is designed to operate well on high-permittivity semiconductor substrates typical for an MMIC amplifier, and allows a wider MMIC substrate to be used, enabling integration with larger MMICs (power amplifiers). The waveguide-to- CBCPW (conductor-backed coplanar waveguide) transition topology is based on an integrated dipole placed in the E-plane of the waveguide module. It demonstrates low loss and good impedance matching. Measurement and simulation demonstrate that the loss of the transition and waveguide loss is less than 1-dB over a 340-to-380-GHz bandwidth. A transition is inserted along the propagation direction of the waveguide. This transition uses a planar dipole aligned with the maximum E-field of the TE10 waveguide mode as an inter face between the waveguide and the MMIC. Mode conversion between the coplanar striplines (CPS) that feed the dipole and the CBCPW transmission line is accomplished using a simple air-bridge structure. The bottom side ground plane is truncated at the same reference as the top-side ground plane, leaving the end of the MMIC suspended in air.

Leong, Kevin M.↗

DOE OSTI2026

Advancements in NbTiN based circuits for Superconducting Digital Logic

Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. This work, centered on NbTiN, presents recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. We specifically report on fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.

Pokhrel, A. [Imec,Heverlee,Belgium]↗

NASA NTRS1991

Interface Circuit For Printer Port

Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

Tucker, Jerry H.↗

NASA NTRS2008

HEMT Amplifiers and Equipment for their On-Wafer Testing

Power amplifiers comprising InP-based high-electron-mobility transistors (HEMTs) in coplanar-waveguide (CPW) circuits designed for operation at frequencies of hundreds of gigahertz, and a test set for onwafer measurement of their power levels have been developed. These amplifiers utilize an advanced 35-nm HEMT monolithic microwave integrated-circuit (MMIC) technology and have potential utility as local-oscillator drivers and power sources in future submillimeter-wavelength heterodyne receivers and imaging systems. The test set can reduce development time by enabling rapid output power characterization, not only of these and similar amplifiers, but also of other coplanar-waveguide power circuits, without the necessity of packaging the circuits.

Fung, King man↗

DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗

DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗

NASA NTRS1995

Integrated Cryogenic Satellite Communications Cross-Link Receiver Experiment

An experiment has been devised which will validate, in space, a miniature, high-performance receiver. The receiver blends three complementary technologies; high temperature superconductivity (HTS), pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuits (MMIC), and a miniature pulse tube cryogenic cooler. Specifically, an HTS band pass filter, InP MMIC low noise amplifier, HTS-sapphire resonator stabilized local oscillator (LO), and a miniature pulse tube cooler will be integrated into a complete 20 GHz receiver downconverter. This cooled downconverter will be interfaced with customized signal processing electronics and integrated onto the space shuttle's 'HitchHiker' carrier. A pseudorandom data sequence will be transmitted to the receiver, which is in low Earth orbit (LEO), via the Advanced Communication Technology Satellite (ACTS) on a 20 GHz carrier. The modulation format is QPSK and the data rate is 2.048 Mbps. The bit error rate (BER) will be measured in situ. The receiver is also equipped with a radiometer mode so that experiment success is not totally contingent upon the BER measurement. In this mode, the receiver uses the Earth and deep space as a hot and cold calibration source, respectively. The experiment closely simulates an actual cross-link scenario. Since the receiver performance depends on channel conditions, its true characteristics would be masked in a terrestrial measurement by atmospheric absorption and background radiation. Furthermore, the receiver's performance depends on its physical temperature, which is a sensitive function of platform environment, thermal design, and cryocooler performance. This empirical data is important for building confidence in the technology.

Romanofsky, R. R.↗

NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗

NASA NTRS2004

Silicon-Germanium Films Grown on Sapphire for Ka-Band Communications Applications

NASA's vision in the space communications area is to develop a broadband data network in which there is a high degree of interconnectivity among the various satellite systems, ground stations, and wired systems. To accomplish this goal, we will need complex electronic circuits integrating analog and digital data handling at the Ka-band (26 to 40 GHz). The purpose of this project is to show the feasibility of a new technology for Ka-band communications applications, namely silicon germanium (SiGe) on sapphire. This new technology will have several advantages in comparison to the existing silicon-substrate- based circuits. The main advantages are extremely low parasitic reactances that enable much higher quality active and passive components, better device isolation, higher radiation tolerance, and the integration of digital and analog circuitry on a single chip.

Alterovitz, Samuel A.↗

NASA NTRS1983

Monolithic lead salt-silicon focal plane development

This paper is a summary of work done in the development of monolithic lead salt-silicon infrared focal plane technology. The photoconductive detector materials, PbS and PbSe are chemically deposited onto premetallized silicon MOSFET integrated circuit wafers. A variety of structures based on an implanted PMOS process were fabricated and evaluated. Operational results of an eight-element PbS array multiplexed on-chip are presented along with radiometric measurements on other integrated PbS-silicon MOSFET structures. PbS imagery is shown using one element of a 20-element array integrated on-chip.

Barrett, J. R.↗