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At least 937 records · Page 52
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Computational Nanoelectronics and Nanotechnology at NASA ARC

Both physical and economic considerations indicate that the scaling era of CMOS will run out of steam around the year 2010. However, physical laws also indicate that it is possible to compute at a rate of a billion times present speeds with the expenditure of only one Watt of electrical power. NASA has long-term needs where ultra-small semiconductor devices are needed for critical applications: high performance, low power, compact computers for intelligent autonomous vehicles and Petaflop computing technology are some key examples. To advance the design, development, and production of future generation micro- and nano-devices, IT Modeling and Simulation Group has been started at NASA Ames with a goal to develop an integrated simulation environment that addresses problems related to nanoelectronics and molecular nanotechnology. Overview of nanoelectronics and nanotechnology research activities being carried out at Ames Research Center will be presented. We will also present the vision and the research objectives of the IT Modeling and Simulation Group including the applications of nanoelectronic based devices relevant to NASA missions.

Saini, Subhash↗
NASA NTRS2002

Specification and Design of the SBRC-190: A Cryogenic Multiplexer for Far Infrared Photoconductor Detectors

Arrays of far-infrared photoconductor detectors operate at a few degrees Kelvin and require electronic amplifiers in close proximity. For the electronics, a cryogenic multiplexer is ideal to avoid the large number of wires associated with individual amplifiers for each pixel, and to avoid adverse effects of thermal and radiative heat loads from the circuitry. For low background applications, the 32 channel CRC 696 CMOS device was previously developed for SIRTF, the cryogenic Space Infrared Telescope Facility. For higher background applications, we have developed a similar circuit, featuring several modifications: (a) an AC coupled, capacitive feedback transimpedence unit cell, to minimize input offset effects, thereby enabling low detector biases, (b) selectable feedback capacitors to enable operation over a wide range of backgrounds, and (c) clamp and sample & hold output circuits to improve sampling efficiency, which is a concern at the high readout rates required. We describe the requirements for and design of the new device.

Erickson, E. F.↗
NASA NTRS2002

Battling Brittle Bones

The accuDEXA(R) Bone Mineral Density Assessment System, manufactured by Schick Technologies, Inc., utilizes "camera on a chip" sensor technology invented and developed by NASA's Jet Propulsion Laboratory. Schick's accuDEXA system offers several advantages over traditional osteoporosis tests, which assess bone density loss in the hip and spine, and require specialized personnel to conduct. With accuDEXA, physicians can test the entire body's bone density at a peripheral site, such as the finger, without applying gels or having patients remove garments. Results are achieved in 30 seconds and printed out in less than a minute, compared to the estimated exam time of 15 minutes for hip and spine density analyses. Schick has also applied the CMOS APS technology to a new software product that performs dental radiography using up to 90 percent less radiation exposure than conventional X-rays. Called Computed Dental Radiography(R), the new digital imaging product utilizes an electronic sensor in place of X-ray film to generate sharp and clear images that appear on a computer screen within 3 seconds, and can be enlarged and enhanced to identify problems.

Source record↗
NASA NTRS2002

Heavy Ion Transient Characterization of a Photobit Hardened-by-Design Active Pixel Sensor Array

This paper presents heavy ion data on the single event transient (SET) response of a Photobit active pixel sensor (APS) four quadrant test chip with different radiation tolerant designs in a standard 0.35 micron CMOS process. The physical design techniques of enclosed geometry and P-channel guard rings are used to design the four N-type active photodiode pixels as described in a previous paper. Argon transient measurements on the 256 x 256 chip array as a function of incident angle show a significant variation in the amount of charge collected as well as the charge spreading dependent on the pixel type. The results are correlated with processing and design information provided by Photobit. In addition, there is a large degree of statistical variability between individual ion strikes. No latch-up is observed up to an LET of 106 MeV/mg/sq cm.

Marshall, Paul W.↗
NASA NTRS2003

Total Ionizing Dose Effects in MOS Oxides and Devices

The development of military and space electronics technology has traditionally been heavily influenced by the commercial semiconductor industry. The development of MOS technology, and particularly CMOS technology, as dominant commercial technologies has occurred entirely within the lifetime of the NSREC. For this reason, it is not surprising that the study of radiation interactions with MOS materials, devices and circuits has been a major theme of this conference for most of its history. The basic radiation problem in a MOS transistor is illustrated. The application of an appropriate gate voltage causes a conducting channel to form between the source and drain, so that current flows when the device is turned on. In Fig. lb, the effect of ionizing radiation is illustrated. Radiation-induced trapped charge has built up in the gate oxide, which causes a shift in the threshold voltage (that is, a change in the voltage which must be applied to turn the device on). If this shift is large enough, the device cannot be turned off, even at zero volts applied, and the device is said to have failed by going depletion mode.

Oldham, Timothy R.↗
NASA NTRS2001

Coupling between Microstrip Lines Embedded in Polyimide Layers for 3D-MMICs on Si

Three-dimensional circuits built upon multiple layers of polyimide are required for constructing SilSiGe monolithic microwavdmillimeter-wave integrated circuits on CMOS (low resistivity) Si wafers. However, the closely spaced transmission lines are susceptible to high levels of coupling, which degrades circuit performance. In this paper, Finite Difference Time Domain (FDTD) analysis and measured characteristics of novel shielding structures that significantly reduce coupling between embedded microstrip lines are presented. A discussion of the electric and magnetic field distributions for the coupled microstrip lines is presented to provide a physical rationale for the presented results.

Ponchak, George E.↗
NASA NTRS2003

Coupling Between Microstrip Lines With Finite Width Ground Plane Embedded in Thin Film Circuits

Three-dimensional (3D) interconnects built upon multiple layers of polyimide are required for constructing 3D circuits on CMOS (low resistivity) Si wafers, GaAs, and ceramic substrates. Thin film microstrip lines (TFMS) with finite width ground planes embedded in the polyimide are often used. However, the closely spaced TFMS lines a r e susceptible to high levels of coupling, which degrades circuit performance. In this paper, Finite Difference Time Domain (FDTD) analysis and experimental measurements a r e used to show that the ground planes must be connected by via holes to reduce coupling in both the forward and backward directions. Furthermore, it is shown that coupled microstrip lines establish a slotline type mode between the two ground planes and a dielectric waveguide type mode, and that the via holes recommended here eliminate these two modes.

Ponchak, George E.↗
NASA NTRS2003

Development of UItra-Low Temperature Motor Controllers: Ultra Low Temperatures Evaluation and Characterization of Semiconductor Technologies For The Next Generation Space Telescope

Electronics designed for low temperature operation will result in more efficient systems than room temperature. This improvement is a result of better electronic, electrical, and thermal properties of materials at low temperatures. In particular, the performance of certain semiconductor devices improves with decreasing temperature down to ultra-low temperature (-273 'C). The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical components and systems suitable for applications in deep space missions. Research is being conducted on devices and systems for use down to liquid helium temperatures (-273 'C). Some of the components that are being characterized include semiconductor switching devices, resistors, magnetics, and capacitors. The work performed this summer has focused on the evaluation of silicon-, silicon-germanium- and gallium-Arsenide-based (GaAs) bipolar, MOS and CMOS discrete components and integrated circuits (ICs), from room temperature (23 'C) down to ultra low temperatures (-263 'C).

Elbuluk, Malik E.↗
NASA NTRS2003

Carrier Plus: A sensor payload for Living With a Star Space Environment Testbed (LWS/SET)

The Defense Threat Reduction Agency (DTR4) and National Aeronautics and Space Administration (NASA) Goddard Space Flight Center are collaborating to develop the Carrier Plus sensor experiment platform as a capability of the Space Environments Testbed (SET). The Space Environment Testbed (SET) provides flight opportunities for technology experiments as part of NASA's Living With a Star (LWS) program. The Carrier Plus will provide new capability to characterize sensor technologies such as state-of-the-art visible focal plane arrays (FPAs) in a natural space radiation environment. The technical objectives include on-orbit validation of recently developed FPA technologies and performance prediction methodologies, as well as characterization of the FPA radiation response to total ionizing dose damage, displacement damage and transients. It is expected that the sensor experiment will carry 4-6 FPAs and associated radiation correlative environment monitors (CEMs) for a 2006-2007 launch. Sensor technology candidates may include n- and p-charge coupled devices (CCDs), active pixel sensors (APS), and hybrid CMOS arrays. The presentation will describe the Carrier Plus goals and objectives, as well as provide details about the architecture and design. More information on the LWS program can be found at http://lws.gsfc.nasa.gov/. Business announcements for LWS/SET and program briefings are posted at http://lws-set.gsfc.nasa.gov

Marshall, Cheryl J.↗
NASA NTRS1999

Assessment of Selected CERES Electronic Component Survivability under Simulated Overvoltage Conditions

In August, 1998 a Clouds and the Earth's Radiant Energy System (CERES) instrument telemetry housekeeping parameter generated a yellow warning message that indicated an on-board + 15V Data Acquisition Assembly (DAA) power converter deregulation anomaly. An exhaustive investigation was undertaken to understand this anomaly and the long-term consequences which have severely reduced CERES operations on the Tropical Rainfall Measuring Mission (TRMM) spacecraft. Among investigations performed were ground tests that approximated the on-board electronic circuitry using a small quantity of flight identical components exposed to maximum spacecraft bus over-voltage conditions. These components include monolithic integrated microcircuits that perform analog signal conditioning on instrument sensor signals and an analog- to-digital converter (ADC) for the entire DAA. All microcircuit packages have either a bipolar silicon design with internal current limiting protections or have a complementary metal oxide semiconductor (CMOS) design with bias protections. Ground tests that have been running for approximately 8 months have indicated that these components are capable of withstanding as much as twice their input supply voltage ratings without noticeable performance degradation. These data provide CERES operators with confidence of being able to continue science operations over the remaining life of the TRMM mission. This paper will discuss this anomaly and some possible causes, a simulator of affected electronics, test results, prognosis for future CERES operations, and conclusions.

Chapman, John J.↗
NASA NTRS2002

A comparison of imaging methods for use in an array biosensor

An array biosensor has been developed which uses an actively-cooled, charge-coupled device (CCD) imager. In an effort to save money and space, a complementary metal-oxide semiconductor (CMOS) camera and photodiode were tested as replacements for the cooled CCD imager. Different concentrations of CY5 fluorescent dye in glycerol were imaged using the three different detection systems with the same imaging optics. Signal discrimination above noise was compared for each of the three systems.

Evaluation Studies↗
NASA NTRS2004

Curvature-Based Wavefront Sensor for Use on Extended, Arbitrary, Low-Contract Scenes Final Technical Report August 2004

A small amount of work has been done on this project; the strategy to be adopted has been better defined, though no experimental work has been started. 1) Wavefront error signals: The best choice appears use a lenslet array at a pupil image to produce defocused image pairs for each subaperture. Then use the method proposed by Molodij et al. to produce subaperture curvature signals. Basically, this method samples a moderate number of locations in the image where the value of the image Laplacian is high, then taking the curvature signal from the difference of the Laplacians of the extrafocal images at those locations. The tip-tilt error is obtained from the temporal dependence of the first spatial derivatives of an in-focus image, at selected locations where these derivatives are significant. The wavefront tilt can be obtained from the full-aperture image. 2) Extrafocal image generation: The important aspect here is to generate symmetrically defocused images, with dynamically adjustable defocus. The adjustment is needed because larger defocus is required before the feedback loop is closed, and at times when the seeing is worse. It may be that the usual membrane mirror is the best choice, though other options should be explored. 3) Detector: Since the proposed sensor is to work on solar granulation, rather than a point source, an array detector for each subaperture is required. A fast CMOS camera such as that developed by the National Solar Observatory would be a satisfactory choice. 4) Processing: Processing requirements have not been defined in detail, though significantly fewer operations per cycle are required than for a correlation tracker.

LaBonte, Barry J.↗
NASA NTRS2004

Smart Camera Technology Increases Quality

When it comes to real-time image processing, everyone is an expert. People begin processing images at birth and rapidly learn to control their responses through the real-time processing of the human visual system. The human eye captures an enormous amount of information in the form of light images. In order to keep the brain from becoming overloaded with all the data, portions of an image are processed at a higher resolution than others, such as a traffic light changing colors. changing colors. In the same manner, image processing products strive to extract the information stored in light in the most efficient way possible. Digital cameras available today capture millions of pixels worth of information from incident light. However, at frame rates more than a few per second, existing digital interfaces are overwhelmed. All the user can do is store several frames to memory until that memory is full and then subsequent information is lost. New technology pairs existing digital interface technology with an off-the-shelf complementary metal oxide semiconductor (CMOS) imager to provide more than 500 frames per second of specialty image processing. The result is a cost-effective detection system unlike any other.

Source record↗
NASA NTRS2004

The Space Technology 5 Avionics System

The Space Technology 5 (ST5) mission is a NASA New Millennium Program project that will validate new technologies for future space science missions and demonstrate the feasibility of building launching and operating multiple, miniature spacecraft that can collect research-quality in-situ science measurements. The three satellites in the ST5 constellation will be launched into a sun-synchronous Earth orbit in early 2006. ST5 fits into the 25-kilogram and 24-watt class of very small but fully capable spacecraft. The new technologies and design concepts for a compact power and command and data handling (C&DH) avionics system are presented. The 2-card ST5 avionics design incorporates new technology components while being tightly constrained in mass, power and volume. In order to hold down the mass and volume, and quali& new technologies for fUture use in space, high efficiency triple-junction solar cells and a lithium-ion battery were baselined into the power system design. The flight computer is co-located with the power system electronics in an integral spacecraft structural enclosure called the card cage assembly. The flight computer has a full set of uplink, downlink and solid-state recording capabilities, and it implements a new CMOS Ultra-Low Power Radiation Tolerant logic technology. There were a number of challenges imposed by the ST5 mission. Specifically, designing a micro-sat class spacecraft demanded that minimizing mass, volume and power dissipation would drive the overall design. The result is a very streamlined approach, while striving to maintain a high level of capability, The mission's radiation requirements, along with the low voltage DC power distribution, limited the selection of analog parts that can operate within these constraints. The challenge of qualifying new technology components for the space environment within a short development schedule was another hurdle. The mission requirements also demanded magnetic cleanliness in order to reduce the effect of stray (spacecraft-generated) magnetic fields on the science-grade magnetometer.

Speer, Dave↗
NASA NTRS2004

Space Electronics: A Challenging World for Designers

This viewgraph presentation provides an overview of: 1) The Space Radiation Environment; 2) The Effects on Electronics; 3) The Environment in Action; 4) Hardening Approaches to Commercial CMOS Electronics (including device vulnerabilities).

Poivey, Christian↗
NASA NTRS2002

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Ponchak, George E.↗
NASA NTRS2005

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Phillips, Thomas A.↗