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At least 919 records · Page 51

Online assessment of a distributed processor

ORT (Operational Readiness Test) software allows one engineer to test readiness of 64 minicomputers and their peripherals from single console. Software makes roll call of computers and peripherals via common data buffer to check readiness of system in morning "wake up" or at other important times. Subsystems are tested in parallel to save time. "Watchdog" terminates test of any system that does not respond in time, so one failed system does not halt test sequence. Entire rollcall is complete in about 15 minutes. Software is designed for Space Shuttle prelaunch checkout, but approach should interest users of similar equipment.

Ehrlich, L. F.↗

MBASIC processor

MBASIC is high-level, interactive computer language that reduces time of computer task programming. Outstanding features of MBASIC include: multiple assignments or statements in single instruction; conditional, assignment, and repetitive statement modifiers; and excellent string-handling capabilities. Two machine versions are available: UNIVAC (written in reentrant Assembler code for execution under EXEC 8) AND DEC-10 (written in Assembler code for execution under TOPS-10).

Hartley, R. B.↗

Cartography: LACIE's spatial processor

The spatial processing needs of LACIE include the location of agricultural test sites, and the registration of ground truth to LANDSAT imagery. The technological aspects of LACIE cartographic support, the need for cartography in satellite crop surveys, and proposed improvements which would enhance support of future programs are discussed.

Rader, M. L.↗

Orbit attitude processor. STS-1 bench program verification test plan

A plan for the static verification of the STS-1 ATT PROC ORBIT software requirements is presented. The orbit version of the SAPIENS bench program is used to generate the verification data. A brief discussion of the simulation software and flight software modules is presented along with a description of the test cases.

Mcclain, C. R.↗

Correlator computer interface and module implementation: Mark 3 processor

Two hardware aspects of the Mark 3 correlator are briefly described. The first area concerns the choice of interface to the controlling minicomputer and the second area concerns the implementation of the correlator module. Multiple computer automated measurement and control (CAMAC) modules and a single large CAMAC module were considered as possible packaging forms for the correlator. The large CAMAC module approach was chosen because of the difficulty in partitioning the correlator with minimum interconnections, the fabrication economy of a single large planar assembly, and the desire to minimize the number of modules.

Nesman, E. F.↗

Concerning the feasibility of a real time SAR digital processor for VOIR low resolution imaging modes

The feasibility of real time digital processing of synthetic aperture radar data for Venus orbiting imaging radar low resolution modes was investigated. First, it is shown that range migration is not a problem for these modes. Then, under the assumption of no range migration, fast Fourier transform implementations for accomplishing both range and azimuth correlation in real time are shown to be feasible with current technology.

Truong, T. K.↗

Real-time operating system for selected Intel processors

The rationale for system development is given along with reasons for not using vendor supplied operating systems. Although many system design and performance goals were dictated by problems with vendor supplied systems, other goals surfaced as a result of a design for a custom system able to span multiple projects. System development and management problems and areas that required redesign or major code changes for system implementation are examined as well as the relative successes of the initial projects. A generic description of the actual project is provided and the ongoing support requirements and future plans are discussed.

Pool, W. R.↗

Microcomputer array processor system

The microcomputer array system is discussed with specific attention given to its electronic warware applications. Several aspects of the system architecture are described as well as some of its distinctive characteristics.

Slezak, K. D.↗