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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 919 records · Page 51
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Galileo spacecraft power management and distribution system

The Galileo PMAD (power management and distribution system) is described, and the design drivers that established the final as-built hardware are discussed. The spacecraft is powered by two general-purpose heat-source-radioisotope thermoelectric generators. Power bus regulation is provided by a shunt regulator. Galileo PMAD distributes a 570-W beginning of mission (BOM) power source to a user complement of some 137 load elements. Extensive use of pyrotechnics requires two pyro switching subassemblies. They initiate 148 squibs which operate the 47 pyro devices on the spacecraft. Detection and correction of faults in the Galileo PMAD is an autonomous feature dictated by requirements for long life and reliability in the absence of ground-based support. Volatile computer memories in the spacecraft command and data system and attitude control system require a continuous source of backup power during all anticipated power bus fault scenarios. Power for the Jupiter Probe is conditioned, isolated, and controlled by a Probe interface subassembly. Flight performance of the spacecraft and the PMAD has been successful to date, with no major anomalies.

Detwiler, R. C.↗
DOE OSTI2023

Proxy Applications for Converged Workloads: DMC LDRD Initiative

Modern scientific applications are complicated and require coordination of several components. Proxy application driven software-hardware co-design plays a vital role in driving innovation among the developments of applications, software infrastructure and hardware architecture. Proxy applications are self-contained and simplified codes that are intended to model the performance-critical computations within applications. Applications executing on modern High Performance Computing (HPC) systems are susceptible to network congestion, insufficient memory bandwidth within and across compute nodes, and inadvertent loss of performance due to bugs and unoptimized programming models. Modern numerical simulations and machine learning models play a critical role in studying physical phenomenon under myriad uncertainties. Such applications often exhibit irregular computation and memory accesses at specific regions of the application code, which can contribute to various performance bottlenecks at scale. To mitigate such issues and prepare the next generation hardware for a variety of computation and data movement contingencies, a well-known practice is to consider "proxy" applications as representative motifs for various classes of scientific applications. While there is disagreement in the HPC community on the mechanisms of construction of the proxy applications, there is a strong consensus on their positive impact in co-design. Proxy Applications for Converged Workloads (PACER) is about facilitating software-hardware co-design through proxy applications with the goal of improving the performance of converged science workflows on heterogeneous systems.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1992

Memory Network For Distributed Data Processors

Universal Memory Network (UMN) is modular, digital data-communication system enabling computers with differing bus architectures to share 32-bit-wide data between locations up to 3 km apart with less than one millisecond of latency. Makes it possible to design sophisticated real-time and near-real-time data-processing systems without data-transfer "bottlenecks". This enterprise network permits transmission of volume of data equivalent to an encyclopedia each second. Facilities benefiting from Universal Memory Network include telemetry stations, simulation facilities, power-plants, and large laboratories or any facility sharing very large volumes of data. Main hub of UMN is reflection center including smaller hubs called Shared Memory Interfaces.

Bolen, David↗
NASA NTRS1991

Content addressable memory project

The progress on the Rutgers CAM (Content Addressable Memory) Project is described. The overall design of the system is completed at the architectural level and described. The machine is composed of two kinds of cells: (1) the CAM cells which include both memory and processor, and support local processing within each cell; and (2) the tree cells, which have smaller instruction set, and provide global processing over the CAM cells. A parameterized design of the basic CAM cell is completed. Progress was made on the final specification of the CPS. The machine architecture was driven by the design of algorithms whose requirements are reflected in the resulted instruction set(s). A few of these algorithms are described.

Hall, Josh↗
DOE OSTI2023

Optimizing Data Movement for GPU-Based In-Situ Workflow Using GPUDirect RDMA

The extreme-scale computing landscape is increasingly dominated by GPU-accelerated systems. At the same time, in-situ workflows that employ memory-to-memory inter-application data exchanges have emerged as an effective approach for leveraging these extreme-scale systems. In the case of GPUs, GPUDirect RDMA enables third-party devices, such as network interface cards, to access GPU memory directly and has been adopted for intra-application communications across GPUs. In this paper, we present an interoperable framework for GPU-based in-situ workflows that optimizes data movement using GPUDirect RDMA. Specifically, we analyze the characteristics of the possible data movement pathways between GPUs from an in-situ workflow perspective, and design a strategy that maximizes throughput. Furthermore, we implement this approach as an extension of the DataSpaces data staging service, and experimentally evaluate its performance and scalability on a current leadership GPU cluster. The performance results show that the proposed design reduces data-movement time by up to 53% and 40% for the sender and receiver, respectively, and maintains excellent scalability for up to 256 GPUs.

Zhang, Bo↗
NASA NTRS1985

Low-Voltage Protection For Volatile Computer Memories

Short-circuit current provides minimum memory power. Protective circuit includes dc-to-dc converter that supplies keep-alive voltage to memories when short circuit occurs in any of system loads. Converter powered by lowvoltage across two of three series diodes generated by short-circuit bus current. Relay switch is in open (short-circuit-detected) position. Protective circuit useful wherever necessary to improve reliability of volatile memories or other circuits that must not lose power.

Detwiler, R. C.↗
DOE OSTI2024

ASGarD: Adaptive Sparse Grid Discretization

Many areas of science exhibit physical processes that are described by high dimensional partial differential equations (PDEs), e.g., the 4D, 5D and 6D models describing magnetized fusion plasmas, models describing quantum chemistry, or derivatives pricing. Such problems are affected by the so-called “curse of dimensionality” where the number of degrees of freedom (or unknowns) required to be solved for scales as N D where N is the number of grid points in any given dimension D. A simple, albeit naive, 6D example is demonstrated in the left panel of Figure 1. With N = 1000 grid points in each dimension, the memory required just to store the solution vector, not to mention forming the matrix required to advance such a system in time, would exceed an exabyte - and also the available memory on the largest of supercomputers available today. The right panel of Figure 1 demonstrates potential savings for a range of problem dimensionalities and grid resolution. While there are methods to simulate such high-dimensional systems, they are mostly based on Monte-Carlo methods, which rely on a statistical sampling such that the resulting solutions include noise. Since the noise in such methods can only be reduced at a rate proportional to $\sqrt{N_p}$ where N p is the number of Monte-Carlo samples, there is a need for continuum, or grid/mesh-based methods for high-dimensional problems, which both do not suffer from noise and bypass the curse of dimensionality. We present a simulation framework that provides such a method using adaptive sparse grids.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1986

CSTAR star catalogue development

The Continuous Stellar Tracking Attitude Reference (CSTAR) system is an in-house project for the Space Station to provide high accuracy, drift free attitude and angular rate information for the GN&C system. Constraints exist on the star catalogue incorporated in the system. These constraints include the following: mass memory allocated for catalogue storage, star tracker imaging sensitivity, the minimum resolvable separation angle between stars, the width of the field of view of the star tracker, and the desired number of stars to be tracked in a field of view. The Smithsonian Astrophysical Observatory (SAO) catalogue is the basis reference for this study. As it stands, the SAO does not meet the requirements of any of the above constraints. Star selection algorithms have been devised for catalogue optimization. Star distribution statistics have been obtained to aid in the development of these rules. VAX based software has been developed to implement the star selection algorithms. The software is modular and provides a design tool to tailor the catalogue to available star tracker technology. The SAO catalogue has been optimized for the requirements of the present CSTAR system.

Uhde-Lacovara, J. A.↗
NASA NTRS1987

Central Processor Acts as High-Speed DMA Controller

Computer-system architecture enables system host central processor (CP) to make high-speed, direct-memory-access (DMA) data transfers without cost and complexity of adding dedicated DMA controller. New system, CCP used as DMA controller, obviating need for dedicated DMA controller; yet maximum transfer rates equivalent to those obtained with dedicated DMA controller. Useful wherever dedicated DMA controller desired because of required data-transfer rates.

Blaha, Matthew S.↗
NASA NTRS1981

Technology and future ground processing systems

Land-observing satellites with multiple thematic mappers will produce data at rates of 100 to 300 Mbps. When coupled with a high daily scene production rate, these rates will require new approaches to ground processing. Consideration is given here to future downlink rates and data volumes, and requirements peculiar to the future user community are discussed. The advanced technologies required to attain an operational system in the years 1985-1990 are considered, together with advances foreseen in communications, mass storage, bulk memories, and data processing. Using advanced devices, a centralized data processing system capable of handling the 100 Mbps data rate is described. New approaches, among them a parallel pipelined calibration front-end, real-time browse image production, a high bandwidth optical disk archive, regional image broadcast and massively parallel product production, are considered. A distributed system capable of handling the 300 Mbps data rate is then described. Designs for a hub system and a regional processing center are presented.

Wood, B. J.↗
DOE OSTI2021

Asynchronous distributed-memory task-parallel algorithm for compressible flows on unstructured 3D Eulerian grids

Here, we discuss the implementation of a finite element method, used to numerically solve the Euler equations of compressible flows, using an asynchronous runtime system (RTS). The algorithm is implemented for distributed-memory machines, using stationary unstructured 3D meshes, combining data-, and task-parallelism on top of the Charm++ RTS. Charm++’s execution model is asynchronous by default, allowing arbitrary overlap of computation and communication. Task-parallelism allows scheduling parts of an algorithm independently of, or dependent on, each other. Built-in automatic load balancing enables continuous redistribution of computational load by migration of work units based on real-time CPU load measurement. The RTS also features automatic checkpointing, fault tolerance, resilience against hardware failure, and supports power-, and energy-aware computation. We demonstrate scalability up to 25 x 10 9 cells at $\mathscr{O}$10 4 compute cores and the benefits of automatic load balancing for irregular workloads. The full source code with documentation is available at https://quinoacomputing.org.

42 ENGINEERING↗
NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗
DOE OSTI2021

TBAA20: Task-Based Algorithms and Applications

The new challenges posed by Exascale system architectures have resulted in difficulty achieving a desired scalability using traditional distributed ­memory runtimes. Task­-based programming models show promise in addressing these challenges, providing application developers with a productive and performant approach to programming on next generation systems. Empirical studies show that task-based models can overcome load ­balancing issues that are inherent to traditional distributed ­memory runtimes, and that task-­based runtimes perform comparably to those systems when balanced. This panel is designed to explore the advantages of task-­based programming models on modern and future HPC systems from an industry, university, and national lab perspective. It aims at gathering application experts and proponents of these models to present concrete and practical examples of using task­-based runtimes to overcome the challenges posed by Exascale system architectures. This report describes the objectives, activities, and outcomes of the panel TBAA: Task­-Based Algorithms and Applications which was held at the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC 20) on November 18, 2020.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Latency and Bandwidth Microbenchmarks of US Department of Energy Systems in the June 2023 Top 500 List

As a rule, Top 500 class supercomputers are extensively benchmarked as part of their acceptance testing process. However, barring publicly posted LINPACK / HPCG results, most benchmark results are often inaccessible outside the hosting institution. Moreover, these higher level benchmarks do not provide easy answers to common questions such as “What is the realizable memory bandwidth?” or “What is the launch latency on the accelerator?” To partially address these issues, we executed selected single-node micro-benchmarks — focused on latencies and memory bandwidth — on every US Department of Energy system above rank 150 of the June 2023 Top 500 list, excepting NERSC’s Cori and ORNL’s Frontier TDS (now decommissioned or repurposed). We hope to provide an easy “first stop” reference for users of current Top 500 systems and inspire users and administrators of other Top 500 systems to similarly compile and make available benchmark results for their systems.

Siefert, Christopher M.↗
NASA NTRS1971

Asymptotic stability properties of linear Volterra integrodifferential equations.

The Liapunov stability properties of solution to a certain system of Volterra integrodifferential equations is studied. Various types of Liapunov stability are defined; the definitions are natural extensions of the corresponding notions for ordinary differential equations. Necessary and sufficient conditions, in general, for uniform stability and uniform asymptotic stability are obtained in the form of a theorem. Connections between the stability of the system studied and the stability properties of a related Volterra integrodifferential equation with infinite memory are examined. Sufficient conditions in order that the trivial solution to the system studied be stable, uniformly stable, asymptotically stable, or uniformly asymptotically stable are derived.

Miller, R. K.↗
NASA NTRSDate not supplied

BioSentinel: Leading the Way for Deep Space CubeSat Missions

Flagship science missions are not alone in Deep Space thanks to BioSentinel, a 6U spacecraft launched on Artemis-1. BioSentinel is one of the longest operating CubeSats beyond cislunar space. The subsystems and COTS components of the BioSentinel bus are a template for future deep space missions, and the lessons learned from over a year of operations will enable improved performance for the next missions. BioSentinel achieved its unprecedented performance for an SLS secondary payload due to preparation, planning, and a robust design. Pre-launch antenna and interface testing with both DSN and ESA confirmed command and data pathways and allowed for operational flexibility in the critical early hours post-deployment. Mission Operations simulations prior to launch identified potential risks and primed operators to respond in flight, preparing the team to react quickly to successfully detumble the spacecraft and enter a power-positive state. The spacecraft would not have survived without the inclusion of the trailblazing 3D-printed composite cold gas propulsion system. The non-standard tank geometry enabled efficient use of the limited space available in the CubeSat, as well as the capability to detumble the spacecraft and manage momentum, while providing sufficient margin to execute potential delta-V maneuvers. The Iris radio has operated for over 18 months with no significant issues. Initial Iris performance estimates have been accurate throughout the mission. BioSentinel continues to collect data on thermal conditions and to validate our performance models with real-world knowledge. We have received exemplary support from our DSN partners. Following the conclusion of the primary science mission, the Linear Energy Transfer (LET) Spectrometer continued to collect solar and galactic radiation data from its location in heliocentric orbit. The free space dataset offered by the BioSentinel LET is a valuable source of data for model validation and future mission planning. As the spacecraft travels farther from Earth it is poised to provide longitudinally distributed measurements of solar particle events during solar maximum. The lessons learned from BioSentinel suggest key areas to enhance performance. The ability to upload modified flight software can increase the stability of memory management. Additional heaters in the propulsion system design have already proven successful on the Starling mission. Streamlining mission operations can reduce costs, increase data return, and better utilize DSN time. Enhancements such as these will facilitate reliable, long-duration deep space exploration using the proven BioSentinel 6U CubeSat bus.

BioSentinel↗
NASA NTRS2005

OpenMP Performance on the Columbia Supercomputer

This presentation discusses Columbia World Class Supercomputer which is one of the world's fastest supercomputers providing 61 TFLOPs (10/20/04). Conceived, designed, built, and deployed in just 120 days. A 20-node supercomputer built on proven 512-processor nodes. The largest SGI system in the world with over 10,000 Intel Itanium 2 processors and provides the largest node size incorporating commodity parts (512) and the largest shared-memory environment (2048) with 88% efficiency tops the scalar systems on the Top500 list.

Haoqiang, Jin↗
DOE OSTI2023

Adaptive cache management based on programming model information

A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.

Na, Weon Taek↗