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At least 919 records · Page 51
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Phase-Measuring System

System developed and used at Langley Research Center measures phase between two signals of same frequency or between two signals, one of which is harmonic multiple of other. Simple and inexpensive device combines digital and analog components to give accurate phase measurements. One signal at frequency f fed to pulse shaper, produces negative pulse at time t4. Pulse applied to control input of sample-and-hold module 1. Second signal, at frequency nf, fed to zero-crossover amplifier, producing square wave at time t. Signal drives first one-shot producing narrow negative pulse at t1. Signal then drives second one-shot producing narrow positive pulse at time t2. This pulse used to turn on solid-state switch and reset integrator circuit to zero.

Davis, W. T.↗
NASA NTRS1990

Battery test expert systems

The characteristics of NIHBES (nickel-hydrogen battery expert system) are described, with attention also given to NICBES-2 (nickel-cadmium battery expert system-2). The nickel-hydrogen battery testbed is set up almost identically to the nickel-cadmium battery testbed, with the exceptions of no battery protection and reconditioning circuits (BPRCs) and the frequency of transmission of data. The Ni-H2 testbed has no BPRCs and the data are transmitted every 30 s instead of every minute. An expert system shell was chosen to develop this particular expert system. The GoldWorks expert system shell from Gold Hill Computers was chosen for the task. NIHBES will extract the desired data and return fault diagnosis, status and advice, and decision support. Expert systems have been proven to be viable tools in the control and monitoring of space power systems. Presently, the DDAS (digital data acquisition system) monitors and controls the orbit time, and is responsible for limit checking, data acquisition, and data summaries. It is concluded that in the future control of the Hubble Space Telescope breadboard will be passed to NIHBES. NIHBES will be more beneficial to the testbed than the DDAS alone due to the limitations of the DDAS. The DDAS cannot provide long-term trend analysis, plotting capability, fault diagnosis, or advice.

Johnson, Yvette B.↗
NASA NTRS2011

Higher Order Parametric Excitation Modes for Spaceborne Quadrupole Mass Spectrometers

This paper describes a technique to significantly improve upon the mass peak shape and mass resolution of spaceborne quadrupole mass spectrometers (QMSs) through higher order auxiliary excitation of the quadrupole field. Using a novel multiresonant tank circuit, additional frequency components can be used to drive modulating voltages on the quadrupole rods in a practical manner, suitable for both improved commercial applications and spaceflight instruments. Auxiliary excitation at frequencies near twice that of the fundamental quadrupole RF frequency provides the advantages of previously studied parametric excitation techniques, but with the added benefit of increased sensed excitation amplitude dynamic range and the ability to operate voltage scan lines through the center of upper stability islands. Using a field programmable gate array, the amplitudes and frequencies of all QMS signals are digitally generated and managed, providing a robust and stable voltage control system. These techniques are experimentally verified through an interface with a commercial Pfeiffer QMG422 quadrupole rod system.When operating through the center of a stability island formed from higher order auxiliary excitation, approximately 50% and 400% improvements in 1% mass resolution and peak stability were measured, respectively, when compared with traditional QMS operation. Although tested with a circular rod system, the presented techniques have the potential to improve the performance of both circular and hyperbolic rod geometry QMS sensors.

Gershman, D. J.↗
NASA NTRS1975

A simulation analysis of phase processing circuitry in the Ohio University Omega receiver prototype

A FORTRAN IV simulation study of the all-digital phase-processing circuitry is described. A digital phase-lock loop (DPLL) forms the heart of the Omega navigation receiver prototype, and through the DPLL, the phase of the 10.2 KHz Omega signal was estimated when the true signal phase is contaminated with noise. The DPLL uses a frequency synthesizer as the reference oscillator. The synthesizer is composed of synchronous rate multipliers (SRM's) driven by a temperature-compensated crystal oscillator, and the use of the SRM's in this application introduces phase jitter which degrades system performance. Simulation of the frequency synthesizer discussed was to analyze the circuits on a bit-by-bit level in order to evaluate the overall design, to see easily the effects of proposed design changes prior to actual breadboarding, to determine the optimum integration time for the DPLL in an environment typical of general aviation conditions, and to quantify the phase error introduced by the SRM synthesizer and examine its effect on the system.

Palkovic, R. A.↗
NASA NTRS2005

Single-Chip FPGA Azimuth Pre-Filter for SAR

A field-programmable gate array (FPGA) on a single lightweight, low-power integrated-circuit chip has been developed to implement an azimuth pre-filter (AzPF) for a synthetic-aperture radar (SAR) system. The AzPF is needed to enable more efficient use of data-transmission and data-processing resources: In broad terms, the AzPF reduces the volume of SAR data by effectively reducing the azimuth resolution, without loss of range resolution, during times when end users are willing to accept lower azimuth resolution as the price of rapid access to SAR imagery. The data-reduction factor is selectable at a decimation factor, M, of 2, 4, 8, 16, or 32 so that users can trade resolution against processing and transmission delays. In principle, azimuth filtering could be performed in the frequency domain by use of fast-Fourier-transform processors. However, in the AzPF, azimuth filtering is performed in the time domain by use of finite-impulse-response filters. The reason for choosing the time-domain approach over the frequency-domain approach is that the time-domain approach demands less memory and a lower memory-access rate. The AzPF operates on the raw digitized SAR data. The AzPF includes a digital in-phase/quadrature (I/Q) demodulator. In general, an I/Q demodulator effects a complex down-conversion of its input signal followed by low-pass filtering, which eliminates undesired sidebands. In the AzPF case, the I/Q demodulator takes offset video range echo data to the complex baseband domain, ensuring preservation of signal phase through the azimuth pre-filtering process. In general, in an SAR I/Q demodulator, the intermediate frequency (fI) is chosen to be a quarter of the range-sampling frequency and the pulse-repetition frequency (fPR) is chosen to be a multiple of fI. The AzPF also includes a polyphase spatial-domain pre-filter comprising four weighted integrate-and-dump filters with programmable decimation factors and overlapping phases. To prevent aliasing of signals, the bandwidth of the AzPF is made 80 percent of fPR/M. The choice of four as the number of overlapping phases is justified by prior research in which it was shown that a filter of length 4M can effect an acceptable transfer function. The figure depicts prototype hardware comprising the AzPF and ancillary electronic circuits. The hardware was found to satisfy performance requirements in real-time tests at a sampling rate of 100 MHz.

Gudim, Mimi↗
NASA NTRS1978

Studies in optical parallel processing

Threshold and A/D devices for converting a gray scale image into a binary one were investigated for all-optical and opto-electronic approaches to parallel processing. Integrated optical logic circuits (IOC) and optical parallel logic devices (OPA) were studied as an approach to processing optical binary signals. In the IOC logic scheme, a single row of an optical image is coupled into the IOC substrate at a time through an array of optical fibers. Parallel processing is carried out out, on each image element of these rows, in the IOC substrate and the resulting output exits via a second array of optical fibers. The OPAL system for parallel processing which uses a Fabry-Perot interferometer for image thresholding and analog-to-digital conversion, achieves a higher degree of parallel processing than is possible with IOC.

Lee, S. H.↗
NASA NTRS2011

Crush Test Abuse Stand

The purpose of this system is to simulate an internal short on battery cells by causing deformation (a crushing force) in a cell without penetration. This is performed by activating a hydraulic cylinder on one side of a blast wall with a hydraulic pump located on the other. The operator can control the rate of the crush by monitoring a local pressure gauge connected to the hydraulic cylinder or a load cell digital display located at the hydraulic pump control area. The internal short simulated would be considered a worst-case scenario of a manufacturer fs defect. This is a catastrophic failure of a cell and could be a very destructive event. Fully charged cells are to have an internal short simulated at the center of the length of the cell (away from terminals). The crush can be performed with a .- to 1-in. (.0.6- to 2.5-cm) rod placed crossways to the cell axis, causing deformation of the cell without penetration. The OCV (open-circuit voltage) and temperature of the cells, as well as the pressure and crushing force, are recorded during the operation. Occurrence of an internal short accompanied by any visible physical changes such as venting, fires, or explosions is reported. Typical analytical data examined after the test would be plots of voltage, temperature, and pressure or force versus time. The rate of crushing force can be increased or decreased based on how fast the operator pumps the hydraulic pump. The size of cylinder used to compress the battery cell can be easily changed by adding larger or smaller fittings onto the end of the hydraulic cylinder based on the battery/cell size being tested. The cell is crushed remotely and videotaped, allowing the operator to closely monitor the situation from a safe distance.

Collins, Jacob↗
NASA NTRS1993

Synthesis algorithm of VLSI multipliers for ASIC

Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

Chua, O. H.↗
NASA NTRS2013

Data Transfer for Multiple Sensor Networks Over a Broad Temperature Range

At extreme temperatures, cryogenic and over 300 C, few electronic components are available to support intelligent data transfer over a common, linear combining medium. This innovation allows many sensors to operate on the same wire bus (or on the same airwaves or optical channel: any linearly combining medium), transmitting simultaneously, but individually recoverable at a node in a cooler part of the test area. This innovation has been demonstrated using room-temperature silicon microcircuits as proxy. The microcircuits have analog functionality comparable to componentry designed using silicon carbide. Given a common, linearly combining medium, multiple sending units may transmit information simultaneously. A listening node, using various techniques, can pick out the signal from a single sender, if it has unique qualities, e.g. a voice. The problem being solved is commonly referred to as the cocktail party problem. The human brain uses the cocktail party effect when it is able to recognize and follow a single conversation in a party full of talkers and other noise sources. High-temperature sensors have been used in silicon carbide electronic oscillator circuits. The frequency of the oscillator changes as a function of the changes in the sensed parameter, such as pressure. This change is analogous to changes in the pitch of a person s voice. The output of this oscillator and many others may be superimposed onto a single medium. This medium may be the power lines supplying current to the sensors, a third wire dedicated to data transmission, the airwaves through radio transmission, an optical medium, etc. However, with nothing to distinguish the identities of each source that is, the source separation this system is useless. Using digital electronic functions, unique codes or patterns are created and used to modulate the output of the sensor.

Krasowski, Michael↗
NASA NTRS1990

GaAs VLSI for aerospace electronics

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Larue, G.↗
NASA NTRS2003

Prototype Parts of a Digital Beam-Forming Wide-Band Receiver

Some prototype parts of a digital beamforming (DBF) receiver that would operate at multigigahertz carrier frequencies have been developed. The beam-forming algorithm in a DBF receiver processes signals from multiple antenna elements with appropriate time delays and weighting factors chosen to enhance the reception of signals from a specific direction while suppressing signals from other directions. Such a receiver would be used in the directional reception of weak wideband signals -- for example, spread-spectrum signals from a low-power transmitter on an Earth-orbiting spacecraft or other distant source. The prototype parts include superconducting components on integrated-circuit chips, and a multichip module (MCM), within which the chips are to be packaged and connected via special inter-chip-communication circuits. The design and the underlying principle of operation are based on the use of the rapid single-flux quantum (RSFQ) family of logic circuits to obtain the required processing speed and signal-to-noise ratio. RSFQ circuits are superconducting circuits that exploit the Josephson effect. They are well suited for this application, having been proven to perform well in some circuits at frequencies above 100 GHz. In order to maintain the superconductivity needed for proper functioning of the RSFQ circuits, the MCM must be kept in a cryogenic environment during operation.

Kaplan, Steven B.↗
NASA NTRS1996

Feedback Linearization in a Six Degree-of-Freedom MAG-LEV Stage

A six degree-of-freedom electromagnetically suspended motion control stage (the Angstrom Stage) has been designed and constructed for use in short-travel, high-resolution motion control applications. It achieves better than 0.5 nm resolution over a 100 micron range of travel. The stage consists of a single moving element (the platen) floating in an oil filled chamber. The oil is crucial to the stage's operation since it forms squeeze film dampers between the platen and the frame. Twelve electromagnetic actuators provide the forces necessary to suspend and servo the platen, and six capacitance probes measure its position relative to the frame. The system is controlled using a digital signal processing board residing in a '486 based PC. This digital controller implements a feedback linearization algorithm in real-time to account for nonlinearities in both the magnetic actuators and the fluid film dampers. The feedback linearization technique reduces a highly nonlinear plant with coupling between the degrees of freedom into one that is linear, decoupled, and setpoint independent. The key to this procedure is a detailed plant model. The operation of the feedback linearization procedure is transparent to the outer loop of the controller, and so a proportional controller is sufficient for normal operation. We envision applications of this stage in scanned probe microscopy and for integrated circuit measurement.

Ludwick, Stephen J.↗
NASA NTRS1990

Optimal digital control of a Stirling cycle cooler

This short paper describes work in progress on the conceptual design of a control system for a cryogenic cooler intended for use aboard spacecraft. The cooler will produce 5 watts of cooling at 65 K and will be used to support experiments associated with the following: earth observation; atmospheric measurements; infrared, x-ray, and gamma-ray astronomy; and magnetic field characterization. The cooler has been designed and constructed for NASA/GSFC by Philips Laboratories and is described in detail. The cooler has a number of unique design features intended to enhance long life and maintenance free operation in space including use of the high efficiency Stirling thermodynamic refrigeration cycle, linear magnetic motors, clearance-seals, and magnetic bearings. The proposed control system design is based on optimal control theory and is targeted for custom integrated circuit implementation. The resulting control system will meet the following mission requirements: efficiency, reliability, optimal thermodynamic, electrical, and mechanical performance; freedom from operator intervention; light weight; and small size.

Feeley, J.↗
NASA NTRS2011

Fault-Tolerant, Radiation-Hard DSP

Commercial digital signal processors (DSPs) for use in high-speed satellite computers are challenged by the damaging effects of space radiation, mainly single event upsets (SEUs) and single event functional interrupts (SEFIs). Innovations have been developed for mitigating the effects of SEUs and SEFIs, enabling the use of very-highspeed commercial DSPs with improved SEU tolerances. Time-triple modular redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW (very long instruction word) class of parallel processors. TTMR improves SEU rates substantially. SEFIs are solved by a SEFI-hardened core circuit, external to the microprocessor. It monitors the health of the processor, and if a SEFI occurs, forces the processor to return to performance through a series of escalating events. TTMR and hardened-core solutions were developed for both DSPs and reconfigurable field-programmable gate arrays (FPGAs). This includes advancement of TTMR algorithms for DSPs and reconfigurable FPGAs, plus a rad-hard, hardened-core integrated circuit that services both the DSP and FPGA. Additionally, a combined DSP and FPGA board architecture was fully developed into a rad-hard engineering product. This technology enables use of commercial off-the-shelf (COTS) DSPs in computers for satellite and other space applications, allowing rapid deployment at a much lower cost. Traditional rad-hard space computers are very expensive and typically have long lead times. These computers are either based on traditional rad-hard processors, which have extremely low computational performance, or triple modular redundant (TMR) FPGA arrays, which suffer from power and complexity issues. Even more frustrating is that the TMR arrays of FPGAs require a fixed, external rad-hard voting element, thereby causing them to lose much of their reconfiguration capability and in some cases significant speed reduction. The benefits of COTS high-performance signal processing include significant increase in onboard science data processing, enabling orders of magnitude reduction in required communication bandwidth for science data return, orders of magnitude improvement in onboard mission planning and critical decision making, and the ability to rapidly respond to changing mission environments, thus enabling opportunistic science and orders of magnitude reduction in the cost of mission operations through reduction of required staff. Additional benefits of COTS-based, high-performance signal processing include the ability to leverage considerable commercial and academic investments in advanced computing tools, techniques, and infra structure, and the familiarity of the science and IT community with these computing environments.

Czajkowski, David↗
NASA NTRS2013

Minimal Power Latch for Single-Slope ADCs

Column-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics

Hancock, Bruce R.↗
NASA NTRS2018

Stirling Convertor Controller Development at NASA Glenn Research Center

For nearly two decades, NASA Glenn Research Center has been supporting the development of radioisotope power systems (RPS). NASA desires higher conversion efficiency RPS options that are reliable and robust with long-life design. Dynamic conversion, such as Stirling and Brayton, offer the potential for higher conversion efficiencies than current RPS but have yet to be demonstrated in a flight application. The RPS program sent out a solicitation to investigate options for dynamic conversion technologies. As a result of this solicitation, four dynamic power convertor (DPC) technologies were selected for design and three are proceeding to the fabrication phase of prototype dynamic convertors. One lesson learned from the Advanced Stirling Radioisotope Generator (ASRG) project is that controller development should be coordinated with the development of a dynamic convertor. As a result of this, Glenn has been utilizing hardware from past Stirling convertor projects, including that of the ASRG, to support controller development for the DPCs. Glenn has developed a strong knowledge base on both analog and digital Stirling DPC controllers and will continue to expand and apply that knowledge to the DPCs. Over the past 15 years, controllers were developed at Glenn, at Lockheed Martin (LM), and by the Johns Hopkins University Applied Physics Laboratory (APL). Various generations of the controllers have been developed as lessons were learned through various component- and system-level tests. Some of the tests performed were fault tolerance, flight acceptance vibration, electromagnetic interference (EMI), spacecraft integration, and extended operation. The fault tolerance test characterized the controller’s ability to handle various fault conditions, including high or low bus power consumption, total open load or short circuit, and replacing a failed controller card while the backup maintains control of the Stirling convertor. The vibration test confirms the controller’s ability to control an Advanced Stirling Convertor (ASC) during launch. The EMI test characterized the alternating-current (AC) and direct-current (DC) magnetic and electric fields emitted by the single ASC and if the controller has an impact on the radiated EMI. Spacecraft integration testing in the Radioisotope Power Systems (RPS), System Integration Laboratory (RSIL) provided insight into the electrical interactions between the representative RPS, its associated control schemes, and realistic electric system loads. The extended operation test allows data to be collected over a period of thousands of hours to obtain long-term performance data of the system. This paper describes the history of controller development at Glenn, tests performed on these controllers, and lessons learned.

Dugala, Gina M.↗
NASA NTRS1991

The MARCOR GPS mobile data system

Market research revealed several key demands for an Automatic Vehicle Location (AVL) Global Positioning System (GPS) radio. The demands were for minimization of urban building blockage, easy programmability to minimize mobile data transmission costs, high accuracy for street map level coordination, interface capability with non-digital Specialized Mobile Radios (SMR), and a selling price close to that of alternatives such as Signposts and Loran-C. A team of experts was assembled to surmount these challenges and deliver a GPS radio for $500 to $1000, which operates at high accuracy in an urban environment and is plug-compatible with nearly all vehicle radios. Among the engineering and production breakthroughs described here are a unique Simultrac (Trademark) approach to satellite tracking, enabling up to eight GPS satellites to be used for position determination with a 2-channel receiver, and a receiver-in-a-microphone design. A powerful Application Specific Integrated Circuit (ASIC) allowed GPS to be brought within easy reach of millions of AVL users such as bus, taxi, and delivery vehicle fleets.

Rothblatt, Martin↗
NASA NTRS2012

Characterization of the Vectron PX-570 Crystal Oscillator for Use in Harsh Environments

Computing hardware, data-acquisition systems, communications systems, and many electronic control systems require well-controlled timing signals for proper and accurate operation. These signals are, in most cases, provided by circuits that employ crystal oscillators due to availability, cost, ease of operation, and accuracy. In some cases, the electronic systems are expected to survive and operate under harsh conditions that include exposure to extreme temperatures. These applications exist in terrestrial systems as well as in aerospace products. Well-logging, geothermal systems, and industrial process control are examples of ground-based applications, while distributed jet engine control in aircraft, space-based observatories (such as the James Webb Space Telescope), satellites, and lunar and planetary landers are typical environments where electronics are exposed to harsh operating conditions. To ensure these devices produce reliable results, the digital heartbeat from the oscillator must deliver a stable signal that is not affected by external temperature or other conditions. One such solution is a recently introduced commercial-off-the-shelf (COTS) oscillator, the PX-570 series from Vectron International. The oscillator was designed for high-temperature applications and as proof, the crystal oscillator was subjected to a wide suite of tests to determine its ruggedness for operation in harsh environments. The tests performed by Vectron included electrical characterization under wide range of temperature, accelerated life test/aging, shock and vibration, internal moisture analysis, ESD threshold, and latch-up testing. The parametric evaluation was performed on the oscillator's frequency, output signal rise and fall times, duty cycle, and supply current over the temperature range of -125 C to +230 C. The evaluations also determined the effects of thermal cycling and the oscillator's re-start capability at extreme hot and cold temperatures. These thermal cycling and restart tests were performed at the NASA Glenn Research Center. Overall, the crystal oscillator performed well and demonstrated very good frequency stability. This paper will discuss the test procedures and present details of the performance results.

Li, Jacob↗