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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 919 records · Page 51
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

A Low Voltage DC Power Electronic Hub to Support Buildings

This paper presents the communication, control, and architecture, for a low voltage (nominal 480V) hybrid AC/DC microgrid for supporting small commercial buildings with critical data center loads. The proposed system is based on a dc-power electronic hub (PEH) that seamlessly integrates renewable energy resources, energy storage, and back-up generation to support commercial building economical energy management and reliability. This PEH concept provides a parallelization of critical power to the commercial and industrial buildings leading to increased efficiency and reliability compared to traditional uninterruptable power supplies. The demonstration of the proposed PEH architecture and controls is conducted through a controller hardware in the loop validation.

Starke, Michael↗
DOE OSTI2024

Decoupling Power Quality Issues in Grid-Microgrid Network Using Microgrid Building Blocks

Microgrids are evolving as promising options to enhance reliability of the connected transmission and distribution systems. Traditional design and deployment of microgrids require significant engineering analysis. However, Microgrid Building Blocks (MBB), consisting of modular blocks that integrate seamlessly to form effective microgrids, are promising technologies to enable faster and broader adoption of microgrids. Back-to-Back converter placed at the point of common coupling of microgrid is an integral part of MBB. This paper presents applications of MBB to decouple power quality issues in grid-microgrid network serving power quality sensitive critical loads such as data centers, new grid-edge technologies such as vehicle-to-grid generation, and emergency condition loads such as electric vehicle charging loads during evacuation prior disaster events. Simulation results show that MBB effectively decouple the power quality issues across networks and allow network with low power quality to transfer high-power quality power to connected networks during emergency conditions.

Acharya, Samrat S. [BATTELLE (PACIFIC NW LAB)]↗
DOE OSTI2026

A Novel Low-Profile High-Efficiency Three-Phase Matrix Transformer

High step-down isolated DC-DC conversion from an 800 V DC bus to low-voltage, high-current outputs is required in automotive auxiliary converters and data center power supplies. In such applications, conventional transformer-based converters require large turns ratios, which increase winding resistance, leakage inductance, and magnetic height. This paper proposes a novel low-profile three-phase matrix transformer that realizes a large effective voltage ratio through flux division among multiple secondary legs, without increasing the physical turns count of each winding. As a result, the proposed structure reduces copper usage and transformer height while preserving the voltage conversion capability of a conventional three-phase transformer. Finite element analysis shows that the proposed design reduces magnetic height by 27%, ferrite volume by 34%, and copper volume by 28%. Circuit-level simulations of an 800 V/12 V,3 kW CLLLC dual-active-bridge converter further show that the lower winding resistance reduces total system loss by 91% and increases DC-DC efficiency from 82.6% to 97.6% at 3 kW output.

Inoue, Shuntaro [ORNL] (ORCID:0000000262637627)↗
DOE OSTI2025

Convergence of Energy and IT Sectors

Today there has never been a more profound codependence and synergetic convergence, such as the one between the energy and IT sectors, and the industries will need to work together more closely to meet today’s growing data center power demands.

AI↗
DOE OSTI2025

Future Industrial Demand: Large, Elastic, and Concentrated [Guest Editorial]

Here, the future industrial demand on the grid is expected to be large, price sensitive, and concentrated. Grid industrial demand increasingly encompasses a new customer type defined as a large flexible load (LFL). This LFL type defines customers with consumption that responds quickly to price or other incentives without interrupting their core business process, such cryptocurrency mining. This customer type can often ramp up and down quickly, which across an entire industry can mean gigawatts of power within a few minutes. In addition to these price-sensitive loads, significant growth is also anticipated in sectors like manufacturing, data centers, and electrification of transportation and buildings.

Mukherjee, Srijib [Oak Ridge National Laboratory (↗
DOE OSTI2024

From Failure to Insight: Analyzing Disk Breakdowns in Large-Scale HPC Environments

Disk failure data provides valuable insights for preventing failures, enhancing storage robustness, guiding system design and deployment, and ensuring reliable operations at data centers. This paper introduces two disk failure datasets collected from large-scale HPC production environments over the past five years, comprising over 5,000 failure records from more than 40,000 disks. We analyzed these datasets across multiple dimensions, including temporal, spatial, and relational trends, and performed a comprehensive reliability assessment. Our analysis yielded numerous observations and insights that influence various operational aspects of HPC storage systems. We believe this study offers a holistic understanding of disk failure trends likely to interest the HPC storage community.

George, Anjus↗
DOE OSTI2024

Foreword: Special Section on Multiphysics Aspects of Power Electronics Packaging - Power Die, Power Module, and Converter Level - Part 1

Power electronics are increasingly being used to condition electricity for a wide array of applications, such as transportation (on land, air, and water), data centers, radio frequency, directed energy, wind, solar, and grid-tied applications. To increase power density, performance, efficiency, and reliability and reduce cost, innovations and developments are needed in the multiphysics packaging of power electronics at a die, module, and converter level. This includes fundamental research and development related to emerging high-voltage, high-temperature, and high-switching-frequency power electronics; packaging materials; thermal materials and interfaces; fluid-based thermal management technologies; reliability; condition monitoring; and prognostics. To address these important aspects, this Special Section on Multiphysics Aspects of Power Electronics Packaging includes several articles to be published in two parts. More details are given below on the articles included in the first part.

condition monitoring↗
DOE OSTI2024

Foreword: Special Section on Multiphysics Aspects of Power Electronics Packaging—Power Die, Power Module, and Converter Level: Part 2

Power electronics are increasingly being used to condition electricity for a wide array of applications, such as transportation (on land, air, and water), data centers, radio frequency, directed energy, wind, solar, and grid-tied applications. Here, to increase power density, performance, efficiency, and reliability-as well as to reduce cost-innovations and developments are needed in the multiphysics packaging of power electronics at a die, module, and converter level. This includes fundamental R&D related to emerging high-voltage, high-temperature, and high-switching-frequency power electronics, packaging materials, thermal materials and interfaces, fluid-based thermal management technologies, reliability, condition monitoring, and prognostics. Latest developments in this area are published as a Special Section on Multiphysics Aspects of Power Electronics Packaging. The first part was published in the May 2024 issue of the IEEE Transactions on Components, Packaging and Manufacturing Technology (Volume 14, Issue 5). The second part of that Special Section is being published in this issue. A brief summary of the papers included in the second part are given below.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2020

Soft-Switching Solid-State Transformer With Reduced Conduction Loss

Solid-state transformers (SSTs) are a promising solution photovoltaic (PV), wind, traction, data center, battery energy storage system (BESS), and fast charging electric vehicle (EV) applications. The traditional SSTs are typically three-stage, i.e., hard-switching cascaded multilevel rectifiers and inverters with dual active bridge (DAB) converters, which leads to bulky passives, low efficiency, and high electromagnetic interference (EMI). This article proposes a new soft-switching solid-state transformer (S4T). The S4T has full-range zero-voltage switching (ZVS), electrolytic capacitor-less dc link, and controlled dv/dt, which reduces EMI. The S4T comprises two reverse-blocking current-source inverter (CSI) bridges, auxiliary branches for ZVS, and transformer magnetizing inductor as a reduced dc link with 60% ripple. Compared with the prior S4T, an effective change on the leakage inductance diode is made to reduce the number of the devices on the main power path by 20% for significant conduction loss saving and retain the same functionality of damping the resonance between the leakage and resonant capacitors and recycling trapped leakage energy. The conduction loss saving is crucial, being the dominating loss mechanism in SSTs. Importantly, the proposed single-stage SST not only holds the potential for high power density and high efficiency but also has full functionality, e.g., multiport dc loads integration, voltage regulation, and reactive power compensation, unlike the traditional single-stage matrix SST. The S4T can achieve single-stage isolated bidirectional dc–dc, ac–dc, dc–ac, or ac–ac conversion. It can also be configured input-series output-parallel (ISOP) in a modular way for medium-voltage (MV) grids. Hence, the S4T is a promising candidate for the SST. The full functionality, e.g., voltage buck–boost, multiport, etc., and the universality of the S4T for the dc–dc, dc–ac, and ac–ac conversion are verified through the simulations and experiments of two-port and three-port MV prototypes based on 3.3 kV SiC MOSFETs in dc–dc, dc–ac, and ac–ac modes at 2 kV.

14 SOLAR ENERGY↗
DOE OSTI2022

7.2 kV Three-Port SiC Single-Stage Current-Source Solid-State Transformer With 90 kV Lightning Protection

This article proposes a multiport modular single-stage current-source solid-state transformer (SST) for applications like photovoltaic, energy storage integration, electric vehicle fast charging, data center, etc. The 7.2 kV 50 kVA current-source SST consists of five input-series output-parallel modules, each based on 3.3 kV SiC reverse-blocking MOSFET-plus-diode modules. The proposed SST has some unique features. First, compared to the voltage-source or matrix converter-based SSTs, the current-source SST has a unique advantage of single-stage isolated AC/DC or AC/AC conversion with an inductive DC link, but no medium-voltage (MV) AC experiments have been reported. This article for the first time demonstrates MV AC current-source SST up to 7.5 kV peak. Second, the multiport SST has a buffer port for active power decoupling (APD) or energy storage integration. The double-line-frequency power ripple from single-phase AC grid normally results in a large capacitor size in MV SSTs. The APD scheme is proposed in MV applications for the first time to enable a reduced DC link and the electrolytic capacitor-less SST with high reliability. Third, as a direct grid-connected converter without line-frequency transformer, insulation and protection are critical. A medium-frequency transformer design passes 55 kV basic-insulation level (BIL) and 60 kV high potential dielectrics withstand test with only 0.09% leakage inductance. Importantly, a lightning protection scheme is presented to protect the SST itself from 90 kV BIL impulse. Fourth, the proposed current-source SST topology is a modular soft-switching solid-state transformer (M-S4T) with full-range zero-voltage switching and controlled dv/dt for low electromagnetic interference. Furthermore, these concepts are verified in a three-port M-S4T prototype with forced oil cooling under single-module, stacked-module, steady-state, and dynamic operations.

14 SOLAR ENERGY↗
DOE OSTI2025

The environmental impact, carbon emissions and sustainability of computing in the ATLAS experiment

ATLAS, a general-purpose experiment at the Large Hadron Collider (LHC), makes use of a large internationally-distributed computing infrastructure, including over 10 6 TB of managed data on disk and tape and almost one million simultaneously running CPU cores. Upgrades for the High-Luminosity LHC (HL-LHC) will increase the required computing resources by a factor of 3–4 by the beginning of the 2030s, and by an order of magnitude before the conclusion of data taking at the beginning of the 2040s. These resources are spread over around 100 computing sites worldwide. Efforts are underway within the experiment to evaluate and mitigate various aspects of the environmental impact of the sites, with the additional long-term goal of making recommendations to the sites that will significantly reduce the total expected environmental impact in the HL-LHC era. These efforts take several forms: building awareness in the experiment community, adjusting aspects of the computing policy, and modifications of data center configurations, either in ways that take advantage of particular features of ATLAS workloads or in generic ways that reduce the environmental impact of the computing resources. This paper describes the ongoing investigations and approaches that have already provided useful and actionable outcomes.

Aad, G. [CNRS/IN2P3] (ORCID:0000000266654934)↗
DOE OSTI2021

MAPA: Multi-Accelerator Pattern Allocation Policy for Multi-Tenant GPU Servers

Multi-accelerator servers are increasingly being deployed in shared multi-tenant environments (such as in cloud data centers) in order to meet the demands of large-scale compute-intensive workloads. In addition, these accelerators are increasingly being inter-connected in complex topologies and workloads are exhibiting a wider variety of inter-accelerator communication patterns. However, existing al-location policies are ill-suited for these emerging use-cases. Specifically, this work identifies that multi-accelerator workloads are commonly fragmented leading to reduced bandwidth and increased latency for inter-accelerator communication. We propose Multi-Accelerator Pattern Allocation (MAPA), a graph pattern mining approach towards providing generalized allocation support for allocating multi-accelerator workloads on multi-accelerator servers. We demonstrate that MAPA is able to improve the execution time of multi-accelerator workloads and that MAPA is able to provide generalized benefits across various accelerator topologies. Finally, we demonstrate a speedup of 12.4% for75th percentile of jobs with the worst case execution time reduced by up to 35% against baseline policy using MAPA.

Ranganath, Kiran↗
DOE OSTI2023

Spy in the GPU-box: Covert and Side Channel Attacks on Multi-GPU System

The deep learning revolution has been enabled in large part by GPUs, and more recently accelerators, which make it possible to carry out computationally demanding training and inference in acceptable times. As the size of machine learning networks and workloads continues to increase, multi-GPU machines have emerged as an important platform offered on High Performance Computing and cloud data centers. Since these machines are shared among multiple users, it becomes increasingly important to protect applications against potential attacks. In this paper, we explore the vulnerability of Nvidia's DGX multi-GPU machines to covert and side channel attacks. These machines consist of a number of discrete GPUs that are interconnected through a combination of custom interconnect (NVLink) and PCIe connections. We reverse engineer the interconnected cache hierarchy and show that it is possible for an attacker on one GPU to cause contention on the L2 cache of another GPU. We use this observation to first develop a covert channel attack across two GPUs, achieving the best bandwidth of around 4 MB/s. We also develop a prime and probe attack on a remote GPU allowing an attacker to recover the cache access pattern of another workload. This access pattern can be used in any number of side channel attacks: we demonstrate a proof of concept attack that fingerprints the application running on the remote GPU, with high accuracy. We also develop a proof of concept attack to extract hyperparameters of a machine learning workload. Our work establishes for the first time the vulnerability of these machines to microarchitectural attacks and can guide future research to improve their security.

Dutta, Sankha↗
DOE OSTI2023

Application Experiences on a GPU-Accelerated Arm-based HPC Testbed

This paper assesses and reports the experience of ten teams working to port, validate, and benchmark several High Performance Computing applications on a novel GPU-accelerated Arm testbed system. The testbed consists of eight NVIDIA Arm HPC Developer Kit systems, each one equipped with a server-class Arm CPU from Ampere Computing and two data center GPUs from NVIDIA Corp. The systems are connected together using InfiniBand interconnect. The selected applications and mini-apps are written using several programming languages and use multiple accelerator-based programming models for GPUs such as CUDA, OpenACC, and OpenMP offloading. Working on application porting requires a robust and easy-to-access programming environment, including a variety of compilers and optimized scientific libraries. The goal of this work is to evaluate platform readiness and assess the effort required from developers to deploy well-established scientific workloads on current and future generation Arm-based GPU-accelerated HPC systems. The reported case studies demonstrate that the current level of maturity and diversity of software and tools is already adequate for large-scale production deployments.

Elwasif, Wael↗
DOE OSTI2023

A MultiGPU Performance-Portable Solution for Array Programming Based on Kokkos

Today, multiGPU nodes are widely used in high-performance computing and data centers. However, current programming models do not provide simple, transparent, and portable support for automatically targeting multiple GPUs within a node on application areas of array programming. In this paper, we describe a new application programming interface based on the Kokkos programming model to enable array computation on multiple GPUs in a transparent and portable way across both NVIDIA and AMD GPUs. We implement different variations of this technique to accommodate the exchange of stencils (array boundaries) among different GPU memory spaces, and we provide autotuning to select the proper number of GPUs, depending on the computational cost of the operations to be computed on arrays, that is completely transparent to the programmer. We evaluate our multiGPU extension on Summit (#5 TOP500), with six NVIDIA V100 Volta GPUs per node, and Crusher that contains identical hardware/software as Frontier (#1 TOP500), with four AMD MI250X GPUs, each with 2 Graphics Compute Dies (GCDs)for a total of 8 GCDs per node. We also compare the performance of this solution against the use of MPI + Kokkos, which is the cur-rent de facto solution for multiple GPUs in Kokkos. Our evaluation shows that the new Kokkos solution provides good scalability for many GPUs and a faster and simpler solution (from a programming productivity perspective) than MPI + Kokkos.

Valero Lara, Pedro↗
DOE OSTI2024

Performance Study of CXL Memory Topology

This paper presents a comprehensive evaluation of the performance impact of various Compute Express Link (CXL) memory topologies, with a particular emphasis on CXL switches, in the context of High- Performance Computing (HPC) and Large Language Model (LLM) inference workloads. Our study unveils significant performance variations across different topologies, demonstrating that certain configurations yield superior performance for specific workloads. These findings underscore the critical importance of tailored topol- ogy selection in optimizing system performance. Additionally, we address the inherent challenges associated with integrating CXL switches, including overhead considerations and routing complex- ities. Our research highlights the necessity for thorough evalua- tion methodologies to fully leverage CXL technology’s potential in contemporary computing environments. These insights provide valuable guidance for system architects and data center operators in designing and optimizing CXL-based infrastructures for diverse workload requirements.

CXL, memory, Artificial Intelligence (AI), HPC↗
DOE OSTI2025

Extending SEER for Extreme Heterogeneity

Heterogeneous and multi-device nodes are increasingly common in high-performance computing and data centers, yet existing programming models often lack simple, transparent, and portable support for these diverse architectures. The main contribution of this work is the development of novel SEER capabilities to address this challenge by providing a descriptive programming model that allows applications to seamlessly leverage heterogeneous nodes across various device types. SEER uses efficient memory management and can select the proper device[s] depending on the computational cost of the applications. This is completely transparent to the programmer, thereby providing a highly productive programming environment. Integrating extreme heterogeneity into the SEER library as shown with the use of NVIDIA and AMD GPUs simultaneously allows it to expand and exploit the performance possibilities. Our analysis based on the well-known Conjugate Gradient algorithm reports accelerations above 1.5 × on computationally demanding steps of such an algorithm by using both architectures simultaneously.

Teranishi, Keita [ORNL] (ORCID:0000000166472690)↗