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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Stripe-line pattern is etched on both sides of double-sided film. Since conductor thickness is only half that of single-sided film, problems in wrapping and etching are greatly reduced.
Concept has several important advantages over close-wound system: memory and coil chips are separate and interchangeable; interconnections in coil level are eliminated by packing memory chip and electronics in single structure; and coil size can be adjusted to optimum value in terms of power dissipation and field uniformity.
Size and thickness of field adjusting plate can be varied. Memory chip specification is relaxed, since chips in structure need not be matched in bias margin.
To aid work being conducted on the feasibility of a low cost Omega navigational receiver, a control panel was designed and constructed according to supplied specifications. Since the proposed Omega receiver is designed around a microprocessor, software engineering necessary for control panel operation is included in the design. The control panel is to be used as an operational model for use in the design of a prototype receiver. A detailed description of the hardware design is presented along with a description of the software needed to operate the panel. A complete description of the operating procedures for the panel are also included.
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Bar-spacing tolerances are relaxed in replicator suitable for low-drive field.
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Several versions of the 100K bit chip, which is configured as a single serial loop, were designed, fabricated and evaluated. Design and process modifications were introduced into each succeeding version to increase device performance and yield. At an intrinsic field rate of 150 KHz the final design operates from -10 C to +60 C with typical bias margins of 12 and 8 percent, respectively, for continuous operation. Asynchronous operation with first bit detection on start-up produces essentially the same margins over the temperature range. Cost projections made from fabrication yield runs on the 100K bit devices indicate that the memory element cost will be less than 10 millicents/bit in volume production.
Design, fabrication and test of partially populated prototype recorder using 100 kilobit serial chips is described. Electrical interface, operating modes, and mechanical design of several module configurations are discussed. Fabrication and test of the module demonstrated the practicality of multiplexing resulting in lower power, weight, and volume. This effort resulted in the completion of a module consisting of a fully engineered printed circuit storage board populated with 5 of 8 possible cells and a wire wrapped electronics board. Interface of the module is 16 bits parallel at a maximum of 1.33 megabits per second data rate on either of two interface buses.
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