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All sources NASA NTRS DOE OSTI

NASA NTRS2010

FPGA-based hardware/software co-design instrument command-and-control solutions

Traditional design methodology dictates that an instrument electronics platform should consist of a printed circuit board (PCB)—often multiple boards—populated with many components and support electronics. More specifically, each subsystem is composed of numerous integrated circuits (ICs) spread across the board(s), connected with innumerable traces and wires. Additionally, it is often the case that the hardware and software design teams are quite separated—the hardware team designs a board and hands it to a software team, who must then deal with any hardware quirkiness and may need to rewrite software due to inadequately defined interfaces...

Allen, Mark A.↗

NASA NTRS2008

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

The fabrication and testing of the first semiconductor transistors and small-scale integrated circuits (ICs) to achieve up to 3000 h of stable electrical operation at 500 C in air ambient is reported. These devices are based on an epitaxial 6H-SiC junction field-effect transistor process that successfully integrated high temperature ohmic contacts, dielectric passivation, and ceramic packaging. Important device and circuit parameters exhibited less than 10% of change over the course of the 500 C operational testing. These results establish a new technology foundation for realizing durable 500 C ICs for combustion-engine sensing and control, deep-well drilling, and other harsh-environment applications.

Neudeck, Philip G.↗

DOE OSTI2024

Toward quantum networking with frequency-bin qudits

Quantum networking holds tremendous promise in transforming computation and communication. Entangled-photon sources are critical for quantum repeaters and networking, while photonic integrated circuits are vital for miniaturization and scalability. In this talk, we focus on generating and manipulating frequency-bin entangled states within integrated platforms. We encode quantum information as a coherent superposition of multiple optical frequencies; this approach is favorable due to its amenability to high-dimensional entanglement and compatibility with fiber transmission. We successfully generate and measure the density matrix of biphoton frequency combs from integrated silicon nitride microrings, fully reconstructing the state in an 8 × 8 two-qudit Hilbert space, the highest so far for frequency bins. Moreover, we employ Vernier electro-optic phase modulation methods to perform time-resolved measurements of biphoton correlation functions. Currently, we are exploring bidirectional pumping of microrings to generate indistinguishable entangled pairs in both directions, aiming to demonstrate key networking operations such as entanglement swapping and Greenberger–Horne–Zeilinger state generation in the frequency domain.

Myilswamy, Karthik V.↗

NASA NTRS1980

Solar cell system having alternating current output

A monolithic multijunction solar cell was modified by fabricating an integrated circuit inverter on the back of the cell to produce a device capable of generating an alternating current output. In another embodiment, integrated curcuit power conditioning electronics was incorporated in a module containing a solar cell power supply.

Evans, J. C., Jr.↗

NASA NTRS2010

SEU/SET Tolerant Phase-Locked Loops

The phase-locked loop (PLL) is an old and widely used circuit for frequency and phase demodulation, carrier and clock recovery, and frequency synthesis [1]. Its implementations range from discrete components to fully integrated circuits and even to firmware or software. Often the PLL is a highly critical component of a system, as for example when it is used to derive the on-chip clock, but as of this writing no definitive single-event upset (SET)/single-event transient (SET) tolerant PLL circuit has been described. This chapter hopes to rectify that situation, at least in regard to PLLs that are used to generate clocks. Older literature on fault-tolerant PLLs deals with detection of a hard failure, which is recovered by replacement, repair, or manual restart of discrete component systems. Several patents exist along these lines (6349391, 6272647, and 7089442). A newer approach is to harden the parts of a PLL system, to one degree or another, such as by using a voltage-based charge pump or a triple modular redundant (TMR) voted voltage-controlled oscillator (VCO). A more comprehensive approach is to harden by triplication and voting (TMR) all the digital pieces (primarily the divider) of a frequency synthesis PLL, but this still leaves room for errors in the VCO and the loop filter. Instead of hardening or voting pieces of a system, such as a frequency synthesis system (i.e., clock multiplier), we will show how the entire system can be voted. There are two main ways of doing this, each with advantages and drawbacks. We will show how each has advantages in certain areas, depending on the lock acquisition and tracking characteristics of the PLL. Because of this dependency on PLL characteristics, we will briefly revisit the theory of PLLs. But first we will describe the characteristics of voters and their correct application, as some literature does not follow the voting procedure that guarantees elimination of errors. Additionally, we will find that voting clocks is a bit trickier than voting data where an infallible clock is assumed. It is our job here to produce (or recover) that assumed infallible clock!

Shuler, Robert L., Jr.↗

NASA NTRS1981

Arc spraying solderable tabs to glass

Tabs suitable for electrical or mechanical connections in solar cells and integrated circuits are made by spraying technique. Solder wets copper, copper bonds to aluminum, and aluminum adheres to glass. Arc spraying is automated and integrated with encapsulation, eliminating hand tabbing, improving reliability, and reducing cost.

Lindmayer, J.↗

NASA NTRS1987

Tester for Multiple-Conductor Cables

Portable testing circuit enables technician to determine quickly wiring errors in multiple-conductor electrical cable or terminal connectors. Active unit tester made of inexpensive integrated circuits and other readily available components. Timer and one-shot generate pulses counted by shift registers. Shift-register output terminals wired to connector pins so voltage applied to each pin in sequence.

Wirth, Manfred N.↗

NASA NTRS1983

GaAs microwave devices and circuits with submicron electron-beam defined features

This paper describes the fabrication and application of GaAs FET's, both as discrete microwave devices and as the key active components in monolithic microwave integrated circuits. The performance of these devices and circuits is discussed for frequencies ranging from 3 to 25 GHz. The crucial fabrication step is the formation of the submicron gate by electron-beam lithography.

Wisseman, W. R.↗

NASA NTRSDate not supplied

Radiation-Hard Parallel Readout Circuit for Low-Frequency Voltage Signal Measurements

NASA Goddard Space Flight Center (GSFC) has successfully developed and tested a custom-designed low-noise multi-channel digitizer (MCD) application specific integrated circuit (ASIC) for operation in harsh radiation environments. The MCD-ASIC is optimized for low-frequency and low-voltage signal measurements from sensors and transducers. It has 20 input channels where each channel is comprised of auto-zeroed chopper variable-gain amplifier, post amplifier, and a second order ∑∆ modulator. ∑∆ analog-to-digital converter (ADC) relies on oversampling and noise shaping to achieve high-resolution conversion. However, the MCD-ASIC requires digital filtering and decimation to convert the output single bit streams from the ADC to useful data words. A parallel digital platform such as a field-programmable-gate-array (FPGA) is highly suitable to fully leverage the capabilities of the MCD-ASIC. The FPGA controls the MCD-ASIC via serial peripheral interface (SPI) protocol and acquires data from it. A Python-script communicates with the FPGA board through a USB interface on a cross operating platform. Using this architecture, the system is capable of monitoring up to 20 voltage readout channels simultaneously in a real-time manner. Each channel’s parameters can be programmed independently allowing maximum user versatility. In this paper, we present analysis of the analog front-end, the implementation of the digital processing unit on the FPGA, and provide noise performance results from the MCD-ASIC readout.

ASIC↗

DOE OSTI2022

Rate-capability of the VMM3a front-end in the RD51 Scalable Readout System

The VMM3a is an Application Specific Integrated Circuit (ASIC), specifically developed for the readout of gaseous detectors. Originally developed within the ATLAS New Small Wheel (NSW) upgrade, it has been successfully integrated into the Scalable Readout System (SRS) of the RD51 collaboration. This allows, to use the VMM3a also in small laboratory set-ups and mid-scale experiments, which make use of Micro-Pattern Gaseous Detectors (MPGDs). As part of the integration of the VMM3a into the SRS, the readout and data transfer scheme was optimised to reach a high rate-capability of the entire readout system and profit from the VMM3a's high single-channel rate-capability of 3.6Mhits/s. The optimisation focused mainly on the handling of the data output stream of the VMM3a, but also on the development of a trigger-logic between the front-end cards and the DAQ computer. In this article, two firmware implementations of the non-ATLAS continuous readout mode are presented, as well as the implementation of the trigger-logic. Afterwards, a short overview on X-ray imaging results is presented, to illustrate the high rate-capability from an application point-of-view.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2025

Optoelectronic polymer memristors with dynamic control for power-efficient in-sensor edge computing

Abstract As the demand for edge platforms in artificial intelligence increases, including mobile devices and security applications, the surge in data influx into edge devices often triggers interference and suboptimal decision-making. There is a pressing need for solutions emphasizing low power consumption and cost-effectiveness. In-sensor computing systems employing memristors face challenges in optimizing energy efficiency and streamlining manufacturing due to the necessity for multiple physical processing components. Here, we introduce low-power organic optoelectronic memristors with synergistic optical and mV-level electrical tunable operation for a dynamic “control-on-demand” architecture. Integrating signal sensing, featuring, and processing within the same memristors enables the realization of each in-sensor analogue reservoir computing module, and minimizes circuit integration complexity. The system achieves 97.15% fingerprint recognition accuracy while maintaining a minimal reservoir size and ultra-low energy consumption. Furthermore, we leverage wafer-scale solution techniques and flexible substrates for optimal memristor fabrication. By centralizing core functionalities on the same in-sensor platform, we propose a resilient and adaptable framework for energy-efficient and economical edge computing.

Optics↗

NASA NTRS1992

Piezoresistive stress sensors on (110) silicon wafers

Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

Kang, Y. L.↗

NASA NTRS1972

Coaxial Inverted Geometry Epitaxial Transistor

Silicon transistor, developed for use in biotelemetry circuits, provides high current gain at low levels of power and voltage. Device operates from biopotential or miniature batteries and is suitable for incorporation into monolithic integrated circuits. Coaxial configuration and small size offer promise for high frequency application.

Hruby, R. J.↗

DOE OSTI2023

Prospects and applications of on-chip lasers

Abstract Integrated silicon photonics has sparked a significant ramp-up of investment in both academia and industry as a scalable, power-efficient, and eco-friendly solution. At the heart of this platform is the light source, which in itself, has been the focus of research and development extensively. This paper sheds light and conveys our perspective on the current state-of-the-art in different aspects of application-driven on-chip silicon lasers. We tackle this from two perspectives: device-level and system-wide points of view. In the former, the different routes taken in integrating on-chip lasers are explored from different material systems to the chosen integration methodologies. Then, the discussion focus is shifted towards system-wide applications that show great prospects in incorporating photonic integrated circuits (PIC) with on-chip lasers and active devices, namely, optical communications and interconnects, optical phased array-based LiDAR, sensors for chemical and biological analysis, integrated quantum technologies, and finally, optical computing. By leveraging the myriad inherent attractive features of integrated silicon photonics, this paper aims to inspire further development in incorporating PICs with on-chip lasers in, but not limited to, these applications for substantial performance gains, green solutions, and mass production.

Zhou, Zhican↗

NASA NTRS1974

Input-output, expandable-parity network

Large-scale integrated circuit generates and checks parity of four eight-bit registers. In addition, circuit will indicate by output signal whether parity error exists. Circuit can also generate or check parity of words up to 32 bits. This is done by making appropriate internal wiring connections on the large-scale integrated chip.

Mckevitt, J. F., III↗

NASA NTRS1980

The SPS interference problem-electronic system effects and mitigation techniques

The potential for interference between solar power satellites (SPS) and other Earth satellite operations was examined along with interference problems involving specific electronic devices. Conclusions indicate that interference is likely in the 2500 MHz to 2690 MHz direct broadcast satellite band adjacent to SPS. Estimates of the adjacent channel noise from SPS in this band are as high as -124 dBc/4 kHz and -100 dBc/MHz, where dBc represents decibels relative to the total power in the fundamental. A second potential problem is the 7350 MHz, 3d harmonic from SPS that falls within the 7300 MHz to 7450 MHz space to Earth, government, satellite assignment. Catastrophic failures can be produced in integrated circuits when the microwave power levels coupled into inputs and power leads reach 1 to 100 watts. The failures are typically due to bonding wire melting, metallization failures, and junction shorting. Nondestructive interaction or interference, however, generally occurs with coupled power levels of the order of 10 milliwatts. This integration is due to the rectification of microwave energy by the numerous pn junctions within these circuits.

Juroshek, J. R.↗

NASA NTRS2000

Technical Challenges in Reliable Microelectronics Packaging of Microelectromechanical Systems (MEMS) for Space Applications

MEMS have shown a significant promise in the last decade for a variety of applications such as air-bag, pressure sensors, accelerometer, microgyro, chemical sensors, artificial nose, etc. Standard semiconductor microelectronics packaging needs the integrated circuits (IC) to be protected from the harsh environment, and provide electrical communication with the other parts of the circuit, facilitate thermal dissipation efficiently, and impart mechanical strength to the silicon die. Microelectronics packaging involves wafer dicing, bonding, lead attachment, encapsulation to protect from the environment, electrical integrity, and package leak tests to assure the reliable IC packaging technology. Active elements or microstructures in MEMS devices often interfaces with the hostile environment where packaging leak tests and testing of such devices using chemical and mechanical parameters will be very difficult and expensive. Packaging of MEMS is significantly complex as they serve to protect from the environment and microstructures interact with the same environment to measure or affect the desired physical or chemical parameters. The most of the silicon circuitry is sensitive to temperature, moisture, magnetic field, light, and electromagnetic interference. The package must then protect the on-board silicon circuitry while simultaneously exposing the microsensor to the effect it measures to assure the packaging technology of MEMS. MEMS technology has a major application in developing a microspacecraft for space systems provided reliability of MEMS packaging technology is sufficiently addressed. This MEMS technology would eventually miniaturize many of the components of the spacecraft to reach the NASA's goal by building faster, cheaper, better, smaller spacecraft to explore the space more effectively. This paper discusses the latest developments in the MEMS technology and challenging technical issues in the packaging of hermetically sealed and non-hermetically sealed MEMS sensor devices for microspacecraft applications.

Ramesham, Rajeshuni↗

NASA NTRS2000

Assessment and Assurance of Microelectronics Packaging Technology of Microelectromechanical Systems (MEMS)

Microelectromechanical systems (MEMS) have shown a significant promise in the last decade for a variety of applications such as air-bag, pressure sensors, accelerometer, microgyro, etc. Standard semiconductor microelectronics packaging needs the integrated circuits to be protected from the harsh environment, and provide electrical communication with the other parts of the circuit, facilitate thermal dissipation efficiently, and impart mechanical strength to the silicon die. Microelectronics packaging involves wafer dicing, bonding, lead attachment, encapsulation to protect from the environment, electrical integrity, and package leak tests to assure the packaging technology. In the case of MEMS the microstructures (active elements) often interfaces with the hostile environment where packaging leak tests and testing of such devices using chemical and mechanical parameters will be very difficult and expensive. Packaging of MEMS is significantly complex as they serve to protect from the environment and microstructures interact with the same environment to measure or affect the desired physical or chemical parameters. The most of the silicon circuitry is sensitive to temperature, moisture, magnetic field, light, and electromagnetic interference. The package must then protect the on-board silicon circuitry while simultaneously exposing the microsensor to the effect it 'measures to assure the MEMS technology by lowering the risk to zero. MEMS technology has a major application in developing a microspacecraft for space systems provided assurance of MEMS technology is sufficiently addressed nondestructively. This technology would eventually miniaturize many of the components of the spacecraft to reach the NASA's safety and mission assurance goal by building faster, cheaper, better, smaller spacecraft to explore the space more effectively by teaming-up with the other NASA centers using the limited resources available. This paper discusses the latest developments in the MEMS technology and challenging issues in the packaging of hermetically sealed and non-hermetically sealed MEMS sensor devices based on silicon, poly-silicon, and other materials for microspacecraft applications considering the space environment and reliability assurance qualification guidelines in perspective. Acknowledgments: The above research work is supported by the NASA Electronics Parts and Packaging Program (NEPP) and performed by the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA under a contract with the NASA - Code Q for the Office of Safety and Mission Assurance Program 323-79.

Ramesham, Rajeshuni↗