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All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

How far away is plug 'n' play? Assessing the near-term potential of sonification and auditory display

The commercial music industry offers a broad range of plug 'n' play hardware and software scaled to music professionals and scaled to a broad consumer market. The principles of sound synthesis utilized in these products are relevant to application in virtual environments (VE). However, the closed architectures used in commercial music synthesizers are prohibitive to low-level control during real-time rendering, and the algorithms and sounds themselves are not standardized from product to product. To bring sound into VE requires a new generation of open architectures designed for human-controlled performance from interfaces embedded in immersive environments. This presentation addresses the state of the sonic arts in scientific computing and VE, analyzes research challenges facing sound computation, and offers suggestions regarding tools we might expect to become available during the next few years. A list of classes of audio functionality in VE includes sonification -- the use of sound to represent data from numerical models; 3D auditory display (spatialization and localization, also called externalization); navigation cues for positional orientation and for finding items or regions inside large spaces; voice recognition for controlling the computer; external communications between users in different spaces; and feedback to the user concerning his own actions or the state of the application interface. To effectively convey this considerable variety of signals, we apply principles of acoustic design to ensure the messages are neither confusing nor competing. We approach the design of auditory experience through a comprehensive structure for messages, and message interplay we refer to as an Automated Sound Environment. Our research addresses real-time sound synthesis, real-time signal processing and localization, interactive control of high-dimensional systems, and synchronization of sound and graphics.

Bargar, Robin↗
NASA NTRS2004

Development of a Crosslink Channel Simulator

Distributed Spacecraft missions are an integral part of current and future plans for NASA and other space agencies. Many of these multi-vehicle missions involve utilizing the array of spacecraft as a single, instrument requiring communication via crosslinks to achieve mission goals. NASA s Goddard Space Flight Center (GSFC) is developing the Formation Flying Test Bed (FFTB) to provide a hardware-in-the-loop simulation environment to support mission concept development and system trades with a primary focus on Guidance, Navigation, and Control (GN&C) challenges associated with spacecraft flying. The goal of the FFTB is to reduce mission risk by assisting in mission planning and analysis, provide a technology development platform that allows algorithms to be developed for mission functions such as precision formation navigation and control and time synchronization. The FFTB will provide a medium in which the various crosslink transponders being used in multi-vehicle missions can be integrated for development and test; an integral part of the FFTB is the Crosslink Channel Simulator (CCS). The CCS is placed into the communications channel between the crosslinks under test, and is used to simulate on-mission effects to the communications channel such as vehicle maneuvers, relative vehicle motion, or antenna misalignment. The CCS is based on the Starlight software programmable platform developed at General Dynamics Decision Systems and provides the CCS with the ability to be modified on the fly to adapt to new crosslink formats or mission parameters. This paper briefly describes the Formation Flying Test Bed and its potential uses. It then provides details on the current and future development of the Crosslink Channel Simulator and its capabilities.

Hunt, Chris↗
NASA NTRS2005

Reconfiguration of Analog Electronics for Extreme Environments: Problem or Solution?

This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). In addition to hardening-by-process and hardening-by-design, "hardening-by-reconfiguration", when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive self-reconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Partly degraded resources are still used, while completely damaged resources are bypassed. Designs suitable for various environmental conditions can be determined prior to operation or can be determined in-situ, by adaptive reconfiguration algorithms running on built-in digital controllers. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfigurable devices were exposed to, and degraded by, low temperatures (approx. 196 C), high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms. Taking this technology from Technology Readiness Level (TRL) 3 to TRL 5 is the target of a current NASA project.

Field Programmable Transistor Array (FPTA)↗
NASA NTRS1981

Conceptual design for a universal Reed-Solomon decoder

An algorithm which enables one Reed-Solomon decoder to process other Reed-Solomon encoded data from a different code is presented. The sole requirement is that both codes have the same length, the same rate, and the same field of coefficients. It is pointed out that only very simple pre- and post-processing hardware is needed to resolve an encoder/decoder incompatibility and that no encoder modification is needed.

Miller, R. L.↗
NASA NTRS1987

Flight test of a digital controller used in a helicopter autoland system

This paper describes the flight test evaluation of an advanced digital helicopter flight control system. The controller was designed using an optimal control design procedure for a fully coupled lateral and longitudinal vehicle model. Explicit integrals of the guidance error were included to produce a type 1 characteristic. Gain scheduling was used to account for changes in the vehicle dynamics. The digital controller was exercised by combining it with state estimators, a trajectory generator, and a closed-loop guidance algorithm to form a helicopter autoland system. A CH-47 tandem rotor helicopter was equipped with sensors, on-board digital flight computers, and electrohydraulic actuators. The system was exercised by automatically flying straight-in descending decelerating trajectories typcial of VFR manual landing approaches. A description of the test-ground facilities, the flight hardware and software, and the velocity and position tracking performance is included.

Downing, David R.↗
NASA NTRS1991

MDO can help resolve the designer's dilemma

Multidisciplinary design optimization (MDO) is presented as a rapidly growing body of methods, algorithms, and techniques that will provide a quantum jump in the effectiveness and efficiency of the quantitative side of design, and will turn that side into an environment in which the qualitative side can thrive. MDO borrows from CAD/CAM for graphic visualization of geometrical and numerical data, data base technology, and in computer software and hardware. Expected benefits from this methodology are a rational, mathematically consistent approach to hypersonic aircraft designs, designs pushed closer to the optimum, and a design process either shortened or leaving time available for different concepts to be explored.

Sobieszczanski-Sobieski, Jaroslaw↗
NASA NTRS1990

Self arbitrated VLSI asynchronous sequential circuits

A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

Whitaker, S.↗
NASA NTRS2001

Traveling-Wave Tube Amplifier Model to Predict High-Order Modulation Intersymbol Interference

Demands for increased data rates in satellite communications necessitate higher order modulation schemes, larger system bandwidth, and minimum distortion of the modulated signal as it is passed through the traveling wave tube amplifier (TWTA). One type of distortion that the TWTA contributes to is intersymbol interference (ISI), and this becomes particularly disruptive with wide-band, complex modulation schemes. It is suspected that in addition to the dispersion of the TWT, frequency dependent reflections due to mismatches within the TWT are a significant contributor to ISI. To experimentally investigate the effect of these mismatches within the physical TWT on ISI would be prohibitively expensive, as it would require manufacturing numerous amplifiers in addition to the acquisition of the required digital hardware. In an attempt to develop a more accurate model to correlate IS1 with the TWTA and the operational signal, a fully three-dimensional (3D), time-dependent, TWT interaction model has been developed using the electromagnetic particle-in-cell (PIC) code MAFIA (solution of Maxwell's equations by the Finite-Integration-Algorithm). The model includes a user defined slow-wave circuit with a spatially tapered region of loss to implement a sever, and spatially varied geometry (such as helical pitch) to implement a phase velocity taper. The model also includes user defined input/output coupling and an electron beam contained by solenoidal, electrostatic, or periodic permanent magnet (PPM) focusing allowing standard or novel TWTs to be investigated. This model comprehensively takes into account the effects of frequency dependent nonlinear distortions (MAM and AMPM); gain ripple due to frequency dependent reflections at the input/output coupling, severs, and mismatches from dynamic pitch variations; drive induced oscillations; harmonic generation; intermodulation products; and backward waves.

Kory, Carol L.↗
NASA NTRS2007

Protecting Against Faults in JPL Spacecraft

A paper discusses techniques for protecting against faults in spacecraft designed and operated by NASA s Jet Propulsion Laboratory (JPL). The paper addresses, more specifically, fault-protection requirements and techniques common to most JPL spacecraft (in contradistinction to unique, mission specific techniques), standard practices in the implementation of these techniques, and fault-protection software architectures. Common requirements include those to protect onboard command, data-processing, and control computers; protect against loss of Earth/spacecraft radio communication; maintain safe temperatures; and recover from power overloads. The paper describes fault-protection techniques as part of a fault-management strategy that also includes functional redundancy, redundant hardware, and autonomous monitoring of (1) the operational and health statuses of spacecraft components, (2) temperatures inside and outside the spacecraft, and (3) allocation of power. The strategy also provides for preprogrammed automated responses to anomalous conditions. In addition, the software running in almost every JPL spacecraft incorporates a general-purpose "Safe Mode" response algorithm that configures the spacecraft in a lower-power state that is safe and predictable, thereby facilitating diagnosis of more complex faults by a team of human experts on Earth.

Morgan, Paula↗
NASA NTRS2021

A High Dynamic-Range Photon-Counting Receiver for Deep Space Optical Communication

The Deep Space Optical Communication (DSOC) project will demonstrate free-space optical communication at almost 3 AU, or 3 orders of magnitude further than any previous attempt. DSOC will utilize the 5m Palomar Hale Telescope to receive the downlink signal, which will couple the downlink light onto an optical table and into a superconducting nanowire single photon detector (SNSPD). The output of the SNSPD is digitized by the Ground Laser Receiver Signal Processing Assembly (GSPA) using a high throughput streaming time to digital converter (TDC). The GSPA is a scalable FPGA-based receiver which demodulates and decodes the DSOC downlink signal through novel signal processing algorithms implemented on Xilinx UltraScale+ FPGAs, as well as Python-based software monitor and control routines. Exploiting the unique TDC-based architecture, the GSPA supports over four orders of magnitude of downlink data rates across multiple orders of magnitude of signal and background powers. In this paper we present an overview of the hardware, firmware and software architectures to implement this system, as well as performance analysis for links ranging from near-Earth to 2.8 AU.

Srinivasan, Meera↗
NASA NTRSDate not supplied

Automated Addressing Failure Detection for Multiplexer Systems

Multiplexers are electronic devices which select between several input signals and deliver an output signal. Also known as data selectors or mux, multiplexers are commonly used in circuit design to provide signal switching, simplify hardware and manufacturing, and decrease cost. Systems which use a digital mux as a switch or selector are vulnerable to events called addressing failures, arising in hardware or software. An addressing failure results in the system requesting, or the mux delivering, a data signal other than the one intended. The unintended use of this erroneous signal may lead to system-level failures. This paper discusses a novel method of automatic detection for addressing failures, utilizing multiplexer channelization and a monitoring algorithm.

multiplexer↗
NASA NTRS1974

An improved version of the table look-up algorithm for pattern recognition

The table look-up approach to pattern recognition has been used for 3 years at several research centers in a variety of applications. A new version has been developed which is faster, requires significantly less core memory, and retains full precision of the input data. The new version can be used on low-cost minicomputers having 32K words (16 bits each) of core memory and fixed-point arithmetic; no special-purpose hardware is required. An initial FORTRAN version of this system can classify an ERTS computer-compatible tape into 24 classes in less than 15 minutes.

Eppler, W. G.↗
NASA NTRSDate not supplied

Impact of Emerging Computing Architectures and Opportunities for Process Systems Engineering Applications

Moore’s “law” was the observation that the number of transistors in an integrated circuit doubled approximately every two years. This trend has distinctly failed to hold in recent years. The death of Moore’s law has left researchers and practitioners in the computational sciences searching for technologies to provide the speedups formerly supported by Moore’s law. Previously overlooked chip architectures and other computing technologies are now receiving more development resources. Critically, these technologies are gaining more mature software support, opening their adoption by researchers in algorithms and applications. In this article, we review some of these computing technologies, their relationship with various algorithms and applications, and their potential benefits (or pitfalls). We close with recommendations for future work by the process systems engineering community specifically.

Emerging hardware↗
NASA NTRS1981

Potential of dual-measurement techniques for accurate determination of instantaneous rainfall rate from space

The incorporation in the 13.5 GHz SEASAT type radar altimeter of a mode to measure rain rate is investigated. Specifically, an algorithm is developed relating the echo power at the various range bins to the rain rate, taking into consideration Mie scattering and path attenuation. The dependence of the algorithm on rain drop size distribution, and non-uniform rain structure are examined and associated uncertainties defined. A technique for obtaining drop size distribution through the measurements of power at the top of the raincell and power difference through the cell is also investigated together with an associated error analysis. A description of the minor hardware modifications to the basic SEASAT design is given for implementing the rain measurements.

Ulbrich, C. W.↗
NASA NTRS1983

Power subsystem automation study

Generic power-system elements and their potential faults are identified. Automation functions and their resulting benefits are defined and automation functions between power subsystem, central spacecraft computer, and ground flight-support personnel are partitioned. All automation activities were categorized as data handling, monitoring, routine control, fault handling, planning and operations, or anomaly handling. Incorporation of all these classes of tasks, except for anomaly handling, in power subsystem hardware and software was concluded to be mandatory to meet the design and operational requirements of the space station. The key drivers are long mission lifetime, modular growth, high-performance flexibility, a need to accommodate different electrical user-load equipment, onorbit assembly/maintenance/servicing, and potentially large number of power subsystem components. A significant effort in algorithm development and validation is essential in meeting the 1987 technology readiness date for the space station.

Imamura, M. S.↗
NASA NTRS1984

Spatial information technologies for remote sensing today and tomorrow; Proceedings of the Ninth Pecora Symposium, Sioux Falls, SD, October 2-4, 1984

Topics discussed at the symposium include hardware, geographic information system (GIS) implementation, processing remotely sensed data, spatial data structures, and NASA programs in remote sensing information systems. Attention is also given GIS applications, advanced techniques, artificial intelligence, graphics, spatial navigation, and classification. Papers are included on the design of computer software for geographic image processing, concepts for a global resource information system, algorithm development for spatial operators, and an application of expert systems technology to remotely sensed image analysis.

Source record↗
NASA NTRS1991

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 2: Formal specification and correctness theorems

Presented here is a formal specification and verification of a property of a quadruplicately redundant fault tolerant microprocessor system design. A complete listing of the formal specification of the system and the correctness theorems that are proved are given. The system performs the task of obtaining interactive consistency among the processors using a special instruction on the processors. The design is based on an algorithm proposed by Pease, Shostak, and Lamport. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, providing certain preconditions hold, using a computer aided design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

Bickford, Mark↗