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The Impact on Space Radiation Requirements and Effects on ASIMS

The evolution of highly miniaturized electronic and mechanical systems will be accompanied by new problems and issues regarding the radiation response of these systems in the space environment. In this paper we discuss some of the more prominent radiation problems brought about by miniaturization. For example, autonomous micro-spacecraft will require large amounts of high density memory, most likely in the form of stacked, multichip modules of DRAM's, that must tolerate the radiation environment. However, advanced DRAM's (16 to 256 Mbit) are quite susceptible to radiation, particularly single event effects, and even exhibit new radiation phenomena that were not a problem for older, less dense memory chips. Another important trend in micro-spacecraft electronics is toward the use of low-voltage microelectronic systems that consume less power. However, the reduction in operating voltage also caries with it an increased susceptibility to radiation. In the case of application specific integrated microcircuits (ASIM's), advanced devices of this type, such as high density field programmable gate arrays (FPGA's) exhibit new single event effects (SEE), such as single particle reprogramming of anti-fuse links. New advanced bipolar circuits have been shown recently to degrade more rapidly in the low dose rate space environment than in the typical laboratory total dose radiation test used to qualify such devices. Thus total dose testing of these parts is no longer an appropriately conservative measure to be used for hardness assurance. We also note that the functionality of micromechanical Si-based devices may be altered due to the radiation-induced deposition of charge in the oxide passivation layers.

Barnes, C.↗

Plasma membrane ordering agent pluronic F-68 (PF-68) reduces neurotransmitter uptake and release and produces learning and memory deficits in rats

A substantial body of evidence indicates that aged-related changes in the fluidity and lipid composition of the plasma membrane contribute to cellular dysfunction in humans and other mammalian species. In the CNS, reductions in neuronal plasma membrane order (PMO) (i.e., increased plasma membrane fluidity) have been attributed to age as well as the presence of the beta-amyloid peptide-25-35, known to play an important role in the neuropathology of Alzheimer's disease (AD). These PMO increases may influence neurotransmitter synthesis, receptor binding, and second messenger systems as well as signal transduction pathways. The effects of neuronal PMO on learning and memory processes have not been adequately investigated, however. Based on the hypothesis that an increase in PMO may alter a number of aspects of synaptic transmission, we investigated several neurochemical and behavioral effects of the membrane ordering agent, PF-68. In cell culture, PF-68 (nmoles/mg SDS extractable protein) reduced [3H]norepinephrine (NE) uptake into differentiated PC-12 cells as well as reduced nicotine stimulated [3H]NE release. The compound (800-2400 microg/kg, i.p., resulting in nmoles/mg SDS extractable protein in the brain) decreased step-through latencies and increased the frequencies of crossing into the unsafe side of the chamber in inhibitory avoidance training. In the Morris water maze, PF-68 increased the latencies and swim distances required to locate a hidden platform and reduced the time spent and distance swam in the previous target quadrant during transfer (probe) trials. PF-68 did not impair performance of a well-learned working memory task, the rat delayed stimulus discrimination task (DSDT), however. Studies with 14C-labeled PF-68 indicated that significant (pmoles/mg wet tissue) levels of the compound entered the brain from peripheral (i.p.) injection. No PF-68 related changes were observed in swim speeds or in visual acuity tests in water maze experiments, rotorod performance, or in tests of general locomotor activity. Furthermore, latencies to select a lever in the DSDT were not affected. These results suggest that PF-68 induced deficits in learning and memory without confounding peripheral motor, sensory, or motivational effects at the tested doses. Furthermore, none of the doses induced a conditioned taste aversion to a novel 0.1% saccharin solution indicating a lack of nausea or gastrointestinal malaise induced by the compound. The data indicate that increases in neuronal plasma membrane order may have significant effects on neurotransmitter function as well as learning and memory processes. Furthermore, compounds such as PF-68 may also offer novel tools for studying the role of neuronal PMO in mnemonic processes and changes in PMO resulting from age-related disorders such as AD.

Poloxamer/pharmacology↗

Initial operating capability for the hypercluster parallel-processing test bed

The NASA Lewis Research Center is investigating the benefits of parallel processing to applications in computational fluid and structural mechanics. To aid this investigation, NASA Lewis is developing the Hypercluster, a multi-architecture, parallel-processing test bed. The initial operating capability (IOC) being developed for the Hypercluster is described. The IOC will provide a user with a programming/operating environment that is interactive, responsive, and easy to use. The IOC effort includes the development of the Hypercluster Operating System (HYCLOPS). HYCLOPS runs in conjunction with a vendor-supplied disk operating system on a Front-End Processor (FEP) to provide interactive, run-time operations such as program loading, execution, memory editing, and data retrieval. Run-time libraries, that augment the FEP FORTRAN libraries, are being developed to support parallel and vector processing on the Hypercluster. Special utilities are being provided to enable passage of information about application programs and their mapping to the operating system. Communications between the FEP and the Hypercluster are being handled by dedicated processors, each running a Message-Passing Kernel, (MPK). A shared-memory interface allows rapid data exchange between HYCLOPS and the communications processors. Input/output handlers are built into the HYCLOPS-MPK interface, eliminating the need for the user to supply separate I/O support programs on the FEP.

Cole, Gary L.↗

Sptrace

Sptrace is a general-purpose space utilization tracing system that is conceptually similar to the commercial Purify product used to detect leaks and other memory usage errors. It is designed to monitor space utilization in any sort of heap, i.e., a region of data storage on some device (nominally memory; possibly shared and possibly persistent) with a flat address space. This software can trace usage of shared and/or non-volatile storage in addition to private RAM (random access memory). Sptrace is implemented as a set of C function calls that are invoked from within the software that is being examined. The function calls fall into two broad classes: (1) functions that are embedded within the heap management software [e.g., JPL's SDR (Simple Data Recorder) and PSM (Personal Space Management) systems] to enable heap usage analysis by populating a virtual time-sequenced log of usage activity, and (2) reporting functions that are embedded within the application program whose behavior is suspect. For ease of use, these functions may be wrapped privately inside public functions offered by the heap management software. Sptrace can be used for VxWorks or RTEMS realtime systems as easily as for Linux or OS/X systems.

Burleigh, Scott C.↗

Centering a DDR Strobe in the Middle of a Data Packet

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Johnson, Michael↗

High-performance mass storage system for workstations

Reduced Instruction Set Computer (RISC) workstations and Personnel Computers (PC) are very popular tools for office automation, command and control, scientific analysis, database management, and many other applications. However, when using Input/Output (I/O) intensive applications, the RISC workstations and PC's are often overburdened with the tasks of collecting, staging, storing, and distributing data. Also, by using standard high-performance peripherals and storage devices, the I/O function can still be a common bottleneck process. Therefore, the high-performance mass storage system, developed by Loral AeroSys' Independent Research and Development (IR&D) engineers, can offload a RISC workstation of I/O related functions and provide high-performance I/O functions and external interfaces. The high-performance mass storage system has the capabilities to ingest high-speed real-time data, perform signal or image processing, and stage, archive, and distribute the data. This mass storage system uses a hierarchical storage structure, thus reducing the total data storage cost, while maintaining high-I/O performance. The high-performance mass storage system is a network of low-cost parallel processors and storage devices. The nodes in the network have special I/O functions such as: SCSI controller, Ethernet controller, gateway controller, RS232 controller, IEEE488 controller, and digital/analog converter. The nodes are interconnected through high-speed direct memory access links to form a network. The topology of the network is easily reconfigurable to maximize system throughput for various applications. This high-performance mass storage system takes advantage of a 'busless' architecture for maximum expandability. The mass storage system consists of magnetic disks, a WORM optical disk jukebox, and an 8mm helical scan tape to form a hierarchical storage structure. Commonly used files are kept in the magnetic disk for fast retrieval. The optical disks are used as archive media, and the tapes are used as backup media. The storage system is managed by the IEEE mass storage reference model-based UniTree software package. UniTree software will keep track of all files in the system, will automatically migrate the lesser used files to archive media, and will stage the files when needed by the system. The user can access the files without knowledge of their physical location. The high-performance mass storage system developed by Loral AeroSys will significantly boost the system I/O performance and reduce the overall data storage cost. This storage system provides a highly flexible and cost-effective architecture for a variety of applications (e.g., realtime data acquisition with a signal and image processing requirement, long-term data archiving and distribution, and image analysis and enhancement).

Chiang, T.↗

Radiation Tolerant Intelligent Memory Stack (RTIMS)

The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

Ng, Tak-kwong↗

Commutated automatic gain control system

The commutated automatic gain control (AGC) system was designed and built for the prototype Loran-C receiver is discussed. The current version of the prototype receiver, the Mini L-80, was tested initially in 1980. The receiver uses a super jolt microcomputer to control a memory aided phase loop (MAPLL). The microcomputer also controls the input/output, latitude/longitude conversion, and the recently added AGC system. The AGC control adjusts the level of each station signal, such that the early portion of each envelope rise is about at the same amplitude in the receiver envelope detector.

Yost, S. R.↗

Distributed Saturation

The Saturation algorithm for symbolic state-space generation, has been a recent break-through in the exhaustive veri cation of complex systems, in particular globally-asyn- chronous/locally-synchronous systems. The algorithm uses a very compact Multiway Decision Diagram (MDD) encoding for states and the fastest symbolic exploration algo- rithm to date. The distributed version of Saturation uses the overall memory available on a network of workstations (NOW) to efficiently spread the memory load during the highly irregular exploration. A crucial factor in limiting the memory consumption during the symbolic state-space generation is the ability to perform garbage collection to free up the memory occupied by dead nodes. However, garbage collection over a NOW requires a nontrivial communication overhead. In addition, operation cache policies become critical while analyzing large-scale systems using the symbolic approach. In this technical report, we develop a garbage collection scheme and several operation cache policies to help on solving extremely complex systems. Experiments show that our schemes improve the performance of the original distributed implementation, SmArTNow, in terms of time and memory efficiency.

Chung, Ming-Ying↗

VISCEL: A general-purpose computer program for analysis of linear viscoelastic structures (user's manual), volume 1

This program, an extension of the linear equilibrium problem solver ELAS, is an updated and extended version of its earlier form (written in FORTRAN 2 for the IBM 7094 computer). A synchronized material property concept utilizing incremental time steps and the finite element matrix displacement approach has been adopted for the current analysis. A special option enables employment of constant time steps in the logarithmic scale, thereby reducing computational efforts resulting from accumulative material memory effects. A wide variety of structures with elastic or viscoelastic material properties can be analyzed by VISCEL. The program is written in FORTRAN 5 language for the Univac 1108 computer operating under the EXEC 8 system. Dynamic storage allocation is automatically effected by the program, and the user may request up to 195K core memory in a 260K Univac 1108/EXEC 8 machine. The physical program VISCEL, consisting of about 7200 instructions, has four distinct links (segments), and the compiled program occupies a maximum of about 11700 words decimal of core storage.

Gupta, K. K.↗

Two memories for geographical slant: separation and interdependence of action and awareness

The present study extended previous findings of geographical slant perception, in which verbal judgments of the incline of hills were greatly overestimated but motoric (haptic) adjustments were much more accurate. In judging slant from memory following a brief or extended time delay, subjects' verbal judgments were greater than those given when viewing hills. Motoric estimates differed depending on the length of the delay and place of response. With a short delay, motoric adjustments made in the proximity of the hill did not differ from those evoked during perception. When given a longer delay or when taken away from the hill, subjects' motoric responses increased along with the increase in verbal reports. These results suggest two different memorial influences on action. With a short delay at the hill, memory for visual guidance is separate from the explicit memory informing the conscious response. With short or long delays away from the hill, short-term visual guidance memory no longer persists, and both motor and verbal responses are driven by an explicit representation. These results support recent research involving visual guidance from memory, where actions become influenced by conscious awareness, and provide evidence for communication between the "what" and "how" visual processing systems.

NASA Discipline Space Human Factors↗

Planning Coverage Campaigns for Mission Design and Analysis: Clasp for the Proposed DESDynI Mission

Mission design and analysis present challenges in that almost all variables are in constant flux, yet the goal is to achieve an acceptable level of performance against a concept of operations, which might also be in flux. To increase responsiveness, our approach is to use automated planning tools that allow for the continual modification of spacecraft, ground system, staffing, and concept of operations while returning metrics that are important to mission evaluation, such as area covered, peak memory usage, and peak data throughput. We have applied this approach to DESDynI (Deformation, Ecosystem Structure, and Dynamics of Ice) mission design concept using the CLASP (Compressed Large-scale Activity Scheduler/Planner) planning system [7], but since this adaptation many techniques have changed under the hood for CLASP and the DESDynI mission concept has undergone drastic changes, including that it has been renamed the Earth Radar Mission. Over the past two years, we have run more than fifty simulations with the CLASP-DESDynI adaptation, simulating different mission scenarios with changing parameters including targets, swaths, instrument modes, and data and downlink rates. We describe the evolution of simulations through the DESDynI MCR (Mission Concept Review) and afterwards.

DESDynI (Deformation, Ecosystem Structure, and Dyn↗

Pultrusion Process for Fabrication of Tethers (preliminary Concepts)

Three composite materials were manufactured by the pultrusion process, coiled on 24 inch diameter spools for a period of two months, uncoiled and evaluated for memory recall. These materials were pultruded to lengths of approximately 150 feet and cross section profiles were maintained at 0.143 inch in thickness by 0.566 inch in width. Mechanical properties were studied and results compared. The reinforcement material volume percent of each was identical. Of the three systems, the Kevlar reinforced composite had the highest specific strength, the lowest flexural modulus, and the lowest memory recall. Further evaluations of materials and fabrication technology of pultrusion should be conducted to address some problem areas encountered in this preliminary concept. Areas for further study are suggested.

Macconochie, I. O.↗

Optical Firmware

Data-processing system exploits high speeds inherent in optical elements. Instruction sets for different computer operations reside on different external memory chips. Laser diodes activated for each operation generate light, reflected by holographic optical element to designated receptors in arithmetic and logic unit. Pattern of light beams embodies instruction set at given instant. With potential ability to reprogram in real time, conceptual system applicable to task-driven programming or artificial intelligence.

Bergman, Larry A.↗

Shape memory-based actuators and release mechanisms therefrom

SM-based actuators (110) and release mechanisms (100) therefrom and systems (500) including one or more release mechanisms (100). The actuators (110) comprise a SM member (118) and a deformable member (140) mechanically coupled to the SM member (118) which deforms upon a shape change of the SM member triggered by a phase transition of the SM member. A retaining element (160) is mechanically coupled to the deformable member (140), wherein the retaining element (160) moves upon the shape change. Release mechanism (100) include an actuator, a rotatable mechanism (120) including at least one restraining feature (178) for restraining rotational movement of the retaining element (160) before the shape change, and at least one spring (315) that provides at least one locked spring-loaded position when the retaining element is in the restraining feature and at least one released position that is reached when the retaining element is in a position beyond the restraining feature (178). The rotatable mechanism (120) includes at least one load-bearing protrusion (310). A hitch (400) is for mechanically coupling to the load, wherein the hitch is supported on the load bearing protrusion (310) when the rotatable mechanism is in the locked spring-loaded position.

Vaidyanathan, Rajan↗

The scheme machine: A case study in progress in design derivation at system levels

The Scheme Machine is one of several design projects of the Digital Design Derivation group at Indiana University. It differs from the other projects in its focus on issues of system design and its connection to surrounding research in programming language semantics, compiler construction, and programming methodology underway at Indiana and elsewhere. The genesis of the project dates to the early 1980's, when digital design derivation research branched from the surrounding research effort in programming languages. Both branches have continued to develop in parallel, with this particular project serving as a bridge. However, by 1990 there remained little real interaction between the branches and recently we have undertaken to reintegrate them. On the software side, researchers have refined a mathematically rigorous (but not mechanized) treatment starting with the fully abstract semantic definition of Scheme and resulting in an efficient implementation consisting of a compiler and virtual machine model, the latter typically realized with a general purpose microprocessor. The derivation includes a number of sophisticated factorizations and representations and is also deep example of the underlying engineering methodology. The hardware research has created a mechanized algebra supporting the tedious and massive transformations often seen at lower levels of design. This work has progressed to the point that large scale devices, such as processors, can be derived from first-order finite state machine specifications. This is roughly where the language oriented research stops; thus, together, the two efforts establish a thread from the highest levels of abstract specification to detailed digital implementation. The Scheme Machine project challenges hardware derivation research in several ways, although the individual components of the system are of a similar scale to those we have worked with before. The machine has a custom dual-ported memory to support garbage collection. It consists of four tightly coupled processes--processor, collector, allocator, memory--with a very non-trivial synchronization relationship. Finally, there are deep issues of representation for the run-time objects of a symbolic processing language. The research centers on verification through integrated formal reasoning systems, but is also involved with modeling and prototyping environments. Since the derivation algebra is basd on an executable modeling language, there is opportunity to incorporate design animation in the design process. We are looking for ways to move smoothly and incrementally from executable specifications into hardware realization. For example, we can run the garbage collector specification, a Scheme program, directly against the physical memory prototype, and similarly, the instruction processor model against the heap implementation.

Johnson, Steven D.↗

Coordination and establishment of centralized facilities and services for the University of Alaska ERTS survey of the Alaskan environment

The author has identified the following significant results. Specifications have been prepared for the engineering design and construction of a digital color display unit which will be used for automatic processing of ERTS data. The color display unit is a disk refresh memory with computer interfaced input and a color cathode ray tube output display. The system features both analog and digital post disk data manipulation and a versatile color coding device suitable for displaying not only images, but also computer generated graphics such as diagrams, maps, and overlays. Input is from IBM compatible 9 track, 800 BPI tapes, as generated by an IBM 360 computer. ERTS digital tapes are read into the 360, where various analyses such as maximum likelihood classification are performed and the results are written on a magnetic tape which is the input to the color display unit. The greatest versatility in the data manipulation area is provided by the minicomputer built into the color display unit, which is off-line from the main 360 computer. The minicomputer is able to read any line from the refresh disk and place it in its 4K-16 bit memory. Considerable flexibility is available for post-processing enhancement of images by the investigator.

Belon, A. E.↗

Pi-Sat: A Low Cost Small Satellite and Distributed Spacecraft Mission System Test Platform

Current technology and budget trends indicate a shift in satellite architectures from large, expensive single satellite missions, to small, low cost distributed spacecraft missions. At the center of this shift is the SmallSatCubesat architecture. The primary goal of the Pi-Sat project is to create a low cost, and easy to use Distributed Spacecraft Mission (DSM) test bed to facilitate the research and development of next-generation DSM technologies and concepts. This test bed also serves as a realistic software development platform for Small Satellite and Cubesat architectures. The Pi-Sat is based on the popular $35 Raspberry Pi single board computer featuring a 700Mhz ARM processor, 512MB of RAM, a flash memory card, and a wealth of IO options. The Raspberry Pi runs the Linux operating system and can easily run Code 582s Core Flight System flight software architecture. The low cost and high availability of the Raspberry Pi make it an ideal platform for a Distributed Spacecraft Mission and Cubesat software development. The Pi-Sat models currently include a Pi-Sat 1U Cube, a Pi-Sat Wireless Node, and a Pi-Sat Cubesat processor card.The Pi-Sat project takes advantage of many popular trends in the Maker community including low cost electronics, 3d printing, and rapid prototyping in order to provide a realistic platform for flight software testing, training, and technology development. The Pi-Sat has also provided fantastic hands on training opportunities for NASA summer interns and Pathways students.

Software↗