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At least 901 records · Page 50

Electrical control of magnetism by electric field and current-induced torques

The remanent magnetization of ferromagnets has long been studied and used to store binary information. While early magnetic memory designs relied on magnetization switching by locally generated magnetic fields, key insights in condensed matter physics later suggested the possibility of doing it by electrical means instead. In the 1990s, Slonczewski and Berger formulated the concept of current-induced spin torques in magnetic multilayers through which a spin-polarized current generated by a first ferromagnet may be used to switch the magnetization of a second one. This discovery drove the development of spin-transfer-torque magnetic random-access memories (MRAMs). More recent fundamental research revealed other types of current-induced torques named spin-orbit torques (SOTs) and will lead to a new generation of devices including SOT MRAMs and skyrmion-based devices. Parallel to these advances, multiferroics and their magnetoelectric coupling, first investigated experimentally in the 1960s, experienced a renaissance. Dozens of multiferroic compounds with new magnetoelectric coupling mechanisms were discovered and high-quality multiferroic films were synthesized (notably of BiFeO 3 ), also leading to novel device concepts for information and communication technology such as the magnetoelectric spin-orbit (MESO) transistor. The story of the electrical switching of magnetization, which is discussed in this review, is that of a dance between fundamental research (in spintronics, condensed matter physics, and materials science) and technology (MRAMs, MESO transistors, microwave emitters, spin diodes, skyrmion-based devices, components for neuromorphics, etc.). This pas de deux has led to major scientific and technological breakthroughs in recent decades (such as the conceptualization of pure spin currents, the observation of magnetic skyrmions, and the discovery of spin-charge interconversion effects). As a result, this field has not only propelled MRAMs into consumer electronics products but also fueled discoveries in adjacent research areas such as ferroelectrics or magnonics. Here, in this review, recent advances in the control of magnetism by electric fields and by current-induced torques are covered. Fundamental concepts in these two directions are reviewed first, their combination is then discussed, and finally current various families of devices harnessing the electrical control of magnetic properties for various application fields are addressed. The review concludes by giving perspectives in terms of both emerging fundamental physics concepts and new directions in materials science.

36 MATERIALS SCIENCE↗

Polarization rotation in a ferroelectric BaTiO$_3$ film through low-energy He-implantation

Domain engineering in ferroelectric thin films is crucial for next-generation microelectronic and photonic technologies. Here, a method is demonstrated to precisely control domain configurations in BaTiO$_3$ thin films through low-energy He ion implantation. The approach transforms a mixed ferroelectric domain state with significant in-plane polarization into a uniform out-of-plane tetragonal phase by selectively modifying the strain state in the film's top region. This structural transition significantly improves domain homogeneity and reduces polarization imprint, leading to symmetric ferroelectric switching characteristics. The demonstrated ability to manipulate ferroelectric domains post-growth enables tailored functional properties without compromising the coherently strained bottom interface. The method's compatibility with semiconductor processing and ability to selectively modify specific regions make it particularly promising for practical implementation in integrated devices. This work establishes a versatile approach for strain-mediated domain engineering that could be extended to a wide range of ferroelectric systems, providing new opportunities for memory, sensing, and photonic applications where precise control of polarization states is essential.

Luo, Liang [Ames Laboratory (AMES), Ames, IA (Unit↗

Design, processing, and testing of LSI arrays for space station

The development of a low power, high performance MOS 256-bit random assess memory with beam leads is discussed. Beam lead process development on silicon-on-sapphire (SOS) is also discussed, and initial electrical results on beam lead SOS TA5388 devices are presented. A comparison of the beam leaded 256-bit RAM (TA6567) layout is made with the non-beam leaded version (TA6473).

Schneider, W. C.↗

A floating-point/multiple-precision processor for airborne applications

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

Yee, R.↗

Memory-based parallel data output controller

A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.

Stattel, R. J.↗

Optical backplane interconnect switch for data processors and computers

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Hendricks, Herbert D.↗

A report of work activities on the NASA Spacelink public electronic library

NASA Spacelink is a comprehensive electronic data base of NASA and other source educational and informational materials. This service originates at Marshall Space Flight Center (MSFC) in Huntsville, Alabama. This is an education service of NASA Headquarters, through the MSFC Education Office, that first began in February of 1988. The new NASA Spacelink Public Electronic Library was the result of a study conducted to investigate an upgrade or redesign of the original NASA Spacelink. The UNIX Operating System was chosen to be the host operating system for the new NASA Spacelink Public Electronic Library. The UNIX system was selected for this project because of the strengths built into the embedded communication system and for its simple and direct file handling capabilities. The host hardware of the new system is a Sun Microsystems SPARCserver 1000 computer system. The configuration has four 50-MHz SuperSPARC processors with 128 megabytes of shared memory; three SB800 serial ports allowing 24 cable links for phone communications; 4.1 gigabytes of on-line disk storage; and ten (10) CD-ROM drives. Communications devices on the system are sufficient to support the expected number of users through the Internet, the local dial services, long distance dial services; the MSFC PABX, and the NPSS (NASA Packet Switching System) and 1-800 access service for the registered teachers.

Smith, Willard A.↗

IP Protection in TinyML

Tiny machine learning (TinyML) is an essential component of emerging smart microcontrollers (MCUs). How- ever, the protection of the intellectual property (IP) of the model is an increasing concern due to the lack of desktop/server-grade resources on these power-constrained devices. In this paper, we propose STML, a system and algorithm co-design to Secure IP of TinyML on MCUs with ARM TrustZone. Our design jointly optimizes memory utilization and latency while ensuring the security and accuracy of emerging models. We implemented a prototype and benchmarked with 7 models, demonstrating STML reduces 40% of model protection runtime overhead on average.

42 ENGINEERING↗

Distributed out-of-memory NMF on CPU/GPU architectures

We propose an efficient distributed out-of-memory implementation of the non-negative matrix factorization (NMF) algorithm for heterogeneous high-performance-computing systems. The proposed implementation is based on prior work on NMFk, which can perform automatic model selection and extract latent variables and patterns from data. In this work, we extend NMFk by adding support for dense and sparse matrix operation on multi-node, multi-GPU systems. The resulting algorithm is optimized for out-of-memory problems where the memory required to factorize a given matrix is greater than the available GPU memory. Memory complexity is reduced by batching/tiling strategies, and sparse and dense matrix operations are significantly accelerated with GPU cores (or tensor cores when available). Input/output latency associated with batch copies between host and device is hidden using CUDA streams to overlap data transfers and compute asynchronously, and latency associated with collective communications (both intra-node and inter-node) is reduced using optimized NVIDIA Collective Communication Library (NCCL) based communicators. Benchmark results show significant improvement, from 32X to 76x speedup, with the new implementation using GPUs over the CPU-based NMFk. Good weak scaling was demonstrated on up to 4096 multi-GPU cluster nodes with approximately 25,000 GPUs when decomposing a dense 340 Terabyte-size matrix and an 11 Exabyte-size sparse matrix of density 10 -6 .

97 MATHEMATICS AND COMPUTING↗

Beam controlled nano-robotic device

A system and method (referred to as a method) to fabricate nanorobots. The method generates a pixel map of an atomic object and identifies portions of the atomic object that form a nanorobot. The method stores those identifications in a memory. The method adjusts an electron beam to a noninvasive operating level and images the portions of the atomic object that form the nanorobot. The method executes a plurality of scanning profiles by the electron beam to form the nanorobot and detects nanorobot characteristics and their surroundings via the electron beam in response to executing the plurality of scanning profiles.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Inducing a tunable skyrmion-antiskyrmion system through ion beam modification of FeGe films

Abstract Skyrmions and antiskyrmions are nanoscale swirling textures of magnetic moments formed by chiral interactions between atomic spins in magnetic noncentrosymmetric materials and multilayer films with broken inversion symmetry. These quasiparticles are of interest for use as information carriers in next-generation, low-energy spintronic applications. To develop skyrmion-based memory and logic, we must understand skyrmion-defect interactions with two main goals—determining how skyrmions navigate intrinsic material defects and determining how to engineer disorder for optimal device operation. Here, we introduce a tunable means of creating a skyrmion-antiskyrmion system by engineering the disorder landscape in FeGe using ion irradiation. Specifically, we irradiate epitaxial B20-phase FeGe films with 2.8 MeV Au 4+ ions at varying fluences, inducing amorphous regions within the crystalline matrix. Using low-temperature electrical transport and magnetization measurements, we observe a strong topological Hall effect with a double-peak feature that serves as a signature of skyrmions and antiskyrmions. These results are a step towards the development of information storage devices that use skyrmions and antiskyrmions as storage bits, and our system may serve as a testbed for theoretically predicted phenomena in skyrmion-antiskyrmion crystals.

74 ATOMIC AND MOLECULAR PHYSICS↗

An advanced programmable/reconfigurable color graphics display system for crew station technology research

The hardware configuration, software organization, and applications software for the NASA IKONAS color graphics display system are described. The systems were created at the Langley Research Center Display Device Laboratory to develop, evaluate, and demonstrate advanced generic concepts, technology, and systems integration techniques for electronic crew station systems of future civil aircraft. A minicomputer with 64K core memory acts as a host for a raster scan graphics display generator. The architectures of the hardware system and the graphics display system are provided. The applications software features a FORTRAN-based model of an aircraft, a display system, and the utility program for real-time communications. The model accepts inputs from a two-dimensional joystick and outputs a set of aircraft states. Ongoing and planned work for image segmentation/generation, specialized graphics procedures, and higher level language user interface are discussed.

Montoya, R. J.↗

Towards a Qualification Data Set: Expanded SEE Data on the P2020 Processor

Earlier P2020 SEE data are compared and expanded to a recent die revision, significantly increasing samples tested by protons by five devices, and by heavy ions by five devices. Earlier tested SEE types are found to be fairly similar in register, L1 cache, L2 cache, and CPU crashes. New test methods give SEE performance for the flash memory controller, watchdog circuit, and a built-in Ethernet port on the P2020 processor. Results from heavy ion and proton tests are presented, with data separated over a large number of specific error types and test programs.

Vartanian, Sargeh↗

Quantum Memristors in Frequency-Entangled Optical Fields

A quantum memristor is a passive resistive circuit element with memory, engineered in a given quantum platform. It can be represented by a quantum system coupled to a dissipative environment, in which a system–bath coupling is mediated through a weak measurement scheme and classical feedback on the system. In quantum photonics, such a device can be designed from a beam splitter with tunable reflectivity, which is modified depending on the results of measurements in one of the outgoing beams. Here, we show that a similar implementation can be achieved with frequency-entangled optical fields and a frequency mixer that, working similarly to a beam splitter, produces state superpositions. We show that the characteristic hysteretic behavior of memristors can be reproduced when analyzing the response of the system with respect to the control, for different experimentally attainable states. Since memory effects in memristors can be exploited for classical and neuromorphic computation, the results presented in this work could be a building block for constructing quantum neural networks in quantum photonics, when scaling up.

36 MATERIALS SCIENCE↗

On the Feasibility of 1T Ferroelectric FET Memory Array

To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low- V TH state programming; 2) the body contact can not only supply majority carriers (i.e., holes) for efficient high- V TH state write, but also depletion charge for low- V TH state programming, though with lower efficiency; and 3) during the low/high- V TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high- V TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low- V TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.

FeFET↗

Roadmap for unconventional computing with nanotechnology

Abstract In the ‘Beyond Moore’s Law’ era, with increasing edge intelligence, domain-specific computing embracing unconventional approaches will become increasingly prevalent. At the same time, adopting a variety of nanotechnologies will offer benefits in energy cost, computational speed, reduced footprint, cyber resilience, and processing power. The time is ripe for a roadmap for unconventional computing with nanotechnologies to guide future research, and this collection aims to fill that need. The authors provide a comprehensive roadmap for neuromorphic computing using electron spins, memristive devices, two-dimensional nanomaterials, nanomagnets, and various dynamical systems. They also address other paradigms such as Ising machines, Bayesian inference engines, probabilistic computing with p-bits, processing in memory, quantum memories and algorithms, computing with skyrmions and spin waves, and brain-inspired computing for incremental learning and problem-solving in severely resource-constrained environments. These approaches have advantages over traditional Boolean computing based on von Neumann architecture. As the computational requirements for artificial intelligence grow 50 times faster than Moore’s Law for electronics, more unconventional approaches to computing and signal processing will appear on the horizon, and this roadmap will help identify future needs and challenges. In a very fertile field, experts in the field aim to present some of the dominant and most promising technologies for unconventional computing that will be around for some time to come. Within a holistic approach, the goal is to provide pathways for solidifying the field and guiding future impactful discoveries.

Finocchio, Giovanni (ORCID:0000000210433876)↗

Digital video image system

Interactive recording and display device acts as very-high-speed data-input/output interface between analog (video) signals and standard digital-computer components. System can be used with various picture and memory sizes and can be controlled manually or by computer.

Neely, P. L.↗

Sonoluminescence Bubble Measurements using Vision-Based Algorithms

Vision-based measurement methods were used to measure bubble sizes in this sonoluminescence experiment. Bubble imaging was accomplished by placing the bubble between a bright light source and a microscope-CCD camera system. A collimated light-emitting diode was operated in a pulsed model with an adjustable time delay with respect to the piezo-electric transducer drive signal. The light-emitting diode produced a bubble shadowgraph consisting of a multiple exposure made by numerous light pulses imaged onto a charge-couple device camera. Each image was transferred from the camera to a computer-controlled machine vision system via a frame grabber. The frame grabber was equipped with on-board memory to accomodate sequential image buffering while images were transferred to the host processor and analyzed. This configuration allowed the host computer to perform diameter measurements, centroid position measurements and shape estimation in "real-time" as the next image was being acquired. Bubble size measurement accuracy with an uncertainty of 3 microns was achieved using standard lenses and machine vision algorithms. Bubble centroid position accuracy was also within the 3 micron tolerance of the vision system. This uncertainty estimation accounted for the optical spatial resolution, digitization errors and the edge detection algorithm accuracy. The vision algorithms include camera calibration, thresholding, edge detection, edge position determination, distance between two edges computations and centroid position computations.

Hall, Nancy R.↗