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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 901 records · Page 50
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Digital circuits using universal logic gates

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Whitaker, Sterling R.↗
NASA NTRS1998

Voltage-gated calcium channel and antisense oligonucleotides thereto

An antisense oligonucleotide of 10 to 35 nucleotides in length that can hybridize with a region of the .alpha..sub.1 subunit of the SA-Cat channel gene DNA or mRNA is provided, together with pharmaceutical compositions containing and methods utilizing such antisense oligonucleotide.

Hruska, Keith A.↗
NASA NTRS1986

Silicon controlled rectifier polyphase bridge inverter commutated with gate-turn-off thyristor

A polyphase SCR inverter (10) having N switching poles, each comprised of two SCR switches (1A, 1B; 2A, 2B . . . NA, NB) and two diodes (D1B; D1B; D2A, D2B . . . DNA, DNB) in series opposition with saturable reactors (L1A, L1B; L2A, L2B . . . LNA, LNB) connecting the junctions between the SCR switches and diodes to an output terminal (1, 2 . . . 3) is commutated with only one GTO thyristor (16) connected between the common negative terminal of a dc source and a tap of a series inductor (14) connected to the positive terminal of the dc source. A clamp winding (22) and diode (24) are provided, as is a snubber (18) which may have its capacitance (c) sized for maximum load current divided into a plurality of capacitors (C.sub.1, C.sub.2 . . . C.sub.N), each in series with an SCR switch S.sub.1, S.sub.2 . . . S.sub.N). The total capacitance may be selected by activating selected switches as a function of load current. A resistor 28 and SCR switch 26 shunt reverse current when the load acts as a generator, such as a motor while braking.

Edwards, Dean B.↗
NASA NTRS2008

Range-Gated Metrology with Compact Optical Head

This work represents a radical simplification in the design of the optical head needed for high-precision laser ranging applications. The optical head is now a single fiber-optic collimator with dimensions of order of 1 1 2 cm, which can be easily integrated into the system being measured with minimal footprint.

Dubovitsky, Serge↗
NASA NTRS2006

Microdose Induced Data Loss on Floating Gate Memories

Heavy ion irradiation of flash memories shows loss of stored data. The fluence dependence is indicative of microdose effects. Other qualitative factors identifying the effect as microdose are discussed. The data is presented, and compared to statistical results of a microdose target-based model.

radiation effects↗
NASA NTRS2010

The Golden Gate: Building Bridges Between Research and Operations

Previous research has discussed the ongoing dilemma of implementing research-based findings in an applied setting. This panel will discuss lessons learned from various examples where bridges have been forged between research and operations, and examine ways to promote and achieve similar collaborations in other areas in the future.

Schmidt, Lacey L.↗
NASA NTRS2011

Dynamic Gate Product and Artifact Generation from System Models

Model Based Systems Engineering (MBSE) is gaining acceptance as a way to formalize systems engineering practice through the use of models. The traditional method of producing and managing a plethora of disjointed documents and presentations ("Power-Point Engineering") has proven both costly and limiting as a means to manage the complex and sophisticated specifications of modern space systems. We have developed a tool and method to produce sophisticated artifacts as views and by-products of integrated models, allowing us to minimize the practice of "Power-Point Engineering" from model-based projects and demonstrate the ability of MBSE to work within and supersede traditional engineering practices. This paper describes how we have created and successfully used model-based document generation techniques to extract paper artifacts from complex SysML and UML models in support of successful project reviews. Use of formal SysML and UML models for architecture and system design enables production of review documents, textual artifacts, and analyses that are consistent with one-another and require virtually no labor-intensive maintenance across small-scale design changes and multiple authors. This effort thus enables approaches that focus more on rigorous engineering work and less on "PowerPoint engineering" and production of paper-based documents or their "office-productivity" file equivalents.

XML↗
NASA NTRS2011

Single Event Effects (SEE) Testing of Embedded DSP Cores within Microsemi RTAX4000D Field Programmable Gate Array (FPGA) Devices

Motivation for this work is: (1) Accurately characterize digital signal processor (DSP) core single-event effect (SEE) behavior (2) Test DSP cores across a large frequency range and across various input conditions (3) Isolate SEE analysis to DSP cores alone (4) Interpret SEE analysis in terms of single-event upsets (SEUs) and single-event transients (SETs) (5) Provide flight missions with accurate estimate of DSP core error rates and error signatures.

Perez, Christopher E.↗
NASA NTRS2011

Dynamic Gate Product and Artifact Generation from System Models

Model Based Systems Engineering (MBSE) is gaining acceptance as a way to formalize systems engineering practice through the use of models. The traditional method of producing and managing a plethora of disjointed documents and presentations ("Power-Point Engineering") has proven both costly and limiting as a means to manage the complex and sophisticated specifications of modern space systems. We have developed a tool and method to produce sophisticated artifacts as views and by-products of integrated models, allowing us to minimize the practice of "Power-Point Engineering" from model-based projects and demonstrate the ability of MBSE to work within and supersede traditional engineering practices. This paper describes how we have created and successfully used model-based document generation techniques to extract paper artifacts from complex SysML and UML models in support of successful project reviews. Use of formal SysML and UML models for architecture and system design enables production of review documents, textual artifacts, and analyses that are consistent with one-another and require virtually no labor-intensive maintenance across small-scale design changes and multiple authors. This effort thus enables approaches that focus more on rigorous engineering work and less on "PowerPoint engineering" and production of paper-based documents or their "office-productivity" file equivalents.

engineering paradigm↗
NASA NTRS2012

Effects of Ion Atomic Number on Single-Event Gate Rupture (SEGR) Susceptibility of Power MOSFETs

The relative importance of heavy-ion interaction with the oxide, charge ionized in the epilayer, and charge ionized in the drain substrate, on the bias for SEGR failure in vertical power MOSFETs is experimentally investigated. The results indicate that both the charge ionized in the epilayer and the ion atomic number are important parameters of SEGR failure. Implications on SEGR hardness assurance are discussed.

Lauenstein, Jean-Marie↗
NASA NTRS2014

Field Programmable Gate Array Apparatus, Method, and Computer Program

An apparatus is provided that includes a plurality of modules, a plurality of memory banks, and a multiplexor. Each module includes at least one agent that interfaces between a module and a memory bank. Each memory bank includes an arbiter that interfaces between the at least one agent of each module and the memory bank. The multiplexor is configured to assign data paths between the at least one agent of each module and a corresponding arbiter of each memory bank based on the assigned data path. The at least one agent of each module is configured to read data from the corresponding arbiter of the memory bank or write modified data to the corresponding arbiter of the memory bank.

Morfopoulos, Arin C.↗