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DOE OSTI2023

Enhanced Switching Reliability of Hf 0.5 Zr 0.5 O 2 Ferroelectric Films Induced by Interface Engineering

Ferroelectric materials have been widely researched for applications in memory and energy storage. Among these materials and benefiting from their excellent chemical compatibility with complementary metal–oxide–semiconductor (CMOS) devices, hafnia-based ferroelectric thin films hold great promise for highly scaled semiconductor memories, including nonvolatile ferroelectric capacitors and transistors. However, variation in the switched polarization of this material during field cycling and a limited understanding of the responsible mechanisms have impeded their implementation in technology. Here, we show that ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) capacitors that are nearly free of polarization “wake-up”─a gradual increase in switched polarization as a function of the number of switching cycles─can be achieved by introducing ultrathin HfO 2 buffer layers at the HZO/electrodes interface. High-resolution transmission electron microscopy (HRTEM) reveals crystallite sizes substantially greater than the film thickness for the buffer layer capacitors, indicating that the presence of the buffer layers influences the crystallization of the film (e.g., a lower ratio of nucleation rate to growth rate) during postdeposition annealing. This evidently promotes the formation of a polar orthorhombic (O) phase in the as-fabricated buffer layer samples. Synchrotron X-ray diffraction (XRD) reveals the conversion of the nonpolar tetragonal (T) phase to the polar orthorhombic (O) phase during electric field cycling in the control (no buffer) devices, consistent with the polarization wake-up observed for these capacitors. The extent of T–O transformation in the nonbuffer samples is directly dependent on the duration over which the field is applied. Here these results provide insight into the role of the HZO/electrodes interface in the performance of hafnia-based ferroelectrics and the mechanisms driving the polarization wake-up effect.

36 MATERIALS SCIENCE↗

DOE OSTI2020

Electron-electron interactions in low-dimensional Si:P delta layers

Scientists have long studied the physics of highly disordered conducting systems, seeking to understand the multitude of quantum phenomena that govern how electrons move through material systems. Recently, research into silicon-based quantum computing has made disordered conducting systems, such as Si:P monolayers embedded in isotopically pure Si, technically relevant. Consequently, applying and advancing the theoretical frameworks developed to describe electron behavior in disordered systems is a necessary objective in this field of research. This study investigates key components of dopant-based Si quantum computing devices: embedded regions of highly doped delta layers (δ layers). We examine the transport behavior and the electron-electron interaction (EEI) physics in embedded Si:P δ layers by means of self-consistent magnetotransport measurements. Parameters associated with the electronic transport offer a meaningful quantitative characterization of δ-layer quality and dopant diffusion. In addition, by examining EEI behaviors in a set of samples with embedded Si:P δ layers produced with different PH3 exposure procedures prior to Si encapsulation, we show how details of material synthesis affect the dimensionality of charge carrier interactions in embedded Si:P δ layers. Furthermore, the relationship between δ-layer confinement and EEI screening lengths is established here. This understanding will help validate important models used for device simulation and design and lead to improvements in the control of electrostatic gating of and tunneling transport through Si:P single atom transistors.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2020

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

NASA NTRS2000

Temperature Distribution Within a Defect-Free Silicon Carbide Diode Predicted by a Computational Model

Most solid-state electronic devices diodes, transistors, and integrated circuits are based on silicon. Although this material works well for many applications, its properties limit its ability to function under extreme high-temperature or high-power operating conditions. Silicon carbide (SiC), with its desirable physical properties, could someday replace silicon for these types of applications. A major roadblock to realizing this potential is the quality of SiC material that can currently be produced. Semiconductors require very uniform, high-quality material, and commercially available SiC tends to suffer from defects in the crystalline structure that have largely been eliminated in silicon. In some power circuits, these defects can focus energy into an extremely small area, leading to overheating that can damage the device. In an effort to better understand the way that these defects affect the electrical performance and reliability of an SiC device in a power circuit, the NASA Glenn Research Center at Lewis Field began an in-house three-dimensional computational modeling effort. The goal is to predict the temperature distributions within a SiC diode structure subjected to the various transient overvoltage breakdown stresses that occur in power management circuits. A commercial computational fluid dynamics computer program (FLUENT-Fluent, Inc., Lebanon, New Hampshire) was used to build a model of a defect-free SiC diode and generate a computational mesh. A typical breakdown power density was applied over 0.5 msec in a heated layer at the junction between the p-type SiC and n-type SiC, and the temperature distribution throughout the diode was then calculated. The peak temperature extracted from the computational model agreed well (within 6 percent) with previous first-order calculations of the maximum expected temperature at the end of the breakdown pulse. This level of agreement is excellent for a model of this type and indicates that three-dimensional computational modeling can provide useful predictions for this class of problem. The model is now being extended to include the effects of crystal defects. The model will provide unique insights into how high the temperature rises in the vicinity of the defects in a diode at various power densities and pulse durations. This information also will help researchers in understanding and designing SiC devices for safe and reliable operation in high-power circuits.

Kuczmarski, Maria A.↗

DOE OSTI2025

Focused Helium Ion Beam for Direct Patterning of Monolayer MoS 2 Nanoribbon Field Effect Devices

The helium ion microscope (HIM) focused ion beam (FIB) has emerged as a powerful tool to directly pattern nanostructures below 10 nm due to its high-resolution capabilities and the inert nature of the ion source. These attributes make HIM FIB particularly interesting for patterning 2D materials such as transition metal dichalcogenides (TMDs) to investigate transport phenomena at the nanoscale. Reported here is the fabrication of MoS 2 nanoribbon devices using HIM FIB-induced etching (FIBIE) with XeF 2 , allowing for reduced ion dose compared to direct sputtering. While patterning is efficacious, the devices exhibit performance degradation with decreasing nanoribbon width due to damage up to 150 nm beyond the patterned edge. Incorporating an hBN encapsulation improves device performance by one order of magnitude, although the lateral extent of damage remains unchanged. The spatial distribution of damage is shown to be determined by the forward- and backscattered ions and electrons, while the hBN encapsulation layer substantially reduces damage from XeF 2 interactions in unexposed regions. Raman and photoluminescence (PL) measurements corroborate these findings, while ion/solid interaction simulations further elucidate the resolution limits imposed by substrate interactions. In conclusion, this work provides critical insights and a practical pathway for utilizing HIM FIBIE in 2D TMD functional device patterning.

MoS 2↗