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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Real-Time Artificial Intelligence for Particle Reconstruction and Higgs Physics

With the discovery of the Higgs boson at the CERN LHC, the world's highest-energy particle accelerator complex, scientists have acquired an important tool to study the fundamental building blocks of the universe. Precision measurements of Higgs bosons produced with large momentum allow for unique insights into the structure of the interactions of the Higgs boson with other particles that may shed light on physics beyond the standard model. While experimentally challenging, exploring such interactions with novel artificial intelligence (AI) methods can advance our understanding of the Higgs sector, including the Higgs boson's self-interaction. Moreover, the LHC is undergoing a major upgrade to further increase its particle collision rate and thereby operate for an additional decade. The experimental detectors at the upgraded facility must process at least a factor of ten more data at rates of hundreds of terabytes per second all under challenging conditions. New AI techniques are required to reconstruct and select, or trigger on, the most physics-sensitive events in real-time to handle the resulting avalanche of data. The proposed research will achieve the goals of the LHC program at the CMS experiment by developing a sub-microsecond event reconstruction system using real-time AI algorithms that employ field-programmable gate array technologies. By harnessing sophisticated AI techniques, this research focuses on measuring the production of Higgs bosons at large momentum while enhancing particle reconstruction methods in the trigger and beyond. Overall, the proposed research has broader implications for the use of AI in resource-constrained, low-latency embedded applications across all fields of science.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

Recent evaluations of counter-based periodic testing strategies for fault detection in Microprocessor (μP) have shown that only a small set of counters is needed to provide complete coverage of severe faults. Severe faults are defined as faults that leak sensitive information, e.g., an encryption key on the output of a serial port. Alternatively, fault detection can be accomplished by executing instructions that periodically test the control and functional units of the μP. In this paper, we propose a fault detection method that utilizes an ’engineered’ executable program combined with a small set of strategically placed counters in pursuit of a hardware Periodic Built-In-Self-Test (PBIST). We analyze two distinct methods for generating such a binary; the first uses an Automatic Test Generation Pattern (ATPG)-based methodology, and the second uses a process whereby existing counter-based node-monitoring infrastructure is utilized. We show that complete fault coverage of all leakage faults is possible using relatively small binaries with low latency to fault detection and by utilizing only a few strategically placed counters in the μP.

42 ENGINEERING↗
DOE OSTI2022

Data Compression in the NEXT-100 Data Acquisition System

NEXT collaboration detectors are based on energy measured by an array of photomultipliers (PMT) and topological event filtering based on an array of silicon photomultipliers (SiPMs). The readout of the PMT sensors for low-frequency noise effects and detector safety issues requires a grounded cathode connection that makes the readout AC-couple with variations in the signal baseline. Strict detector requirements of energy resolution better than 1% FWHM require a precise baseline reconstruction that is performed offline for data analysis and detector performance characterization. Baseline variations make it inefficient to apply traditional lossy data compression techniques, such as zero-suppression, that help to minimize data throughput and, therefore, the dead time of the system. However, for the readout of the SiPM sensors with less demanding requirements in terms of accuracy, a traditional zero-suppression is currently applied with a configuration that allows for a compression ratio of around 71%. The third stage in the NEXT detectors program, the NEXT-100 detector, is a 100 kg detector that instruments approximately five times more PMT sensors and twice the number of SiPM sensors than its predecessor, the NEXT-White detector, putting more pressure in the DAQ throughput, expected to be over 900 MB/s with the current configuration, which will worsen the dead time of the acquisition data system. This paper describes the data compression techniques applied to the sensor data in the NEXT-100 detector, which reduces data throughput and minimizes dead time while maintaining the event rate to the level of its predecessor, around 50 Hz.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS2002

SEE and TID extension testing of the Xilinx XQR18V04 4Mbit radiation hardened configuration PROM

The XQR18V04 was evaluated for single event upset rates using proton and heavy ions. The PROM was demonstrated to be immune to latch-up, as well as to static upset in the flash memory cells, to an LET > 125 MeV/mg/cmz (effective). The PROM was also tested in a dynamic mode, which revealed three distinct error modes: Read Bit Errors, Address Errors, and a Single Event Functional Interrupt (SEW which affected the data output drivers. Saturation cross-sections, and onset thresholds, for these errorinodes were measured at the heavy ion facility at Texas A&M University, and the proton facility at UC Davis. Additional testing was performed at UC Davis and the Cobalt 60 source at McClellan Air Force Base to examine the effect to TID life as a function of power biasing. The PROM demonstrated a 100% improvement in total TID life with an 84% percent decrease in device usage.

FPGA Virtex II SEU↗
NASA NTRS1998

Evolvable Electronic Systems

Explore the source record for details and available documents.

Evolvable Systems hardware engineered electronics ↗
NASA NTRS2006

Catastrophic Fault Recovery with Self-Reconfigurable Chips

Mission critical systems typically employ multi-string redundancy to cope with possible hardware failure. Such systems are only as fault tolerant as there are many redundant strings. Once a particular critical component exhausts its redundant spares, the multi-string architecture cannot tolerate any further hardware failure. This paper aims at addressing such catastrophic faults through the use of 'Self-Reconfigurable Chips' as a last resort effort to 'repair' a faulty critical component.

fault tolerance↗
NASA NTRS2006

An Interleaver Implementation for the Serially Concatenated Pulse-Position Modulation Decoder

We describe novel interleaver and deinterleaver architectures that support bandwidth efficient memory access for decoders of turbo-like codes that are used in conjunction with high order modulations. The presentation focuses on a decoder for serially concatenated pulse-position modulation (SCPPM), which is a forward-error-correction code designed by NASA to support laser communications from Mars at more than 50 megabits-per-second (Mbps). For 64-ary PPM, the new architectures effectively triple the fan-in of the interleaver and fan-out of the deinterleaver, enabling parallelization that doubles the overall throughput. The techniques described here can be readily modified for other PPM orders.

turbo decoding↗
NASA NTRS2006

Tuning of MEMS Gyroscope using Evolutionary Algorithm and "Switched Drive-Angle" Method

We propose a tuning method for Micro-Electro-Mechanical Systems (MEMS) gyroscopes based on evolutionary computation that has the capacity to efficiently increase the sensitivity of MEMS gyroscopes through tuning and, furthermore, to find the optimally tuned configuration for this state of increased sensitivity. We present the results of an experiment to determine the speed and efficiency of an evolutionary algorithm applied to electrostatic tuning of MEMS micro gyros. The MEMS gyro used in this experiment is a pyrex post resonator gyro (PRG) in a closed-loop control system. A measure of the quality of tuning is given by the difference in resonant frequencies, or frequency split, for the two orthogonal rocking axes. The current implementation of the closed-loop platform is able to measure and attain a relative stability in the sub-millihertz range, leading to a reduction of the frequency split to less than 100 mHz.

Micro-Electro-Mechanical Systems (MEMS)↗
NASA NTRS2008

VIRTEX-4 VQ static SEU Characterization Summary

This report is the result of the combined efforts of members within the Xilinx Radiation Test Consortium (XRTC), sometimes known as the Xilinx SEE Test Consortium. The XRTC is a voluntary association of aerospace entities, including leading aerospace companies, universities and national laboratories, combining resources to characterize reconfigurable FPGAs for aerospace applications. Previous publications of Virtex-4 radiation results are for commercial (non-epitaxial) devices; see, for example, Refs. 1-4. A notable exception is Ref. 5, which presents XRTC upset measurements of storage elements in the PowerPC405s in the XQR4VFX60. This report of upset susceptibility to heavy ions and protons of the static memory elements in the Virtex-4QV family is a direct parallel to the XRTC report on the thin epitaxial devices in the Virtex-2 family released four years ago.

field programmable gate array (FPGA)↗
NASA NTRS2004

Tradeoffs in Flight Design Upset Mitigation in State of the Art FPGAs: Hardened by Design vs. Design Level Hardening

This presentation compares and contrasts the effectiveness and the system/designer impacts of the two main approaches to upset hardening: the Actel approach (RTSX-S and RTAX-S) of low-level (inside each flip-flop) triplication and the Xilinx approach (Virtex and Virtex2) of design-level triplication of both functional blocks and voters. The effectiveness of these approaches is compared using measurements made in conjunction with each of the FPGAs' manufacturer: for Actel, published data [1] and for Xilinx, recent results from the Xilinx SEE Test Consortium (note that the author is an active and founding member). The impacts involve Actel advantages in the areas of transistor-utilization efficiency and minimizing designer involvement in the triplication while the Xilinx advantages relate to the ability to custom tailor upset hardness and the flexibility of re-configurability. Additionally, there are currently clear Xilinx advantages in available features such as the number of I/O's, logic cells, and RAM blocks as well as speed. However, the advantage of the Actel anti-fuses for configuration over the Xilinx SRAM cells is that the latter need additional functionality and external circuitry (PROMs and, at least a watchdog timer) for configuration and configuration scrubbing. Further, although effectively mitigated if done correctly, the proton upset-ability of the Xilinx FPGAs is a concern in severe proton-rich environments. Ultimately, both manufacturers' upset hardening is limited by SEFI (single-event functional interrupt) rates where it appears the Actel results are better although the Xilinx Virtex2-family result of about one SEFI in 65 device-years in solar-min GCR (the more intense part of the galactic cosmic-ray background) should be acceptable to most missions

radiation effects↗
NASA NTRS2003

Mitigating Upsets in SRAM-Based FPGAs from the Xilinx Virtex 2 Family

Static random access memory (SRAM) upset rates in field programmable gate arrays (FPGAs) from the Xilinx Virtex 2 family have been tested for radiation effects on configuration memory, block RAM and the power-on-reset (POR) and SelectMAP single event functional interrupts (SEFIs). Dynamic testing has shown the effectiveness and value of Triple Module Redundancy (TMR) and partial reconfiguration when used in conjunction. Continuing dynamic testing for more complex designs and other Virtex 2 capabilities (i.e., I/O standards, digital clock managers (DCM), etc.) is scheduled.

SEE testing↗
NASA NTRS2014

SEU System Analysis: Not Just the Sum of All Parts

Single event upset (SEU) analysis of complex systems is challenging. Currently, system SEU analysis is performed by component level partitioning and then either: the most dominant SEU cross-sections (SEUs) are used in system error rate calculations; or the partition SEUs are summed to eventually obtain a system error rate. In many cases, system error rates are overestimated because these methods generally overlook system level derating factors. The problem with overestimating is that it can cause overdesign and consequently negatively affect the following: cost, schedule, functionality, and validation/verification. The scope of this presentation is to discuss the risks involved with our current scheme of SEU analysis for complex systems; and to provide alternative methods for improvement.

Single Event Upset (SEU) Testing↗