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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 901 records · Page 50

Transitioning Autonomous Systems Technology Research to a Flight Software Environment

NASA has developed methods and algorithms for autonomous spacecraft operations,including automated planning and scheduling, fault diagnostics and impact determination,procedure management and display. Making the transition from technology research tooperational flight software requires overcoming significant technical, programmatic andcultural challenges. Technology research is aimed at developing methods that performspecific functions correctly, but the resulting software may not be designed for flightprocessors with limited CPU, memory and network resources, and may not be easilyintegrated into spacecraft flight software. Our objective in the Autonomous Systems andOperations Project is to make significant strides toward the transformation from technologyto operational use. Our focus was twofold: maturing research grade autonomy software intoa flight software environment using broadly accepted languages and tools; and integratingautonomy applications with each other and with representative systems and their data andcommand interfaces. For a target flight software environment, we chose Core FlightSoftware, developed by Goddard Space Flight Center as a common operating systemindependent framework. Our hardware integration environment was provided by theIntegrated Power and Avionics Systems (iPAS) Lab at Johnson Space Center, in whichvarious subsystem development has been conducted to address engineering challenges forthe vehicles and systems required for long-duration missions into the solar system. The iPASand its network of connected facilities provides realistic subsystem hardware or simulationsof spacecraft power, life support, guidance, navigation and control, and command and datahandling subsystems. Interfaces between autonomy applications and the subsystems beingassessed and controlled were developed, assessed and refined. The hardware and softwareenvironment using CFS and the iPAS facility has proven to be a highly flexible and realisticenvironment in which to rapidly integrate applications in an iterative, low cost setting. Usingthe integration environment we have developed, we will turn our focus to performance andsizing analysis to determine the computational requirements for full-scale deployment ofautonomy technology. Scalability of reasoners and the spacecraft models upon which theyoperate, and robustness across the full range of spacecraft conditions and environments willbe explored and improved. We are making significant contributions to the future programsthat will build the spacecraft that will take humans beyond the Earth-Moon system, in whichprogram Systems Engineers will be able to accurately and confidently design in accurate,robust and mature autonomous operations systems.

Flight Software↗

Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems

Fail-slow hardware is an under-studied failure mode. We present a study of 114 reports of fail-slow hardware incidents, collected from large-scale cluster deployments in 14 institutions. We show that all hardware types such as disk, SSD, CPU, memory, and network components can exhibit performance faults. We made several important observations such as faults convert from one form to another, the cascading root causes and impacts can be long, and fail-slow faults can have varying symptoms. From this study, we make suggestions to vendors, operators, and systems designers.

fail-slow↗

Computer Science Research Needs for Parallel Discrete Event Simulation (PDES)

Historically, scientific computing efforts have demonstrated the clear need for, and effective use of, supercomputing with traditional time-stepped simulations. Nevertheless, there are several areas in the mission spaces of the U.S. Department of Energy and other agencies waiting to tap advanced computing research using a different, discrete event style of modeling, simulation, and analysis. These span a wide spectrum of applications including energy grid resilience, urban planning and policy, transportation science, building technologies, emergency response and planning, environmental impact analysis, computational epidemiology, Internet communications, cyber security, and cyber-physical systems, to name only a few. Even within traditional scientific applications, the role of discrete event modes of execution is increasing in the form of new event-based mathematical solvers such as quantized state integration methods and discrete-continuous hybrid system solvers. Co-design of advanced supercomputing hardware systems is another area that exploits discrete event simulation at its core for effective analyses. Complex systems, entity behaviors and interconnections play a significant role in all these applications, which are mapped to large-scale models with discrete event formulations. To make advancements in all the aforementioned scientific areas, many technical aspects need to be more thoroughly studied and deeply understood in parallel discrete event simulation (PDES). The unique dynamics inherent in a discrete event modeling approach, by their very nature, intersect and influence the entire stack of the computing system, including (a) the unique nature of the instruction sets exercised in PDES workloads without a predominance of high-precision floating point operations, (b) virtual time-constrained multi-threaded execution of many logical processes per processor, (c) extremely variable and difficult to predict network traffic characteristics, (d) interfaces and inter-dependencies with machine learning and artificial intelligence codes at higher software layers, and (e) highly challenging load balancing needs, especially in effectively accounting for accelerated/extremely heterogeneous computing in current and future high-performance computing systems. Efficient and accurate parallel execution of PDES workloads is also dominated by challenges in dealing with their asynchronous concurrency fundamentally present at the model level. Conservative synchronization, optimistic/speculative synchronization, and their hybrid schemes open new questions in fundamental computer science with respect to reversibility of computation and prediction (lookahead) of behaviors inherent within model codes. On the implementation front, there are relatively few scalable, general-purpose parallel discrete event simulators in the world, and even fewer have been studied on emerging hardware platforms. To enable scientific advances using PDES, the research needs in computer science must also be pursued and met in the intersection of the algorithmic and hardware-aware aspects of scalable PDES engines. This report is aimed at capturing a computer science-oriented view of this important area of research in PDES, presenting a sample of important applications with their inherent discrete event technology elements. Needs are outlined in core areas of parallel discrete event research as well as cross-cutting directions in computer science research that positively impact scientific advancements across several important application areas. A selection of priority research opportunities in advanced computing for PDES is identified to serve as reference for key research topics and their order of importance for scientific advancements.

97 MATHEMATICS AND COMPUTING↗

Memristive Ion Channel-Doped Biomembranes as Synaptic Mimics

Solid-state neuromorphic systems based on transistors or memristors have yet to achieve the interconnectivity, performance, and energy efficiency of the brain due to excessive noise, undesirable material properties, and nonbiological switching mechanisms. Here in this work, we demonstrate that an alamethicin-doped, synthetic biomembrane exhibits memristive behavior, emulates key synaptic functions including paired-pulse facilitation and depression, and enables learning and computing. Unlike state-of-the-art devices, our two-terminal, biomolecular memristor features similar structure (biomembrane), switching mechanism (ion channels), and ionic transport modality as biological synapses while operating at considerably lower power. The reversible and volatile voltage-driven insertion of alamethicin peptides into an insulating lipid bilayer creates conductive pathways that exhibit pinched current–voltage hysteresis at potentials above their insertion threshold. Moreover, the synapse-like dynamic properties of the biomolecular memristor allow for simplified learning circuit implementations. Finally, low-power memristive devices based on stimuli-responsive biomolecules represent a major advance toward implementation of full synaptic functionality in neuromorphic hardware.

36 MATERIALS SCIENCE↗

High performance techniques for micro channel plate computations in photo multipliers

Monte Carlo - MC methods, requiring heavy computations of large data volume, can be used to predict the amplitude distribution and variance of outputted electron charge in Micro Channel Plates - MCPs, which are fed with primary emitted electrons in their inputs. The concept of parallel and serial combination of separate stages of such stochastic processes, which can be applied in MCP systems and simulated using MC computations, has recently proposed and shown interesting theorems and results. Separating the electron multiplication procedures, occurring in the channels of MCP systems, into sub-procedures, which are similar in nature and occur either in parallel or in consecutive manners, is equivalent to splitting the relevant stochastic system calculations into smaller ones, which can be performed concurrently and/or sequentially. In this way, calculations similar in nature, can be executed only once, thus, eliminating a great percentage of heavy computations. However, when designing and implementing the calculation inferences of the derived theorems using High Performance Computation - HPC techniques, the overall computation cost can further and significantly be reduced. In this paper, the hardware mappings of the relevant theorem inferences onto parallel computing architectures, resulting in circuits of computing blocks for calculation purposes of MCP system stochastic processes, are investigated. Each of the designed and implemented computing circuits corresponds to a theorem inference or to a combination of inferences. The parallelism of the proposed circuits consists of both the concurrent functioning of all the system blocks and of the simultaneous operation of each block, which is processing pieces of data, for many parts of the whole circuit in which it belongs. All the circuits are designed and tested using Altera Quartus II environment and can be implemented as chips, which can be incorporated in computing devices to assist Monte Carlo computations for the estimation of different MCP electron multiplication system performances.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Use of Multiple Tracer Gases to Quantify Vane Trailing Edge Flow Into Turbine Rim Seals

Abstract Overlapping features are commonly used as rim seals between stationary and rotating components in a turbine stage. These rim seals are used to prevent main gas path ingestion to the wheelspace cavity, which reduces the lifespan of critical engine components such as the turbine disk. In addition to the overlapping features, purge flow, diverted from the compressor, is injected into the rim cavity to act as an airflow sealing mechanism. Previous research identified that in addition to the purge flow in the rim cavity, cooling flow from the vane trailing edge (VTE) is ingested into the rim seal cavity carrying the potential to cool components in the wheelspace. These previous findings, however, were not able to distinctly separate purge from VTE cooling flows, which is the contribution of this paper based on uniquely using two different tracer gases. A one-stage test turbine operating at engine-relevant conditions and consisting of real engine hardware was used to validate and quantify the ingestion of the VTE flow by independently seeding the purge and VTE flows with two different tracer gases. Experimental results show the presence of VTE flow in the rim seal throughout all purge flowrates evaluated. Circumferential variation of VTE flow was also studied both experimentally and computationally using a computational fluid dynamics model. Results showed that ingested VTE flow can reduce the detrimental effect of hot gas ingestion particularly at higher purge flowrates.

Engineering↗

RAJA Performance Suite

The RAJA Performance Suite is designed to evaluate performance of the RAJA performance portability library on a wide variety of important high performance computing (HPC) algorithmic lulmels. These kernels assess compiler optimizations and various parallel programming model backends accessible through RAJA, such as OpenMP, CUDA, etc. The Initial version of the suite contains 25 computational kernels, each of which appears in 6 variants: Baseline SequcntiaJ, RAJA SequentiaJ, Baseline OpenMP, RAJA OpenMP, Baseline CUDA, RAJA CUDA. All variants of each kernel perform essentially the same mathematical operations and the loop body code for each kernel is identical across all variants. There are a few kernels, such as those that contain reduction operations, that require CUDA-specific coding for their CUDA variants. ActuaJ computer instructions executed and how they run in parallel differs depending on the parallel programming model backend used and which optimizations are perfonned by the compiler used to build the Perfonnance Suite executable. The Suite will be used primarily by RAJA developers to perform regular assessments of RAJA performance across a range of hardware platforms and compilers as RAJA features are being developed. It will also be used by LLNL hardware and software vendor panners for new defining requirements for future computing platform procurements and acceptance testing. In particular, the RAJA Performance Suite will be used for compiler acceptance testing of the upcoming CORAUSierra machine {initial LLNL delivery expected in late-2017/early 2018) and the CORAL-2 procurement. The Suite will aJso be used to generate concise source code reproducers of compiler and runtime issues we uncover so that we may provide them to relevant vendors to be fixed.

Hornung, RichardD.↗

Contingency Contractor Optimization Phase 3 Sustainment Platform Requirements - Contingency Contractor Optimization Tool - Prototype

Sandia National Laboratories (Sandia) is in Phase 3 Sustainment of development of a prototype tool, currently referred to as the Contingency Contractor Optimization Tool - Prototype (CCOTP), under the direction of OSD Program Support. CCOT-P is intended to help provide senior Department of Defense (DoD) leaders with comprehensive insight into the global availability, readiness and capabilities of the Total Force Mix. The CCOT-P will allow senior decision makers to quickly and accurately assess the impacts, risks and mitigating strategies for proposed changes to force/capabilities assignments, apportionments and allocations options, focusing specifically on contingency contractor planning. During Phase 2 of the program, conducted during fiscal year 2012, Sandia developed an electronic storyboard prototype of the Contingency Contractor Optimization Tool that can be used for communication with senior decision makers and other Operational Contract Support (OCS) stakeholders. Phase 3 used feedback from demonstrations of the electronic storyboard prototype to develop an engineering prototype for planners to evaluate. Sandia worked with the DoD and Joint Chiefs of Staff strategic planning community to get feedback and input to ensure that the engineering prototype was developed to closely align with future planning needs. The intended deployment environment was also a key consideration as this prototype was developed. Initial release of the engineering prototype was done on servers at Sandia in the middle of Phase 3. In 2013, the tool was installed on a production pilot server managed by the OUSD(AT&L) eBusiness Center. The purpose of this document is to specify the CCOT-P engineering prototype platform requirements as of May 2016. Sandia developed the CCOT-P engineering prototype using common technologies to minimize the likelihood of deployment issues. CCOT-P engineering prototype was architected and designed to be as independent as possible of the major deployment components such as the server hardware, the server operating system, the database, and the web server. This document describes the platform requirements, the architecture, and the implementation details of the CCOT-P engineering prototype.

42 ENGINEERING↗

Investigation of the performance characteristics of Doppler radar technique for aircraft collision hazard warning, phase 3

System studies, equipment simulation, hardware development and flight tests which were conducted during the development of aircraft collision hazard warning system are discussed. The system uses a cooperative, continuous wave Doppler radar principle with pseudo-random frequency modulation. The report presents a description of the system operation and deals at length with the use of pseudo-random coding techniques. In addition, the use of mathematical modeling and computer simulation to determine the alarm statistics and system saturation characteristics in terminal area traffic of variable density is discussed.

Source record↗

The minitrack tracking function description, volume 1

The treatment of tracking data by the Minitrack system is described from the transmission of the nominal 136-MHz radio beacon energy from a satellite and the reception of this signal by the interferometer network through the ultimate derivation of the direction cosines (the angular coordinates of the vector from the tracking station to the spacecraft) as a function of time. Descriptions of some of the lesser-known functions operating on the system, such as the computer preprocessing program, are included. A large part of the report is devoted to the preprocessor, which provides for the data compression, smoothing, calibration correction, and ambiguity resolution of the raw interferometer phase tracking measurements teletyped from each of the worldwide Minitrack tracking stations to the central computer facility at Goddard Space Flight Center. An extensive bibliography of Minitrack hardware and theory is presented.

Englar, T. S., Jr.↗

The Hubble Space Telescope fine guidance system operating in the coarse track pointing control mode

The Hubble Space Telescope (HST) Fine Guidance System has set new standards in pointing control capability for earth orbiting spacecraft. Two precision pointing control modes are implemented in the Fine Guidance System; one being a Coarse Track Mode which employs a pseudo-quadrature detector approach and the second being a Fine Mode which uses a two axis interferometer implementation. The Coarse Track Mode was designed to maintain FGS pointing error to within 20 milli-arc seconds (rms) when guiding on a 14.5 Mv star. The Fine Mode was designed to maintain FGS pointing error to less than 3 milli-arc seconds (rms). This paper addresses the HST FGS operating in the Coarse Track Mode. An overview of the implementation, the operation, and both the predicted and observed on orbit performance is presented. The discussion includes a review of the Fine Guidance System hardware which uses two beam steering Star Selector servos, four photon counting photomultiplier tube detectors, as well as a 24 bit microprocessor, which executes the control system firmware. Unanticipated spacecraft operational characteristics are discussed as they impact pointing performance. These include the influence of spherically aberrated star images as well as the mechanical shocks induced in the spacecraft during and following orbital day/night terminator crossings. Computer modeling of the Coarse Track Mode verifies the observed on orbit performance trends in the presence of these optical and mechanical disturbances. It is concluded that the coarse track pointing control function is performing as designed and is providing a robust pointing control capability for the Hubble Space Telescope.

Whittlesey, Richard↗

Bolt cutter functional evaluation

The Aerospace Corporation has been implementing finite difference and finite element codes for the analysis of a variety of explosive ordnance devices. Both MESA-2D and DYNA3D have been used to evaluate the role of several design parameters on the performance of a satellite separation system bolt cutter. Due to a lack of high strain rate response data for the materials involved, the properties for the bolt cutter and the bolt were selected to achieve agreement between computer simulation and observed characteristics of the recovered test hardware. The calculations provided insight into design parameters such as the cutter blade kinetic energy, the preload on the bolt, the relative position of the anvil, and the anvil shape. Modeling of the cutting process clarifies metallographic observation of both cut and uncut bolts obtained from several tests. Understanding the physical processes involved in bolt cutter operation may suggest certain design modifications that could improve performance margin without increasing environmental shock response levels.

S. Goldstein↗

DSN Array Simulator

The DSN Array Simulator (wherein 'DSN' signifies NASA's Deep Space Network) is an updated version of software previously denoted the DSN Receive Array Technology Assessment Simulation. This software (see figure) is used for computational modeling of a proposed DSN facility comprising user-defined arrays of antennas and transmitting and receiving equipment for microwave communication with spacecraft on interplanetary missions. The simulation includes variations in spacecraft tracked and communication demand changes for up to several decades of future operation. Such modeling is performed to estimate facility performance, evaluate requirements that govern facility design, and evaluate proposed improvements in hardware and/or software. The updated version of this software affords enhanced capability for characterizing facility performance against user-defined mission sets. The software includes a Monte Carlo simulation component that enables rapid generation of key mission-set metrics (e.g., numbers of links, data rates, and date volumes), and statistical distributions thereof as functions of time. The updated version also offers expanded capability for mixed-asset network modeling--for example, for running scenarios that involve user-definable mixtures of antennas having different diameters (in contradistinction to a fixed number of antennas having the same fixed diameter). The improved version also affords greater simulation fidelity, sufficient for validation by comparison with actual DSN operations and analytically predictable performance metrics.

Tikidjian, Raffi↗

Leveraging High-Level Synthesis to Migrate Motor Control Algorithms From Microcontroller to FPGA

As motor control algorithms become increasingly complex, traditional microcontroller-based implementations are reaching computational limits that prevent the controller from operating at the required speed. This paper presents a novel workflow leveraging High-Level Synthesis (HLS) to migrate motor control algorithms from a microcontroller implementation to a Field-Programmable Gate Array (FPGA) implementation. The proposed approach utilizes the free Vitis HLS software to automatically convert Embedded Coder-generated C code from a Simulink model into Hardware Description Language (HDL) code suitable for FPGA deployment.

FPGA↗

Leveraging High-Level Synthesis to Migrate Motor Control Algorithms From Microcontroller to FPGA

As motor control algorithms become increasingly complex, traditional microcontroller-based implementations are reaching computational limits that prevent the controller from operating at the required speed. This paper presents a novel workflow leveraging High-Level Synthesis (HLS) to migrate motor control algorithms from a microcontroller implementation to a Field-Programmable Gate Array (FPGA) implementation. The proposed approach utilizes the free Vitis HLS software to automatically convert Embedded Coder-generated C code from a Simulink model into Hardware Description Language (HDL) code suitable for FPGA deployment.

FPGA↗

Deployable sensor system using mesh networking and satellite communication

A sensor system may be configured for continuous operation in a low resource environment and/or in extreme environmental conditions. The sensor system may have sufficient processing capabilities to provide scientific computing for pre-processing, quality control, statistical analysis, event classification, data compression and corrections (e.g., spikes in the data), autonomous decisions and actions, triggering other nodes, and information assurance functions that provide data confidentiality, data integrity, authentication, and non-repudiation. The hardware may have both mesh networking and satellite and cellular communication capability, and may be available for relatively low cost. Such a network provides the flexibility to have potentially any number of nodes be completely independent from one another. Thus, the network may scale across a diverse terrain.

97 MATHEMATICS AND COMPUTING↗

Deployable sensor system using mesh networking and satellite communication

A sensor system may be configured for continuous operation in a low resource environment and/or in extreme environmental conditions. The sensor system may have sufficient processing capabilities to provide scientific computing for pre-processing, quality control, statistical analysis, event classification, data compression and corrections (e.g., spikes in the data), autonomous decisions and actions, triggering other nodes, and information assurance functions that provide data confidentiality, data integrity, authentication, and non-repudiation. The hardware may have both mesh networking and satellite and cellular communication capability, and may be available for relatively low cost. Such a network provides the flexibility to have potentially any number of nodes be completely independent from one another. Thus, the network may scale across a diverse terrain.

Frigo, Janette↗

Control Systems Design for STS Accelerator

The Second Target Station (STS) Project will expand the capabilities of the existing Spallation Neutron Source (SNS), with a suite of neutron instruments optimized for long wavelengths. A new accelerator transport line will be built to deliver one out of four SNS pulses to the new target station. The Integrated Control Systems (ICS) will provide remote control, monitoring, OPI, alarms, and archivers for the accelerator systems, such as magnets power supply, vacuum devices, and beam instrumentation. The ICS will upgrade the existing Linac LLRF controls to allow independent operation of the FTS and STS and support different power levels of the FTS and STS proton beam. The ICS accelerator controls are in the phase of preliminary design for the control systems of magnet power supply, vacuum, LLRF, Timing, Machine protection system (MPS), and computing and machine network. The accelerator control systems build upon the existing SNS Machine Control systems, use the SNS standard hardware and EPICS software, and take full advantage of the performance gains delivered by the PPU Project at SNS.

Yan, Jay↗