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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

First operation of a multi-channel Q-Pix prototype: measuring transverse electron diffusion in a gas time projection chamber

We report measurements of the transverse diffusion of electrons in P-10 gas (90% Ar, 10% CH 4 ) in a laboratory-scale time projection chamber (TPC) utilizing a novel pixelated signal capture and digitization technique known as Q-Pix. The Q-Pix method incorporates a precision switched integrating transimpedance amplifier whose output is compared to a threshold voltage. Upon reaching the threshold, a comparator sends a 'reset' signal, initiating a discharge of the integrating capacitor. The time difference between successive resets is inversely proportional to the average current at the pixel in that time interval, and the number of resets is directly proportional to the total collected charge. We developed a 16-channel Q-Pix prototype fabricated from commercial off-the-shelf components and coupled them to 16 concentric annular anode electrodes to measure the spatial extent of the electron swarm that reaches the anode after drifting through the uniform field of the TPC. The swarm is produced at a gold photocathode using pulsed UV light. The measured transverse diffusion agrees with simulations in PyBoltz across a range of operating pressures (200–1500 Torr). These results demonstrate that a Q-Pix readout can successfully reconstruct the ionization topology in a TPC.

47 OTHER INSTRUMENTATION↗
NASA NTRS2009

Lightning Pin Injection Testing on MOSFETS

Lightning transients were pin-injected into metal-oxide-semiconductor field-effect transistors (MOSFETs) to induce fault modes. This report documents the test process and results, and provides a basis for subsequent lightning tests. MOSFETs may be present in DC-DC power supplies and electromechanical actuator circuits that may be used on board aircraft. Results show that unprotected MOSFET Gates are susceptible to failure, even when installed in systems in well-shielded and partial-shielded locations. MOSFET Drains and Sources are significantly less susceptible. Device impedance decreased (current increased) after every failure. Such a failure mode may lead to cascading failures, as the damaged MOSFET may allow excessive current to flow through other circuitry. Preliminary assessments on a MOSFET subjected to 20-stroke pin-injection testing demonstrate that Breakdown Voltage, Leakage Current and Threshold Voltage characteristics show damage, while the device continues to meet manufacturer performance specifications. The purpose of this research is to develop validated tools, technologies, and techniques for automated detection, diagnosis and prognosis that enable mitigation of adverse events during flight, such as from lightning transients; and to understand the interplay between lightning-induced surges and aging (i.e. humidity, vibration thermal stress, etc.) on component degradation.

Ely, Jay J.↗
DOE OSTI2023

2-Aminoanthracene Crystallization in Its Compatible Polystyrene Block: RAFT Synthesis and Enhanced Charge Retention in Pentacene Transistor Gate Dielectrics

We synthesized polystyrene-block-polyanthrylaminomethylstyrene (PS-b-PAAS) via RAFT reaction and side chain modification where the PAAS block is 50%. By blending 2-aminoanthracene (2AA) with PS-b-PAAS, the co-aggregation behavior of the PAAS block and 2AA within the thin film was observed by optical microscopy (OM) and x-ray diffraction. At 5 and 10 wt% of 2AA within the thin film, OM results showed a clear morphological difference between PS matrix and PS-b-PAAS matrix. Differences in the 2AA excited state lifetime in these matrices were also established using transient absorption spectroscopy (TAS). Blends were used as gate dielectrics in pentacene transistors. We compared characteristic voltage (Vc, an indicator of threshold voltage) before and after charging of PS-b-PAAS blended with unsubstituted PS and both polymers individually blended with 2AA. For blended PS-b-PAAS and PS, as the concentration of PS-b-PAAS increases, the decreased Vc especially with negative charging of the pentacene indicated a larger concentration of charge carriers induced by the dielectric film. The charging experiments also revealed that the unique structure formed by the 2AA/PS-b-PAAS blend significantly affected the charge storage capability of the organic field-effect transistors (OFET). Furthermore, this work demonstrates the novel co-aggregation structure in the dielectrics, and furthermore its impact on charge storage capability in pentacene OFETs.

36 MATERIALS SCIENCE↗
NASA NTRS1992

Low energy CMOS for space applications

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Panwar, Ramesh↗
NASA NTRS1987

A study of charged particles/radiation damage to VLSI device materials

Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.

Okyere, John G.↗
NASA NTRS2015

On Possible Arc Inception on Low Voltage Solar Array

Recent analysis of spacecraft failures during the period of 1990-2013 demonstrated clearly that electrostatic discharges caused more than 8 of all registered failures and anomalies, and comprised the most costly losses (25) for operating companies and agencies. The electrostatic discharges on spacecraft surfaces are the results of differential charging above some critical (threshold) voltages. The mechanisms of differential charging are well known, and various methods have been developed to prevent a generation of significant electric fields in areas of triple junctions. For example, low bus voltages in Low Earth Orbit plasma environment and slightly conducting layer over coverglass (ITO) in Geosynchronous Orbit surroundings are believed to be quite reliable measures to prevent discharges on respective surfaces. In most cases, the vulnerable elements of spacecraft (solar arrays, diode boards, etc.) go through comprehensive ground tests in vacuum chambers. However, tests articles contain the miniscule fragments of spacecraft components such as 10-30 solar cells of many thousands deployed on spacecraft in orbit. This is one reason why manufacturing defects may not be revealed in ground tests but expose themselves in arcing on array surface in space. The other reason for ineffectiveness of discharge preventive measures is aging of all materials in harsh orbital environments. The expected life time of modern spacecraft varies within the range of five-fifteen years, and thermal cycling, radiation damages, and mechanical stresses can result in surface erosion on conductive layers and microscopic cracks in coverglass sheets and adhesive films. These possible damages may cause significant increases in local electric field strengths and subsequent discharges. The primary discharges may or may not be detrimental to spacecraft operation, but they can produce the necessary conditions for sustained arcs initiation. Multiple measures were developed to prevent sustained discharges between adjacent strings, and many ground tests were performed to determine threshold parameters (voltage and current) for sustained arcs. And again, manufacturing defects and aging in space environments may result in considerable decrease of critical threshold parameters. This paper is devoted to the analysis of possible reasons behind arcing on spacecraft with low bus voltages.

plasma interaction↗
NASA NTRS2015

On Possible Arc Inception on Low Voltage Solar Array

Recent analysis of spacecraft failures during the period of 1990-2013 demonstrated clearly that electrostatic discharges caused more than 8 percent of all registered failures and anomalies, and comprised the most costly losses (25 percent) for operating companies and agencies. The electrostatic discharges on spacecraft surfaces are the results of differential charging above some critical (threshold) voltages. The mechanisms of differential charging are well known, and various methods have been developed to prevent a generation of significant electric fields in areas of triple junctions. For example, low bus voltages in Low Earth Orbit plasma environment and slightly conducting layer over cover-glass (ITO) in Geosynchronous Orbit surroundings are believed to be quite reliable measures to prevent discharges on respective surfaces. In most cases, the vulnerable elements of spacecraft (solar arrays, diode boards, etc.) go through comprehensive ground tests in vacuum chambers. However, tests articles contain the miniscule fragments of spacecraft components such as 10-30 solar cells of many thousands deployed on spacecraft in orbit. This is one reason why manufacturing defects may not be revealed in ground tests but expose themselves in arcing on array surface in space. The other reason for ineffectiveness of discharge preventive measures is aging of all materials in harsh orbital environments. The expected life time of modern spacecraft varies within the range of five-fifteen years, and thermal cycling, radiation damages, and mechanical stresses can result in surface erosion on conductive layers and microscopic cracks in cover-glass sheets and adhesive films. These possible damages may cause significant increases in local electric field strengths and subsequent discharges. The primary discharges may or may not be detrimental to spacecraft operation, but they can produce the necessary conditions for sustained arcs initiation. Multiple measures were developed to prevent sustained discharges between adjacent strings, and many ground tests were performed to determine threshold parameters (voltage and current) for sustained arcs. And again, manufacturing defects and aging in space environments may result in considerable decrease of critical threshold parameters. This paper is devoted to the analysis of possible reasons behind arcing on spacecraft with low bus voltages.

low voltage solar array↗
DOE OSTI2022

Iodine Electrochemistry Dictates Voltage‐Induced Halide Segregation Thresholds in Mixed‐Halide Perovskite Devices

Abstract Owing to straightforward stoichiometry–bandgap tunability, mixed‐halide perovskites are ideal for many optoelectronic devices. However, unwanted halide segregation under operational conditions, including light illumination and voltage bias, restricts practical use. Additionally, the origin of voltage‐induced halide segregation is still unclear. Herein, a systematic voltage threshold study in mixed bromide/iodide perovskite devices is performed and leads to observation of three distinct voltage thresholds corresponding to the doping of the hole transport material (0.7 ± 0.1 V), halide segregation (0.95 ± 0.05 V), and degradation (1.15 ± 0.05 V) for an optically stable mixed‐halide perovskite composition with a low bromide content (10%). These empirical threshold voltages are minimally affected by composition until very Br‐rich compositions, which reveals the dominant role of iodide/triiodide/iodine electrochemistry in voltage‐induced Br/I phase separation and transport layer doping reactions in halide perovskite devices.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Charge Trapping in Polymer Electrets with Highly Dilute Blended Arylamine Donors

The nature of and ability to control biasing across dielectrics is a key area of research for the design of more versatile organic field-effect transistors (OFETs). One important technique to achieve such control is the inclusion of donor or acceptor molecules in the dielectric to modulate charge trapping therein. Here in this work, we report the effects of the additive concentration on OFETs with two different arylamines blended in polystyrene (PS) dielectrics, N,N'-diphenyl-N,N'-di-p-tolylbenzene-1,4-diamine (MPDA) and 4-anilinotriphenylamine (PATPA), as well as a comparison between PATPA/PS blends and dielectrics where PATPA was chemically tethered to the PS matrix. Dielectrics included in OFETs were subject to charging, and their charging capacity and stability were extracted from the OFET threshold voltages. For both MPDA/PS and PATPA/PS, blends with additive mole fractions as low as χ = 3 × 10 –4 were sufficient to cause increases in the charge trapping relative to pure PS dielectrics. We observed a pronounced inverse relationship between the capacity and stability of blended systems at larger mole fractions (χ = 10 –2 ) where the interadditive molecule distances became comparable to their size (~1 nm). Differences between MPDA and PATPA behaviors were consistent with their different structures and sizes. Furthermore, we found a small effect on electronic trapping arising from the chemical tethering of PATPA to the PS matrix. This result was consistent with the changes made to the additive during the tethering process and small compared to the observed differences arising from the concentration. These results suggest that the average intermolecular separation is a key determinant of charge storage stability in blended dielectrics.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Impact of 12-nm FinFET Technology Variations on TID Effects: A Comparative Study of GF 12LP and 12LP+ at the Transistor Level

Here, this article presents a comparative analysis of total ionizing dose (TID) response in GlobalFoundries’ (GF) 12 low-power (LP) and 12LP+12-nm bulk fin field effect transistor (FinFET) technologies using 10-keV X-rays. Our findings show that 12LP+ n-type transistors demonstrate higher sensitivity to TID degradation of the off-state leakage drain current compared to 12LP. Data indicate that for both 12LP and 12LP+, transistors with higher threshold voltages (VTs) exhibit lower off-state drain-source leakage postirradiation compared to transistors with lower VTs. Data consistently show that transistors with fewer fins per transistor show superior TID tolerance, in both 12LP and 12LP+ technologies. Lower VT transistors in both technologies display similar preirradiation leakage currents. On the other hand, higher VT transistors in 12LP+ show lower preirradiation leakage currents than those in 12LP, highlighting that the front-end-of-line of 12LP+ technology has been modified compared to 12LP. p-type devices in 12LP+ presented negligible degradation. Larger TID sensitivity in 12LP+ might be attributed to the implementation of dual-metal gate work functions, reduced halo doping, deeper source/drain (S/D) doping profiles, and/or 12LP+ having narrower fins compared to 12LP.

Dual-metal gate work functions↗
DOE OSTI2026

TCAD-Machine Learning Enabled TID Compact Model Development for Commercial SiC MOSFET

We propose a TCAD (Technology Computer Aided Design)-machine learning coupled approach that combines a TCAD tool (Charon), optimization/uncertainty quantification tool (Dakota), surrogate models, and Bayesian learning capabilities. The coupling approach is used for accurate modeling and calibration of total ionizing dose (TID) induced threshold voltage (V th ) shifts in Commercial-Off-The-Shelf (COTS) semiconductor devices and to develop physics-informed TID compact models. This versatile approach is applied to model the TID effect in an exemplar COTS 3.3 kV SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). With the Charon-Dakota coupling, we can determine key device geometry and doping values based on device physics, which are difficult to obtain or not available for COTS devices but important for TCAD simulation; additionally, we can efficiently generate thousands of simulation results in a large parameter space, which makes it possible to develop data-driven surrogate models and perform Bayesian calibration. Utilizing the full tool-coupling approach, we achieve calibrated TCAD simulation models that accurately capture the average TID-induced V th shifts behavior with total doses and V th shifts saturation at high doses as observed in experimental data. More importantly, the calibrated TCAD simulations are obtained with determined TID model parameters (e.g., hole trap density and capture cross section) values that contain well quantified uncertainties. Furthermore, we can isolate and quantify the noises that are not captured by the TCAD models but exist in the measured data due to measurements and devices variabilities. Lastly, the calibrated surrogate models are used to develop physics-informed TID compact models. The method is generalizable to other devices and/or radiation conditions with few modifications and can provide well-determined uncertainties.

COTS↗
DOE OSTI2025

Bypassing Fast Time Scales of the Hodgkin-Huxley Neuron Model via a Thresholded Hard Reset

We propose a modification to the Hodgkin-Huxley model to reduce the numerical stiffness of the equations by introducing an explicit voltage threshold. When this threshold is crossed, the voltage and the gating variables are reset to constant values. It is found that, for all of the current stimuli considered, the proposed model accurately reproduces the behavior of the baseline Hodgkin-Huxley model while bypassing the fast dynamics of spiking. Specifically, the model accurately reproduces the spike times and, between spikes, the time courses of the membrane potential and gating variables.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1982

Design, production, and testing of field effect transistors

Cryogenic MOSFETS (CRYOFETS), specifically designed for low temperature preamplifier application with infrared extrinsic detectors were produced and comparatively tested with p-channel MOSFETs under matched conditions. The CRYOFETs exhibit lower voltage thresholds, high source-follower gains at lower bias voltage, and lower dc offset source voltage. The noise of the CRYOFET is found to be 2 to 4 times greater than the MOSFET with a correspondingly lower figure of merit (which is established for source-follower amplifiers). The device power dissipation at a gain of 0.98 is some two orders of magnitude lower than for the MOSFET. Further, CRYOFETs are free of low temperature I vs V character hysteresis and balky conduction turn-on effects and operate effectively in the 2.4 to 20 K range. These devices have promise for use on long term duration sensor missions and for on-focal-plane signal processing at low temperatures.

Sclar, N.↗
NASA NTRS1987

Response of a metal-oxide-semiconductor field-effect transistor to a cosmic-ray ion track

A cosmic-ray ion track passing perpendicularly through the oxide layer of an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) forms a conducting path, the resistance of which is proportional to the stopping power of the cosmic ion and independent of the cross-sectional area of the ion track. The voltage across the oxide capacitance may drop below the threshold voltage if the gate bias is sufficiently low or if the external resistance in the gate-source circuit is sufficiently high. The first of a pair of MOSFETs forming a flip-flop circuit may thus be turned off, and the second transitor may turn on, providing it has a sufficiently short delay time, thereby completing a single-event upset.

Benumof, Reuben↗
DOE OSTI2024

Electron Spin Polarization in Large Electric Fields

This project investigated the effects of large electric fields on electron spin polarization in semiconductors, which is of interest for spin-based electronics (“spintronics”) and quantum information processing. It has been theoretically proposed that large electric fields could potentially preserve or amplify electron spin polarization, which would make it easier to generate, transport, and detect spin polarization in spin-based devices; however, previous measurements had not measured the response of electron spin polarization at large electric fields. During this project, methods to perform measurements of electron spin polarization at large electric fields were developed and performed using ultrafast time- and spatially-resolved magneto-optical spectroscopy, high-voltage pulses, and lock-in detection. The device geometry was engineered to reduce the threshold voltage required to reach the Gunn threshold, and the effect of optical illumination on the sample conductivity and Gunn oscillations was investigated. Electron spin polarization measurements were performed at electric fields up to and beyond the Gunn threshold for the device. The measurements showed that the electron spin polarization magnitude decreased with increasing electric field in the devices measured, and a spin amplification effect was not observed. However, these effects could potentially exist in a different material or in a material with a different doping concentration or in a different device geometry.

36 MATERIALS SCIENCE↗
NASA NTRS1987

High-Voltage Switch Containing (DI)2 Devices

Series switching diodes triggered on by passing above threshold voltage. High-voltage switch made by connecting multitude of deep-impurity, double-injection devices in series with each other and with another, triggerable high-voltage device such as thyristor. Device operates near ground potential to avoid insulation problems in triggering circuit.

Hanes, Maurice H.↗
NASA NTRS2011

Measuring Input Thresholds on an Existing Board

A critical PECL (positive emitter-coupled logic) interface to Xilinx interface needed to be changed on an existing flight board. The new Xilinx input interface used a CMOS (complementary metal-oxide semiconductor) type of input, and the driver could meet its thresholds typically, but not in worst-case, according to the data sheet. The previous interface had been based on comparison with an external reference, but the CMOS input is based on comparison with an internal divider from the power supply. A way to measure what the exact input threshold was for this device for 64 inputs on a flight board was needed. The measurement technique allowed an accurate measurement of the voltage required to switch a Xilinx input from high to low for each of the 64 lines, while only probing two of them. Directly driving an external voltage was considered too risky, and tests done on any other unit could not be used to qualify the flight board. The two lines directly probed gave an absolute voltage threshold calibration, while data collected on the remaining 62 lines without probing gave relative measurements that could be used to identify any outliers. The PECL interface was forced to a long-period square wave by driving a saturated square wave into the ADC (analog to digital converter). The active pull-down circuit was turned off, causing each line to rise rapidly and fall slowly according to the input s weak pull-down circuitry. The fall time shows up as a change in the pulse width of the signal ready by the Xilinx. This change in pulse width is a function of capacitance, pulldown current, and input threshold. Capacitance was known from the different trace lengths, plus a gate input capacitance, which is the same for all inputs. The pull-down current is the same for all inputs including the two that are probed directly. The data was combined, and the Excel solver tool was used to find input thresholds for the 62 lines. This was repeated over different supply voltages and temperatures to show that the interface had voltage margin under all worst case conditions. Gate input thresholds are normally measured at the manufacturer when the device is on a chip tester. A key function of this machine was duplicated on an existing flight board with no modifications to the nets to be tested, with the exception of changes in the FPGA program.

Kuperman, Igor↗
NASA NTRS1966

Digitally controlled pulse-level discriminator operates over wide voltage range

Low power drain discriminator circuit generates an output pulse when an input pulse exceeds a discrete digitally controlled threshold voltage. The discriminator operates over a wide linear or nonlinear range of threshold levels. It uses several amplifier stages ahead of a fixed-reference threshold detector.

Cancro, C. A.↗