Predicting Cognitive States Using Machine Learning Fusion Paradigms to Reduce Model Uncertainty
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machine learning↗
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A 2-to-48-MHz Phase-Locked Loop
A 2-to-48-MHz phase-locked loop (PLL), developed for the U.S. space program, meets or exceeds all space shuttle clock electrical interface requirements by taking as its reference a 2-to-48-MHz clock signal and outputting a phaselocked clock signal set at the same frequency as the reference clock with transistor- transistor logic (TTL) voltage levels. Because it is more adaptable than other PLLs, the new PLL can be used in industries that employ signaling devices and as a tool in future space missions. A conventional PLL consists of a phase/frequency detector, loop filter, and voltage-controlled oscillator in which each component exists individually and is integrated into a single device. PLL components phase-lock to a single frequency or to a narrow bandwidth of frequencies. It is this design, however, that prohibits them from maintaining phase lock to a dynamically changing reference clock when a large bandwidth is required a deficiency the new PLL overcomes. Since most PLL components require their voltage-controlled oscillators to operate at greater than 2-MHz frequencies, conventional PLLs often cannot achieve the low-frequency phase lock allowed by the new PLL. The 2-to-48-MHz PLL is built on a wire-wrap board with pins wired to three position jumpers; this makes changing configurations easy. It responds to variations in voltage-controlled oscillator (VCO) ranges, duty cycle, signal-to-noise ratio (SNR), amplitude, and jitter, exceeding design specifications. A consensus state machine, implemented in a VCO range detector which assures the PLL continues to operate in the correct range, is the primary control state machine for the 2-to-48-MHz PLL circuit. By using seven overlapping frequency ranges with hysteresis, the PLL output sets the resulting phase-locked clock signal at a frequency that agrees with the reference clock with TTL voltage levels. As a space-shuttle tool, the new PLL circuit takes the noisy, degraded reference clock signals as input and outputs phase-locked clock signals of the same frequency but with a corrected wave shape. Since its configuration circuit can be easily changed, the new PLL can do the following: readily respond to variations in VCO ranges, duty cycle, SNR, amplitude, and jitter; continuously operate in the correct VCO range because of its consensus state machine; and use its range detector implements to overlap seven frequency ranges with hysteresis, thus giving the current design a flexibility that exceeds anything available at the time of this development. These features will benefit any industry in which safe and timely clock signals are vital to operation.
Koudelka, Robert D.↗
Generating Real-Time Robotics Control Software from SysML
In this paper, we outline an approach for autogenerating real-time robotics control code from hierarchical state machines and hardware configurations encoded in Systems Modeling Language (SysML). We propose a software architecture that provides an abstract SysML layer with access to device state information and a set of primitive device commands, such as move actuator and release brake, allowing a user to build up a complete functional state machine directly in SysML. The SysML diagram is then exported to a standard SCXML file format and subsequently used to auto-generate hardware control code. Once this architecture is in place, the only explicit code elements that need to be written are the primitive device commands, which can be easily unit tested and reused across different systems. The motivation for this work was the need for a test bed that enables the rapid prototyping of mechanisms and control algorithms for a spacecraft that could ultimately be used for preparing Martian rock samples for their return to Earth. To this end, our software system was also designed to allow for the run-time specification of the hardware layout in SysML, with the hardware-level control functions kept agnostic to the specific parameters or communication bus of any particular device. Further, we outline a system for specifying both the state machine and hardware configuration in the MagicDraw IDE in such a way that the system can be simulated before any code is generated. The resultant software system is easy to debug, understand, and allows users to choose how much information is encoded as a visual or text-based representation.
Godart, Peter↗
Programmable Pulse-Position-Modulation Encoder
A programmable pulse-position-modulation (PPM) encoder has been designed for use in testing an optical communication link. The encoder includes a programmable state machine and an electronic code book that can be updated to accommodate different PPM coding schemes. The encoder includes a field-programmable gate array (FPGA) that is programmed to step through the stored state machine and code book and that drives a custom high-speed serializer circuit board that is capable of generating subnanosecond pulses. The stored state machine and code book can be updated by means of a simple text interface through the serial port of a personal computer.
Zhu, David↗
Intelligent fuzzy controller for event-driven real time systems
Most of the known linguistic models are essentially static, that is, time is not a parameter in describing the behavior of the object's model. In this paper we show a model for synchronous finite state machines based on fuzzy logic. Such finite state machines can be used to build both event-driven, time-varying, rule-based systems and the control unit section of a fuzzy logic computer. The architecture of a pipelined intelligent fuzzy controller is presented, and the linguistic model is represented by an overall fuzzy relation stored in a single rule memory. A VLSI integrated circuit implementation of the fuzzy controller is suggested. At a clock rate of 30 MHz, the controller can perform 3 MFLIPS on multi-dimensional fuzzy data.
Grantner, Janos↗
A Graphical User Interface for the Deep Underground Neutrino Experiment Robotic Test Stand
In preparation for DUNE, Fermilab along with six other institutions are testing cold electronics for quality control before components placed in the far detector. We test them by using a robotic arm that places these chips into sockets on a computer board that will test their functionality. Up until now, the chips have been tested using a command line script that drives a state machine to conduct tests step-by-step. In order to lower the skill barrier to conduct tests and to speed up the quality control process, I was tasked to create a graphical user interface that would allow users to use buttons, text boxes, and drop-down menus to input information and tell the testing state machine how to operate. I had to learn about the Python package Tkinter to start the process of widget placement. I further developed a pause feature unused in the previous command line script that would allow the user to shut down testing gracefully, bring the robotic arm to go back to ground state, and go forward or backward a step in the testing process. After completing the basic functionality of the GUI, I started testing production chips with the GUI to debug. Some issues were found, which required me to further develop parts of the inherited state machine code. The code for the GUI has now been pushed into the copy the DUNE/FD_CE git repository and will soon be merged with the official DUNE/FD_CE repository so that the other institutions testing DUNE cold electronics can use and expand upon it.
Gutierrez Villanueva, Jaziel [Fermilab]↗
Decidability for a temporal logic used in discrete-event system analysis
The type of plant considered is one that can be modeled by a nondeterministic finite-state machine P. The regulator is a deterministic finite state machine R. The closed-loop system is formed by connecting P and R in a regulator configuration. Formulas in a propositional temporal language are used to describe the behavior of the closed-loop system. It is shown that there is a mechanical procedure which, for a given P and R, and a temporal formula Psi, will determine in a finite number of steps whether or not Psi must be true. This 'decidability' result could be proven using other known results on temporal logic. The proof given here shows that the behavior of the closed-loop system may safely be assumed to be ultimately periodic. The results are illustrated on two discrete-event system examples.
Knight, J. F.↗
Onboard Decision-Making for Nominal and Contingency sUAS Flight
This study presents an onboard decision-making architecture for small unmanned aerial systems (sUAS). The decision-maker is part of NASA's SAFE50 project that is working under the UAS Traffic Management (UTM) Technical Capability Level (TCL) 4 to provide autonomous point-to-point UAV flight in BVLOS, high-density urban environments. The decision-maker monitors various metrics to determine the safety and feasibility of the mission and categorizes flight states as Nominal, Off-Nominal, Alternate Land, and Land Now in a finite state machine. Changes in the monitored metrics serve as transitions in the state machine and trigger replanning. Navigation degradation and communication failure are simulated to show the feasibility of the decision-maker framework in appropriately switching the flight state.
Baculi, Joshua↗
Predicting Cognitive States Using Machine Learning Fusion Paradigms to Reduce Model Uncertainty
The development of a synergetic system between humans and technology is a challenge that the scientific community has been facing for many years. Our aeronautic research aims to enhance this synergy between humans and machines through predictive human performance modeling for systems to mitigate high-risk situations. By being able to predict and anticipate human states, the crew monitoring system should be able to adjust and support the pilot for aviation safety. Our work focusing on attention-related human performance-limiting states (AHPLS) that impact a pilot’s performance and introduce high-risk catastrophic situations [1]. For example, AHPLS has been cited as a causal factor in more than 50% of all loss control in flight and thus contributes significantly toward commercial aviation fatalities [1, 2]. Cognitive state and its physiological fingerprint can be valuable information for this detecting AHPLS, but human cognitive state detection is still a major limitation for these crew monitoring systems.
machine learning↗
Development techniques for generic software
In developing the first version of a generic implementation of X.25, Levels 2 and 3, three development techniques are examined: table driven finite state machine implementation, an integrated testing environment, and top down design. A finite state machine (FSM) is a powerful tool for both specifying and implementing protocols. This technique was used in the X.25 specification. A table driven implementation of the FSM was chosen to facilitate changes and simplify coding. The effect that this technique have on program size, speed of execution, coding time, and debugging time are investigated.
Hamilton, R. L.↗
Pass-transistor asynchronous sequential circuits
Design methods for asynchronous sequential pass-transistor circuits, which result in circuits that are hazard- and critical-race-free and which have added degrees of freedom for the input signals, are discussed. The design procedures are straightforward and easy to implement. Two single-transition-time state assignment methods are presented, and hardware bounds for each are established. A surprising result is that the hardware realizations for each next state variable and output variable is identical for a given flow table. Thus, a state machine with N states and M outputs can be constructed using a single layout replicated N + M times.
Whitaker, Sterling R.↗
A programmable architecture for CMOS sequential circuits
This paper presents a programmable architecture for sequential pass transistor circuits. The resulting circuits are such that a state machine with N states and M output is constructed using a single layout replicated N + M times.
Whitaker, S.↗
FPGA-Based X-Ray Detection and Measurement for an X-Ray Polarimeter
This technology enables detection and measurement of x-rays in an x-ray polarimeter using a field-programmable gate array (FPGA). The technology was developed for the Gravitational and Extreme Magnetism Small Explorer (GEMS) mission. It performs precision energy and timing measurements, as well as rejection of non-x-ray events. It enables the GEMS polarimeter to detect precisely when an event has taken place so that additional measurements can be made. The technology also enables this function to be performed in an FPGA using limited resources so that mass and power can be minimized while reliability for a space application is maximized and precise real-time operation is achieved. This design requires a low-noise, charge-sensitive preamplifier; a highspeed analog to digital converter (ADC); and an x-ray detector with a cathode terminal. It functions by computing a sum of differences for time-samples whose difference exceeds a programmable threshold. A state machine advances through states as a programmable number of consecutive samples exceeds or fails to exceed this threshold. The pulse height is recorded as the accumulated sum. The track length is also measured based on the time from the start to the end of accumulation. For track lengths longer than a certain length, the algorithm estimates the barycenter of charge deposit by comparing the accumulator value at the midpoint to the final accumulator value. The design also employs a number of techniques for rejecting background events. This innovation enables the function to be performed in space where it can operate autonomously with a rapid response time. This implementation combines advantages of computing system-based approaches with those of pure analog approaches. The result is an implementation that is highly reliable, performs in real-time, rejects background events, and consumes minimal power.
Gregory, Kyle↗
Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)
A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.
97 MATHEMATICS AND COMPUTING↗
Development of a Smart Alarm System for the CEBAF Injector
RadiaSoft and Jefferson Laboratory are working together to develop a machine-learning-based smart alarm system for the CEBAF injector. Because of the injector’s large number of parameters and possible fault scenarios, it is highly desirable to have an autonomous alarm system that can quickly identify and diagnose unusual machine states. We present our work on artificial neural networks designed to identify such undesirable machine states. In particular, we test both auto-encoders and inverse models as possible tools for differentiating between normal and abnormal states. These models are being developed using both supervised and unsupervised learning techniques, and are being trained using CEBAF injector data collected during dedicated machine studies as well as during regular operations. Lastly, we discuss tradeoffs between the two types of models.
Abell, D. T.↗
Aspect-Oriented Monitoring of C Programs
The paper presents current work on extending ASPECTC with state machines, resulting in a framework for aspect-oriented monitoring of C programs. Such a framework can be used for testing purposes, or it can be part of a fault protection strategy. The long term goal is to explore the synergy between the fields of runtime verification, focused on program monitoring, and aspect-oriented programming, focused on more general program development issues. The work is inspired by the observation that most work in this direction has been done for JAVA, partly due to the lack of easily accessible extensible compiler frameworks for C. The work is performed using the SILVER extensible attribute grammar compiler framework, in which C has been defined as a host language. Our work consists of extending C with ASPECTC, and subsequently to extend ASPECTC with state machines.
runtime verifications↗
A Smart Alarm for the CEBAF Injector
We present initial results from a proof-of-concept ?smart alarm? for the CEBAF injector. Because of the injector's large number of parameters and possible fault scenarios, it is highly desirable to have an autonomous alarm system that can quickly identify and diagnose unusual machine states. Our approach leverages a trained neural network to not only identify an anomalous machine state, but also to identify the root-cause by pinpointing the specific element or region responsible. We developed an inverse model trained on data collected during normal operations. Using the inverse model, measurements from the machine are used to compute machine settings, which are then compared to EPICS setpoints. Instances when predictions differ from EPICS setpoints by a user-defined threshold are flagged as anomalies, and the user is alerted to the issue. We present the results of our data collection efforts, model training and performance, and initial performance metrics.
Tennant, C.↗
Pulse Generator
An apparatus and a computer-implemented method for generating pulses synchronized to a rising edge of a tachometer signal from rotating machinery are disclosed. For example, in one embodiment, a pulse state machine may be configured to generate a plurality of pulses, and a period state machine may be configured to determine a period for each of the plurality of pulses.
Greer, Lawrence↗