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NASA NTRS2003

Fault Creep along the Southern San Andreas from Interferometric Synthetic Aperture Radar, Permanent Scatterers, and Stacking

Interferometric synthetic aperture radar (InSAR) provides a practical means of mapping creep along major strike-slip faults. The small amplitude of the creep signal (less than 10 mm/yr), combined with its short wavelength, makes it difficult to extract from long time span interferograms, especially in agricultural or heavily vegetated areas. We utilize two approaches to extract the fault creep signal from 37 ERS SAR images along the southem San Andreas Fault. First, amplitude stacking is utilized to identify permanent scatterers, which are then used to weight the interferogram prior to spatial filtering. This weighting improves correlation and also provides a mask for poorly correlated areas. Second, the unwrapped phase is stacked to reduce tropospheric and other short-wavelength noise. This combined processing enables us to recover the near-field (approximately 200 m) slip signal across the fault due to shallow creep. Displacement maps fiom 60 interferograms reveal a diffuse secular strain buildup, punctuated by localized interseismic creep of 4-6 mm/yr line of sight (LOS, 12-18 mm/yr horizontal). With the exception of Durmid Hill, this entire segment of the southern San Andreas experienced right-lateral triggered slip of up to 10 cm during the 3.5-year period spanning the 1992 Landers earthquake. The deformation change following the 1999 Hector Mine earthquake was much smaller (4 cm) and broader than for the Landers event. Profiles across the fault during the interseismic phase show peak-to-trough amplitude ranging from 15 to 25 mm/yr (horizontal component) and the minimum misfit models show a range of creeping/locking depth values that fit the data.

Lyons, Suzanne↗

NASA NTRS1993

Experimental evaluation of the certification-trail method

Certification trails are a recently introduced and promising approach to fault-detection and fault-tolerance. A comprehensive attempt to assess experimentally the performance and overall value of the method is reported. The method is applied to algorithms for the following problems: huffman tree, shortest path, minimum spanning tree, sorting, and convex hull. Our results reveal many cases in which an approach using certification-trails allows for significantly faster overall program execution time than a basic time redundancy-approach. Algorithms for the answer-validation problem for abstract data types were also examined. This kind of problem provides a basis for applying the certification-trail method to wide classes of algorithms. Answer-validation solutions for two types of priority queues were implemented and analyzed. In both cases, the algorithm which performs answer-validation is substantially faster than the original algorithm for computing the answer. Next, a probabilistic model and analysis which enables comparison between the certification-trail method and the time-redundancy approach were presented. The analysis reveals some substantial and sometimes surprising advantages for ther certification-trail method. Finally, the work our group performed on the design and implementation of fault injection testbeds for experimental analysis of the certification trail technique is discussed. This work employs two distinct methodologies, software fault injection (modification of instruction, data, and stack segments of programs on a Sun Sparcstation ELC and on an IBM 386 PC) and hardware fault injection (control, address, and data lines of a Motorola MC68000-based target system pulsed at logical zero/one values). Our results indicate the viability of the certification trail technique. It is also believed that the tools developed provide a solid base for additional exploration.

Sullivan, Gregory F.↗

NASA NTRS1998

Implementing Falut Tolerance in the COTS-Based X2000 Architecture: A Case Study on IEEE 1394

Among other challenges from NASA's X2000 Technology Development Program, affordability and miniaturizaton are prominent criteria, which 1) preclude the traditional solutions for mission reliability that rely on customer-built hardware and extensive component/subsystem replication, and 2) call for commercial-of-the-shelf (COTS) based approaches incorporating novel, practical fault tolerance techniques.

IEEE 1394 bus interface commercial-off-th-shelf sp↗

NASA NTRS2000

The Design of a Fault-Tolerant COTS-Based Bus Architecture for Space Applications

The high-performance, scalability and miniaturization requirements together with the power, mass and cost constraints mandate the use of commercial-off-the-shelf (COTS) components and standards in the X2000 avionics system architecture for deep-space missions. In this paper, we report our experiences and findings on the design of an IEEE 1394 compliant fault-tolerant COTS-based bus architecture. While the COTS standard IEEE 1394 adequately supports power management, high performance and scalability, its topological criteria impose restrictions on fault tolerance realization. To circumvent the difficulties, we derive a "stack-tree" topology that not only complies with the IEEE 1394 standard but also facilitates fault tolerance realization in a spaceborne system with limited dedicated resource redundancies. Moreover, by exploiting pertinent standard features of the 1394 interface which are not purposely designed for fault tolerance, we devise a comprehensive set of fault detection mechanisms to support the fault-tolerant bus architecture.

Chau, Savio N.↗

NASA NTRS1988

Applicative architectures for fault-tolerant multiprocessors

This paper proposes functional programming frameworks for the design of highly reliable multiprocessor systems. In contrast to imperative programming environments, a functional environment offers elegant, relatively simple, and efficient solutions to concurrent error detection and recovery problems in multiprocessors. Specific fault tolerance mechanisms for upset exposure, fault containment, secure task assignment, and recovery are developed for a class of applicative multiprocessor architectures. Verification of abstract behavioral characteristics of applicative tasks is used for exposing faults during the execution of tasks. The fault containment mechanism is based on isolation of stack and heap segments of tasks. A protocol for secure task assignment is defined between system components. The architecture permits incremental, distributed, and asynchronous backups of system state. Finally, recovery is accomplished, even in the worst cases, by reexecution of a small number of tasks.

Sharma, Madhumitra↗

NASA NTRS1987

Applicative architectures for fault-tolerant multiprocessors

Functional programming frameworks for the design of highly reliable multiprocessor systems are proposed. In contrast to imperative programming environments, a functional environment offers elegant, relatively simple, and efficient solutions to concurrent error detection and recovery problems in multiprocessors. Specific fault tolerance mechanisms for upset exposure, fault containment, secure task assignment, and recovery are developed for a class of applicative multiprocessor architectures. Verification of abstract behavioral characteristics of applicative tasks is used for exposing faults during the execution of tasks. The fault containment mechanism is based on isolation of stack and heap segments of tasks. A protocol for secure task assignment is defined between system components. The architecture permits incremental, distributed, and asynchronous backups of system state. Finally, recovery is accomplished, even in the worst cases, by re-execution of a small number of tasks.

Sharma, Madhumitra↗

NASA NTRS1972

Identification of geostructures of continental crust particularly as they relate to mineral resource evaluation

The author has identified the following significant results. Preliminary examination of ERTS-1 imagery in central and northern Alaska substantiates the existence of a conjugate set of northeast and northwest faults suggested by linears noted on Nimbus 4 images. Linears of both trends are well expressed and several have been mapped as faults, including the Shaw Creek fault. Imagery provides new data to support the interpretation that the Kobuk Trench is the northern margin of a broad west-trending fault zone bounded on the north and south by strike-slip faults. In northwestern Alaska, MSS band 5 imagery shows Mississippian limestone as white, while shale, sandstone, and chert of other ages appear dark. As the limestone is the basal formation of the numerous thrust plates stacked in the area, images of band 5 will assist significantly in depicting the distribution of the thrust plates. In south-central Alaska the newly described Totshunda fault is readily identified and extends into areas not yet mapped. Also shown is another fault parallel to the south of the Totshunda which has not yet been recognized in the field.

Gryc, G.↗

NASA NTRS1991

Magnetic end effectors for space operations

The Magnetic End Effector (MEE) to be flown as part of the Dexterous End Effector (DEE) flight experiment was designed to operate with the Shuttle Remote Manipulator System (SRMS). Grappling or attachment of payloads is accomplished magnetically with two fault tolerant operations. The small magnetic grapple plate weighs far less than the standard grapple fixture; allows stacking and close spacing of payloads; and eliminates secondary release mechanisms. In addition to specifics regarding the MEE, the DEE project, Magnetic Attachment Tool (MAT), RMS-Force Torque Sensor (RMS-FTS), and Targeting and Reflective Alignment Concept (TRAC) are discussed.

Monford, Leo↗

NASA NTRS2004

NASA Tech Briefs, August 2004

Topics covered include: Data Relay Board with Protocol for High-Speed, Free-Space Optical Communications; Software and Algorithms for Biomedical Image Data Processing and Visualization; Rapid Chemometric Filtering of Spectral Data; Prioritizing Scientific Data for Transmission; Determining Sizes of Particles in a Flow from DPIV Data; Faster Processing for Inverting GPS Occultation Data; FPGA-Based, Self-Checking, Fault-Tolerant Computers; Ultralow-Power Digital Correlator for Microwave Polarimetry; Grounding Headphones for Protection Against ESD; Lightweight Stacks of Direct Methanol Fuel Cells; Highly Efficient Vector-Inversion Pulse Generators; Estimating Basic Preliminary Design Performances of Aerospace Vehicles; Framework for Development of Object-Oriented Software; Analyzing Spacecraft Telecommunication Systems; Collaborative Planning of Robotic Exploration; Tools for Administration of a UNIX-Based Network; Preparing and Analyzing Iced Airfoils; Evaluating Performance of Components; Fuels Containing Methane of Natural Gas in Solution; Direct Electrolytic Deposition of Mats of MnxOy Nanowires; Bubble Eliminator Based on Centrifugal Flow; Inflatable Emergency Atmospheric-Entry Vehicles; Lightweight Deployable Mirrors with Tensegrity Supports; Centrifugal Adsorption Cartridge System; Ultrasonic Apparatus for Pulverizing Brittle Material; Transplanting Retinal Cells using Bucky Paper for Support; Using an Ultrasonic Instrument to Size Extravascular Bubbles; Coronagraphic Notch Filter for Raman Spectroscopy; On-the-Fly Mapping for Calibrating Directional Antennas; Working Fluids for Increasing Capacities of Heat Pipes; Computationally-Efficient Minimum-Time Aircraft Routes in the Presence of Winds; Liquid-Metal-Fed Pulsed Plasma Thrusters; Personal Radiation Protection System; and Attitude Control for a Solar-Sail Spacecraft.

Source record↗

NASA NTRS2019

Challenges Using the Linux Network Stack for Real-Time Communication

Starting in the early 2000s, human-in-the-loop (HITL) simulation groups at NASA and the Air Force Research Lab began using the Linux network stack for some real-time communication. More recently, SpaceX has adopted Ethernet as the primary bus technology for its Falcon launch vehicles and Dragon capsules. As the Linux network stack makes its way from ground facilities to flight critical systems, it is necessary to recognize that the network stack is optimized for communication over the open Internet, which cannot provide latency guarantees. The Internet protocols and their implementation in the Linux network stack contain numerous design decisions that favor throughput over determinism and latency. These decisions often require workarounds in the application or customization of the stack to maintain a high probability of low latency on closed networks, especially if the network must be fault tolerant to single event upsets.

Madden, Michael M.↗

NASA NTRS1992

A set-associative, fault-tolerant cache design

The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the Least Recently Used (LRU) replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.

Lamet, Dan↗

NASA NTRS2011

Imaging the Moon's Core with Seismology

Constraining the structure of the lunar core is necessary to improve our understanding of the present-day thermal structure of the interior and the history of a lunar dynamo, as well as the origin and thermal and compositional evolution of the Moon. We analyze Apollo deep moonquake seismograms using terrestrial array processing methods to search for the presence of reflected and converted energy from the lunar core. Although moonquake fault parameters are not constrained, we first explore a suite of theoretical focal spheres to verify that fault planes exist that can produce favorable core reflection amplitudes relative to direct up-going energy at the Apollo stations. Beginning with stacks of event seismograms from the known distribution of deep moonquake clusters, we apply a polarization filter to account for the effects of seismic scattering that (a) partitions energy away from expected components of ground motion, and (b) obscures all but the main P- and S-wave arrivals. The filtered traces are then shifted to the predicted arrival time of a core phase (e.g. PcP) and stacked to enhance subtle arrivals associated with the Moon s core. This combination of filtering and array processing is well suited for detecting deep lunar seismic reflections, since we do not expect scattered wave energy from near surface (or deeper) structure recorded at varying epicentral distances and stations from varying moonquakes at varying depths to stack coherently. Our results indicate the presence of a solid inner and fluid outer core, overlain by a partial-melt-containing boundary layer (Table 1). These layers are consistently observed among stacks from four classes of reflections: P-to-P, S-to-P, P-to-S, and S-to-S, and are consistent with current indirect geophysical estimates of core and deep mantle properties, including mass, moment of inertia, lunar laser ranging, and electromagnetic induction. Future refinements are expected following the successful launch of the GRAIL lunar orbiter and SELENE 2 lunar lander missions.

Weber, Renee C.↗

NASA NTRS2001

The Mountains of Io: Global and Geological Perspectives from Voyager and Galileo

To search for local and global scale geologic associations that may be related to the internal dynamics of Io, we have completed a global catalog of all mountains and volcanic centers. We have identified 115 mountain structures (covering approx. 3% of the surface) and 541 volcanic centers, including paterae (calderas and dark spots) and shield volcanoes. The average length of an Ionian mountain is 157 km, with the longest being 570 km. The mean height of Ionian mountains is 6.3 km, and the highest known mountain is Boosaule Montes (17.5 +/- 3 km). Five basic morphologic types of mountains have been identified; mesa, plateau peak, ridge, and massif. Very few mountains bear any physical similarity. to classic volcanic landforms, but many resemble flatiron mountains on Earth and are interpreted as tilted crustal blocks. This would be consistent with the hypothesis that most mountains are thrust blocks formed as a result of compressive stresses built up in the lower crust due to the global subsidence of volcanic layers as they are buried over time. More than one mechanism may be responsible for all Ionian mountains, however. The proximity of some mountains to paterae may indicate a direct link between some mountains and volcanism, although it is not always clear which came first. In contrast to earlier studies, a pronounced bimodal pattern is observed in the global distribution of both mountains and volcanic centers. The regions of highest areal densities of volcanic centers are near the sub- and anti-Jovian regions, but are offset roughly 90deg in longitude from the two, regions of greatest concentration of mountains. This anticorrelation may indicate the overprinting of a second stress field on the global compressive stresses due to subsidence. The bimodal distribution of volcanic centers and mountains is consistent with models of asthenospheric tidal heating and internal convection developed by Tackley et al.Over regions of mantle upwelling, compressive stresses in the lower crust induced by global subsidence might be reduced, encouraging volcanism and discouraging mountain building. In regions of mantle downwelling, these compressive stresses in the lower crust might be increased, discouraging volcanism and encouraging mountain building. Alternatively, the global pattern may be related to possible (but undocumented) nonsynchronous rotation of lo, which would produce two regions each of compression and extension in the crust. Evidence of layering and of mass wasting, including landslides, block sliding, debris aprons and downslope creep, on Ionian mountains suggests that the crust of Io is essentially a layered stack of partially consolidated volcanic lavas and plume deposits, becoming more consolidated with depth. The lower crust especially may also be ductily deformed, punctuated by volcanic intrusions and faulting at paterae, and broken into blocks, some of which have been uplifted to form mountains.

Schenk, Paul↗

NASA NTRS1990

Error recovery in shared memory multiprocessors using private caches

The problem of recovering from processor transient faults in shared memory multiprocesses systems is examined. A user-transparent checkpointing and recovery scheme using private caches is presented. Processes can recover from errors due to faulty processors by restarting from the checkpointed computation state. Implementation techniques using checkpoint identifiers and recovery stacks are examined as a means of reducing performance degradation in processor utilization during normal execution. This cache-based checkpointing technique prevents rollback propagation, provides rapid recovery, and can be integrated into standard cache coherence protocols. An analytical model is used to estimate the relative performance of the scheme during normal execution. Extensions to take error latency into account are presented.

Wu, Kun-Lung↗

NASA NTRS1991

High-power converters for space applications

Phase 1 was a concept definition effort to extend space-type dc/dc converter technology to the megawatt level with a weight of less than 0.1 kg/kW (220 lb./MW). Two system designs were evaluated in Phase 1. Each design operates from a 5 kV stacked fuel cell source and provides a voltage step-up to 100 kV at 10 A for charging capacitors (100 pps at a duty cycle of 17 min on, 17 min off). Both designs use an MCT-based, full-bridge inverter, gaseous hydrogen cooling, and crowbar fault protection. The GE-CRD system uses an advanced high-voltage transformer/rectifier filter is series with a resonant tank circuit, driven by an inverter operating at 20 to 50 kHz. Output voltage is controlled through frequency and phase shift control. Fast transient response and stability is ensured via optimal control. Super-resonant operation employing MCTs provides the advantages of lossless snubbing, no turn-on switching loss, use of medium-speed diodes, and intrinsic current limiting under load-fault conditions. Estimated weight of the GE-CRD system is 88 kg (1.5 cu ft.). Efficiency of 94.4 percent and total system loss is 55.711 kW operating at 1 MW load power. The Maxwell system is based on a resonance transformer approach using a cascade of five LC resonant sections at 100 kHz. The 5 kV bus is converted to a square wave, stepped-up to a 100 kV sine wave by the LC sections, rectified, and filtered. Output voltage is controlled with a special series regulator circuit. Estimated weight of the Maxwell system is 83.8 kg (4.0 cu ft.). Efficiency is 87.2 percent and total system loss is 146.411 kW operating at 1 MW load power.

Park, J. N.↗

NASA NTRS2008

Update on Development of SiC Multi-Chip Power Modules

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Lostetter, Alexander↗

NASA NTRS2007

SiC Multi-Chip Power Modules as Power-System Building Blocks

The term "SiC MCPMs" (wherein "MCPM" signifies "multi-chip power module") denotes electronic power-supply modules containing multiple silicon carbide power devices and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking. Moreover, the higher-temperature capabilities of SiC MCPMs could enable operation in environments hotter than Si-based power systems can withstand. The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules. In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications: typical functions could include regulating voltages, storing energy, and driving motors. Because identical SiC MCPM building blocks could be utilized in a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. Several prototype DC-to-DC power-converter modules containing SiC power-switching devices were designed and built to demonstrate the feasibility of the SiC MCPM concept. In anticipation of a future need for operation at high temperature, the circuitry in the modules includes high-temperature inductors and capacitors. These modules were designed to be stacked to construct a system of four modules electrically connected in series and/or parallel. The packaging of the modules is designed to satisfy requirements for series and parallel interconnection among modules, high power density, high thermal efficiency, small size, and light weight. Each module includes four output power connectors two for serial and two for parallel output power connections among the modules. Each module also includes two signal connectors, electrically isolated from the power connectors, that afford four zones for signal interconnections among the SOI controllers. Finally, each module includes two input power connectors, through which it receives power from an in-line power bus. This design feature is included in anticipation of a custom-designed power bus incorporating sockets compatible with snap-on type connectors to enable rapid replacement of failed modules.

Lostetter, Alexander↗

NASA NTRS1993

The Application of Microtechnology to Spacecraft On-Board Computing(abstract)

In this report, we will survey recent advances in chip packaging and stacking techniques that allow miniature computers to be developed for space applications. Several orders of magnitude reduction in mass, volume, and power consumption are possible using these techniques. Moreover, performance improvements can be achieved by increasing the scale of multiprocessing. Most importantly, long-term survivability can potentially be improved by increasing the level of redundancy and fault tolerance.

microtechnology computers multiprocessing packagin↗