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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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78 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

Iridium Interfacial Stack - IrIS

Iridium Interfacial Stack (IrIS) is the sputter deposition of high-purity tantalum silicide (TaSi2-400 nm)/platinum (Pt-200 nm)/iridium (Ir-200 nm)/platinum (Pt-200 nm) in an ultra-high vacuum system followed by a 600 C anneal in nitrogen for 30 minutes. IrIS simultaneously acts as both a bond metal and a diffusion barrier. This bondable metallization that also acts as a diffusion barrier can prevent oxygen from air and gold from the wire-bond from infiltrating silicon carbide (SiC) monolithically integrated circuits (ICs) operating above 500 C in air for over 1,000 hours. This TaSi2/Pt/Ir/Pt metallization is easily bonded for electrical connection to off-chip circuitry and does not require extra anneals or masking steps. There are two ways that IrIS can be used in SiC ICs for applications above 500 C: it can be put directly on a SiC ohmic contact metal, such as Ti, or be used as a bond metal residing on top of an interconnect metal. For simplicity, only the use as a bond metal is discussed. The layer thickness ratio of TaSi2 to the first Pt layer deposited thereon should be 2:1. This will allow Si from the TaSi2 to react with the Pt to form Pt2Si during the 600 C anneal carried out after all layers have been deposited. The Ir layer does not readily form a silicide at 600 C, and thereby prevents the Si from migrating into the top-most Pt layer during future anneals and high-temperature IC operation. The second (i.e., top-most) deposited Pt layer needs to be about 200 nm to enable easy wire bonding. The thickness of 200 nm for Ir was chosen for initial experiments; further optimization of the Ir layer thickness may be possible via further experimentation. Ir itself is not easily wire-bonded because of its hardness and much higher melting point than Pt. Below the iridium layer, the TaSi2 and Pt react and form desired Pt2Si during the post-deposition anneal while above the iridium layer remains pure Pt as desired to facilitate easy and strong wire-bonding to the SiC chip circuitry.

Spry, David↗
NASA NTRS2019

Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits

While NASA Glenn Research Center's "Generation 10" 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100- and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.

Spry, D. J.↗
DOE OSTI2021

srMO-BO-3GP: A sequential regularized multi-objective Bayesian optimization for constrained design applications using an uncertain Pareto classifier

Bayesian optimization (BO) is an efficient and flexible global optimization framework that is applicable to a very wide range of engineering applications. To leverage the capability of the classical BO, many extensions, including multi-objective, multi-fidelity, parallelization, and latent-variable modeling, have been proposed to address the limitations of the classical BO framework. In this work, we propose a novel multi-objective BO formalism, called srMO-BO-3GP, to solve multi-objective optimization problems in a sequential setting. Three different Gaussian processes (GPs) are stacked together, where each of the GPs is assigned with a different task. The first GP is used to approximate a single-objective computed from the multi-objective definition, the second GP is used to learn the unknown constraints, and the third one is used to learn the uncertain Pareto frontier. At each iteration, a multi-objective augmented Tchebycheff function is adopted to convert multi-objective to single-objective, where the regularization with a regularized ridge term is also introduced to smooth the single-objective function. Finally, we couple the third GP along with the classical BO framework to explore the convergence and diversity of the Pareto frontier by the acquisition function for exploitation and exploration. The proposed framework is demonstrated using several numerical benchmark functions, as well as a thermomechanical finite element model for flip-chip package design optimization.

42 ENGINEERING↗
NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗
NASA NTRS2004

Advanced Manufacturing Techniques Demonstrated for Fabricating Developmental Hardware

NASA Glenn Research Center's Engineering Development Division has been working in support of innovative gas turbine engine systems under development by Glenn's Combustion Branch. These one-of-a-kind components require operation under extreme conditions. High-temperature ceramics were chosen for fabrication was because of the hostile operating environment. During the designing process, it became apparent that traditional machining techniques would not be adequate to produce the small, intricate features for the conceptual design, which was to be produced by stacking over a dozen thin layers with many small features that would then be aligned and bonded together into a one-piece unit. Instead of using traditional machining, we produced computer models in Pro/ENGINEER (Parametric Technology Corporation (PTC), Needham, MA) to the specifications of the research engineer. The computer models were exported in stereolithography standard (STL) format and used to produce full-size rapid prototype polymer models. These semi-opaque plastic models were used for visualization and design verification. The computer models also were exported in International Graphics Exchange Specification (IGES) format and sent to Glenn's Thermal/Fluids Design & Analysis Branch and Applied Structural Mechanics Branch for profiling heat transfer and mechanical strength analysis.

Redding, Chip↗
DOE OSTI2025

A gravity-based mounting approach for large-scale cryogenic calorimeter arrays

Cryogenic calorimeters are among the leading technologies for searching for rare events. The CUPID experiment is exploiting this technology to deploy a tonne-scale detector to search for neutrinoless double-beta decay of 100 Mo. The CUPID collaboration proposed an innovative approach to assembling cryogenic calorimeters in a stacked configuration, held in position solely by gravity. This gravity-based assembly method is unprecedented in the field of cryogenic calorimeters and offers several advantages, including relaxed mechanical tolerances and simplified construction. To assess and optimize its performance, we constructed a medium-scale prototype hosting 28 Li 2 MoO 4 crystals and 30 Ge light detectors, both operated as cryogenic calorimeters at the Laboratori Nazionali del Gran Sasso (Italy). Despite an unexpected excess of noise in the light detectors, the results of this test proved (i) a thermal stability better than ±0.5 mK at 10 mK, (ii) a good energy resolution of Li 2 MoO 4 cryogenic calorimeters, (6.6 ± 2.2) keV FWHM at 2615 keV, and (iii) a Li 2 MoO 4 light yield measured by the closest light detector of 0.36 keV/MeV, sufficient to guarantee the particle identification requested by CUPID.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗