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At least 91 records · Page 5

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NASA NTRS1983

Clamp-mount device

A clamp-mount device is disclosed for mounting equipment to an associated I-beam and the like structural member of the type having oppositely extending flanges wherein the device comprises a base and a pair of oppositely facing clamping members carried diagonally on the base clamping flanges therebetween and having flange receiving openings facing one another. Lock means are carried diagonally by the base opposite the clamping members locking the flanges in the clamping members. A resilient hub is carried centrally of the base engaging and biasing a back side of the flanges maintaining tightly clamped and facilitating use on vertical as well as horizontal members. The base turns about the hub to receive the flanges within the clamping members. Equipment may be secured to the base by any suitable means such as bolts in openings. Slidable gate latches secure the hinged locks in an upright locking position. The resilient hub includes a recess opening formed in the base and a rubber-like pad carried in this opening being depressably and rotatably carried therein.

Clark, K. H.↗

NASA NTRS1984

NSC 800, 8-bit CMOS microprocessor

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.↗

NASA NTRS2011

NASA Tech Briefs, September 2011

Topics covered include: Fused Reality for Enhanced Flight Test Capabilities; Thermography to Inspect Insulation of Large Cryogenic Tanks; Crush Test Abuse Stand; Test Generator for MATLAB Simulations; Dynamic Monitoring of Cleanroom Fallout Using an Air Particle Counter; Enhancement to Non-Contacting Stress Measurement of Blade Vibration Frequency; Positively Verifying Mating of Previously Unverifiable Flight Connectors; Radiation-Tolerant Intelligent Memory Stack - RTIMS; Ultra-Low-Dropout Linear Regulator; Excitation of a Parallel Plate Waveguide by an Array of Rectangular Waveguides; FPGA for Power Control of MSL Avionics; UAVSAR Active Electronically Scanned Array; Lockout/Tagout (LOTO) Simulator; Silicon Carbide Mounts for Fabry-Perot Interferometers; Measuring the In-Process Figure, Final Prescription, and System Alignment of Large; Optics and Segmented Mirrors Using Lidar Metrology; Fiber-Reinforced Reactive Nano-Epoxy Composites; Polymerization Initiated at the Sidewalls of Carbon Nanotubes; Metal-Matrix/Hollow-Ceramic-Sphere Composites; Piezoelectrically Enhanced Photocathodes; Iridium-Doped Ruthenium Oxide Catalyst for Oxygen Evolution; Improved Mo-Re VPS Alloys for High-Temperature Uses; Data Service Provider Cost Estimation Tool; Hybrid Power Management-Based Vehicle Architecture; Force Limit System; Levitated Duct Fan (LDF) Aircraft Auxiliary Generator; Compact, Two-Sided Structural Cold Plate Configuration; AN Fitting Reconditioning Tool; Active Response Gravity Offload System; Method and Apparatus for Forming Nanodroplets; Rapid Detection of the Varicella Zoster Virus in Saliva; Improved Devices for Collecting Sweat for Chemical Analysis; Phase-Controlled Magnetic Mirror for Wavefront Correction; and Frame-Transfer Gating Raman Spectroscopy for Time-Resolved Multiscalar Combustion Diagnostics.

Source record↗

NASA NTRS2007

Flight Qualified Micro Sun Sensor

A prototype small, lightweight micro Sun sensor (MSS) has been flight qualified as part of the attitude-determination system of a spacecraft or for Mars surface operations. The MSS has previously been reported at a very early stage of development in NASA Tech Briefs, Vol. 28, No. 1 (January 2004). An MSS is essentially a miniature multiple-pinhole electronic camera combined with digital processing electronics that functions analogously to a sundial. A micromachined mask containing a number of microscopic pinholes is mounted in front of an active-pixel sensor (APS). Electronic circuits for controlling the operation of the APS, readout from the pixel photodetectors, and analog-to-digital conversion are all integrated onto the same chip along with the APS. The digital processing includes computation of the centroids of the pinhole Sun images on the APS. The spacecraft computer has the task of converting the Sun centroids into Sun angles utilizing a calibration polynomial. The micromachined mask comprises a 500-micron-thick silicon wafer, onto which is deposited a 57-nm-thick chromium adhesion- promotion layer followed by a 200-nm-thick gold light-absorption layer. The pinholes, 50 microns in diameter, are formed in the gold layer by photolithography. The chromium layer is thin enough to be penetrable by an amount of Sunlight adequate to form measurable pinhole images. A spacer frame between the mask and the APS maintains a gap of .1 mm between the pinhole plane and the photodetector plane of the APS. To minimize data volume, mass, and power consumption, the digital processing of the APS readouts takes place in a single field-programmable gate array (FPGA). The particular FPGA is a radiation- tolerant unit that contains .32,000 gates. No external memory is used so the FPGA calculates the centroids in real time as pixels are read off the APS with minimal internal memory. To enable the MSS to fit into a small package, the APS, the FPGA, and other components are mounted on a single two-sided board following chip-on-board design practices

Liebe, Carl Christian↗

DOE OSTI2024

Sulfonated Aromatic Polypentenamers: Scope of the Acetyl Sulfate Reaction

A precision polymer featuring one phenyl pendant at every fifth carbon on a polyethylene backbone was modified to varying degrees of sulfonation (DS = 33–98%) using acetyl sulfate with standard conditions by varying reaction times (up to 48 h). This soft, homogeneous method allows for evenly distributed phenylsulfonic acid groups with minimal side reactions and results in light brown, transparent materials with glass transition temperatures of 33–78 °C that increase with DS and parent polymer molar mass. The DS was accurately determined through well-resolved 1 H NMR (DSHNMR) signals of the regularly spaced phenyl groups and corroborated by inverse-gated decoupling 13 C NMR analysis. These analyses were compared to a series of other commonly accepted methods for DS determination including titration and elemental analysis (EA). The DS by titration (DS titr ) also increased with reaction time but was consistently lower than those determined by NMR. Significant discrepancies between theoretical and measured sulfur mass were observed for several samples through EA. Qualitative methods, such as infrared spectroscopy and thermal analyses, were also performed and correlated well with the DS determined by NMR. Here, this study presents a promising method to achieve a complete scope of homogeneous sulfonation from mild reaction conditions and presents a case to determine DS through multiple methods, with spectroscopic analyses, such as NMR, being potentially the most valuable.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

NASA NTRS1982

Ka-band Ga-As FET noise receiver/device development

The development of technology for a 30 GHz low noise receiver utilizing GaAs FET devices exclusively is discussed. This program required single and dual-gate FET devices, low noise FET amplifiers, dual-gate FET mixers, and FET oscillators operating at Ka-band frequencies. A 0.25 micrometer gate FET device, developed with a minimum noise figure of 3.3 dB at 29 GHz and an associated gain of 7.4 dB, was used to fabricate a 3-stage amplifier with a minimum noise figure and associated gain of 4.4 dB and 17 dB, respectively. The 1-dB gain bandwidth of this amplifier extended from below 26.5 GHz to 30.5 GHz. A dual-gate mixer with a 2 dB conversion loss and a minimum noise figure of 10 dB at 29 GHz as well as a dielectric resonator stabilized FET oscillator at 25 GHz for the receiver L0. From these components, a hybrid microwave integrated circuit receiver was constructed which demonstrates a minimum single-side band noise figure of 4.6 dB at 29 GHz with a conversion gain of 17 dB. The output power at the 1-dB gain compression point was -5 dBm.

Schellenberg, J. M.↗

DOE OSTI2022

Tuning Organic Electrochemical Transistor Threshold Voltage using Chemically Doped Polymer Gates

Organic electrochemical transistors (OECTs) have shown promise as transducers and amplifiers of minute electronic potentials due to their large transconductances. Tuning the OECT threshold voltage is important to achieve low-powered devices with amplification properties within the desired operational voltage range. However, traditional design approaches have struggled to decouple channel and materials properties from threshold voltage, thereby compromising on several other OECT performance metrics, such as electrochemical stability, transconductance, and dynamic range. In this work, simple solution-processing methods are utilized to chemically dope polymer gate electrodes, thereby controlling their work function, which in turn tunes the operation voltage range of the OECTs without perturbing their channel properties. Chemical doping of initially air-sensitive polymer electrodes further improves their electrochemical stability in ambient conditions. Thus, OECTs that are simultaneously low-powered and electrochemically resistant to oxidative side reactions under ambient conditions are demonstrated. Furthermore, this approach shows that threshold voltage, which is once interwoven with other OECT properties, can in fact be an independent design parameter, expanding the design space of OECTs.

chemical doping↗

NASA NTRS1996

Cyclically controlled welding purge chamber

An arrangement for butt-welding cylindrical sections of large, thin-wall tanks includes a rotatable mandrel with side-by-side sets of radial position adjusters. Each set of adjusters bears on one of the tank sections adjacent the seam, to prevent the sections from sagging out-of-round. The mandrel rotates relative to the welder, so that a continuous seam is formed. A purge chamber is fixed in position behind the seam at the weld head, and is flushed with inert gas. The purge chamber includes a two-sided structure which is contiguous with the cylindrical sections and a circumferential vane to form an open-ended tube-like structure, through which the radial position adjusters pass as the mandrel and cylindrical workpiece sections rotate. The tube-like structure is formed into a chamber by a plurality of movable gates which are controlled to maintain a seal while allowing adjusters to progress through the purge chamber.

Gallagher, Robert L.↗

NASA NTRS2006

Micro-Inspector Avionics Module (MAM): A Self-Contained Low Power, Reconfigurable Avionics Platform for Small Spacecrafts and Instruments

This paper describes development of a radiation tolerant, low power, reconfigurable avionics module aimed at meeting the avionics needs of the JPL Micro-Inspector spacecraft. This module represents a complete avionics system, consisting of two PowerPC 405 CPUs embedded within a reconfigurable FPGA fabric of over 8 Million logic gates, 64MB of EDAC protected Flash storage and 128MB of EDAC protected DDR SDRAM or SDRAM memories, along with FPGA SEU mitigation logic, and all necessary power conversion. Processor SEU mitigation is achieved by running the two processors in a lock-step and compare configuration. All of these building blocks are integrated into a double sided circuit board that takes as little as 6 square inches of board space. This module can be embedded into a user system as part of a bigger circuit assembly or as a self contained module. This module is being developed as part of a JPL led Micro-Inspector Program, funded by NASA ESMD aimed at producing a 10Kg micro spacecraft.

configurable↗

DOE OSTI2021

SV-Sim: Scalable PGAS-based State Vector Simulation of Quantum Circuits

High-performance quantum circuit simulation in a classic HPC is still imperative in the NISQ era. Observing that the major obstacle of scalable state-vector quantum simulation arises from the massively fine-grained irregular data-exchange with remote nodes, in this paper we present SV-Sim to apply the emerging PGAS-based communication models (i.e., direct peer access for intra-node CPUs/GPUs and SHMEM for inter-node CPU/GPU clusters) for efficient scalable quantum circuit simulation. Through an orchestrated device functional pointer design, SV-Sim is able to abstract the quantum gate sets across various heterogeneous backends, including IBM/Intel/AMD CPUs, NVIDIA /AMD GPUs, and Intel MIC, in a unified framework, but still asserting outstanding performance and tractable interface to higher-level quantum programming environments, such as IBM Qiskit, Microsoft Q\# and Google Cirq. Circumventing the disability of polymorphism in GPUs and leveraging the device-initiated one-sided communication, SV-Sim can process dynamically synthesized quantum circuit in a single GPU/CPU kernel without the need of expensive JIT or runtime branching, significantly improving the performance and simplifying the programming complexity for the emerging variational quantum algorithms. Evaluations on NVIDIA A100-DGX-1, V100-DGX-2, AMD MI100, ALCF Theta, and OLCF Summit HPCs show that SV-Sim can delivery scalable performance on various state-of-the-art HPC platforms, offering a useful tool for quantum algorithm validation and verification.

Li, Ang↗

DOE OSTI2022

A Half-Bridge On-State Voltage Sensor for In-Situ Measurements

Current prognostics for life expectancy of power semiconductors utilize off-line measurements of the on-state resistance. Presented is a half-bridge (HB) on-state voltage (VON) sensor capable of being utilized for in-situ measurements enabling continuous and real-time monitoring of the on-state resistance. The design provides a single VON measurement output that contains independent VON information of both high and low side devices in a HB leg. The measurement output is referenced from the middle point of the HB and combines the two complementary VON sensing outputs. This system reduces the number of components, required number of analog signal processing circuits, and ADC channels for in-situ health monitoring of a power electronics system. These reductions will facilitate integration of the VON sensor with the gate driver board and achieve low system profile. The experimental results demonstrate the proposed VON measurements while switching with inductive and resistive loads.

Roy, Chondon↗

NASA NTRS2013

An Offload NIC for NASA, NLR, and Grid Computing

This work addresses distributed data management and access dynamically configurable high-speed access to data distributed and shared over wide-area high-speed network environments. An offload engine NIC (network interface card) is proposed that scales at nX10-Gbps increments through 100-Gbps full duplex. The Globus de facto standard was used in projects requiring secure, robust, high-speed bulk data transport. Novel extension mechanisms were derived that will combine these technologies for use by GridFTP, bandwidth management resources, and host CPU (central processing unit) acceleration. The result will be wire-rate encrypted Globus grid data transactions through offload for splintering, encryption, and compression. As the need for greater network bandwidth increases, there is an inherent need for faster CPUs. The best way to accelerate CPUs is through a network acceleration engine. Grid computing data transfers for the Globus tool set did not have wire-rate encryption or compression. Existing technology cannot keep pace with the greater bandwidths of backplane and network connections. Present offload engines with ports to Ethernet are 32 to 40 Gbps f-d at best. The best of ultra-high-speed offload engines use expensive ASICs (application specific integrated circuits) or NPUs (network processing units). The present state of the art also includes bonding and the use of multiple NICs that are also in the planning stages for future portability to ASICs and software to accommodate data rates at 100 Gbps. The remaining industry solutions are for carrier-grade equipment manufacturers, with costly line cards having multiples of 10-Gbps ports, or 100-Gbps ports such as CFP modules that interface to costly ASICs and related circuitry. All of the existing solutions vary in configuration based on requirements of the host, motherboard, or carriergrade equipment. The purpose of the innovation is to eliminate data bottlenecks within cluster, grid, and cloud computing systems, and to add several more capabilities while reducing space consumption and cost. Provisions were designed for interoperability with systems used in the NASA HEC (High-End Computing) program. The new acceleration engine consists of state-ofthe- art FPGA (field-programmable gate array) core IP, C, and Verilog code; novel communication protocol; and extensions to the Globus structure. The engine provides the functions of network acceleration, encryption, compression, packet-ordering, and security added to Globus grid or for cloud data transfer. This system is scalable in nX10-Gbps increments through 100-Gbps f-d. It can be interfaced to industry-standard system-side or network-side devices or core IP in increments of 10 GigE, scaling to provide IEEE 40/100 GigE compliance.

Awrach, James↗

NASA NTRS1989

Thin film memory matrix using amorphous and high resistive layers

Memory cells in a matrix are provided by a thin film of amorphous semiconductor material overlayed by a thin film of resistive material. An array of parallel conductors on one side perpendicular to an array of parallel conductors on the other side enable the amorphous semiconductor material to be switched in addressed areas to be switched from a high resistance state to a low resistance state with a predetermined level of electrical energy applied through selected conductors, and thereafter to be read out with a lower level of electrical energy. Each cell may be fabricated in the channel of an MIS field-effect transistor with a separate common gate over each section to enable the memory matrix to be selectively blanked in sections during storing or reading out of data. This allows for time sharing of addressing circuitry for storing and reading out data in a synaptic network, which may be under control of a microprocessor.

Thakoor, Anilkumar P.↗

DOE OSTI2022

All‐Polymer Bulk‐Heterojunction Organic Electrochemical Transistors with Balanced Ionic and Electronic Transport

Abstract The rapid development of organic electrochemical transistor (OECTs)‐based circuits brings new opportunities for next‐generation integrated bioelectronics. The all‐polymer bulk‐heterojunction (BHJ) offers an attractive, inexpensive alternative to achieve efficient ambipolar OECTs, and building blocks of logic circuits constructed from them, but have not been investigated to date. Here, the first all‐polymer BHJ‐based OECTs are reported, consisting of a blend of new p‐type ladder conjugated polymer and a state‐of‐the‐art n‐type ladder polymer. The whole ladder‐type polymer BHJ also proves that side chains are not necessary for good ion transport. Instead, the polymer nanostructures play a critical role in the ion penetration and transportation and thus in the device performance. It also provides a facile strategy and simplifies the fabrication process, forgoing the need to pattern multiple active layers. In addition, the development of complementary metal–oxide–semiconductor (CMOS)‐like OECTs allows the pursuit of advanced functional logic circuitry, including inverters and NAND gates, as well as for amplifying electrophysiology signals. This work opens a new approach to the design of new materials for OECTs and will contribute to the development of organic heterojunctions for ambipolar OECTs toward high‐performing logic circuits.

Chemistry↗

DOE OSTI2024

Quantum Computing for High-Energy Physics: State of the Art and Challenges

Quantum computers offer an intriguing path for a paradigmatic change of computing in the natural sciences and beyond, with the potential for achieving a so-called quantum advantage—namely, a significant (in some cases exponential) speedup of numerical simulations. The rapid development of hardware devices with various realizations of qubits enables the execution of small-scale but representative applications on quantum computers. In particular, the high-energy physics community plays a pivotal role in accessing the power of quantum computing, since the field is a driving source for challenging computational problems. This concerns, on the theoretical side, the exploration of models that are very hard or even impossible to address with classical techniques and, on the experimental side, the enormous data challenge of newly emerging experiments, such as the upgrade of the Large Hadron Collider. In this Roadmap paper, led by CERN, DESY, and IBM, we provide the status of high-energy physics quantum computations and give examples of theoretical and experimental target benchmark applications, which can be addressed in the near future. Having in mind hardware with about 100 qubits capable of executing several thousand two-qubit gates, where possible, we also provide resource estimates for the examples given using error-mitigated quantum computing. The ultimate declared goal of this task force is therefore to trigger further research in the high-energy physics community to develop interesting use cases for demonstrations on near-term quantum computers.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2023

Cross Entropy Benchmark for Measurement-Induced Phase Transitions

Here, we investigate prospects of employing the linear cross entropy to experimentally access measurement-induced phase transitions without requiring any postselection of quantum trajectories. For two random circuits that are identical in the bulk but with different initial states, the linear cross entropy χ between the bulk measurement outcome distributions in the two circuits acts as an order parameter, and can be used to distinguish the volume law from area law phases. In the volume law phase (and in the thermodynamic limit) the bulk measurements cannot distinguish between the two different initial states, and χ = 1. In the area law phase χ < 1. For circuits with Clifford gates, we provide numerical evidence that χ can be sampled to accuracy ϵ from O⁢(1/ϵ 2 ) trajectories, by running the first circuit on a quantum simulator without postselection, aided by a classical simulation of the second. We also find that for weak depolarizing noise the signature of the measurement-induced phase transitions is still present for intermediate system sizes. In our protocol we have the freedom of choosing initial states such that the “classical” side can be simulated efficiently, while simulating the “quantum” side is still classically hard.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2024

Metadynamics simulations reveal mechanisms of Na + and Ca 2+ transport in two open states of the channelrhodopsin chimera, C1C2

Cation conducting channelrhodopsins (ChRs) are a popular tool used in optogenetics to control the activity of excitable cells and tissues using light. ChRs with altered ion selectivity are in high demand for use in different cell types and for other specialized applications. However, a detailed mechanism of ion permeation in ChRs is not fully resolved. Here, we use complementary experimental and computational methods to uncover the mechanisms of cation transport and valence selectivity through the channelrhodopsin chimera, C1C2, in the high- and low-conducting open states. Electrophysiology measurements identified a single-residue substitution within the central gate, N297D, that increased Ca 2+ permeability vs. Na + by nearly two-fold at peak current, but less so at stationary current. We then developed molecular models of dimeric wild-type C1C2 and N297D mutant channels in both open states and calculated the PMF profiles for Na + and Ca 2+ permeation through each protein using well-tempered/multiple-walker metadynamics. Results of these studies agree well with experimental measurements and demonstrate that the pore entrance on the extracellular side differs from original predictions and is actually located in a gap between helices I and II. Cation transport occurs via a relay mechanism where cations are passed between flexible carboxylate sidechains lining the full length of the pore by sidechain swinging, like a monkey swinging on vines. In the mutant channel, residue D297 enhances Ca 2+ permeability by mediating the handoff between the central and cytosolic binding sites via direct coordination and sidechain swinging. We also found that altered cation binding affinities at both the extracellular entrance and central binding sites underly the distinct transport properties of the low-conducting open state. This work significantly advances our understanding of ion selectivity and permeation in cation channelrhodopsins and provides the insights needed for successful development of new ion-selective optogenetic tools.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

NASA NTRS1989

CCD imaging sensors

A method for promoting quantum efficiency (QE) of a CCD imaging sensor for UV, far UV and low energy x-ray wavelengths by overthinning the back side beyond the interface between the substrate and the photosensitive semiconductor material, and flooding the back side with UV prior to using the sensor for imaging. This UV flooding promotes an accumulation layer of positive states in the oxide film over the thinned sensor to greatly increase QE for either frontside or backside illumination. A permanent or semipermanent image (analog information) may be stored in a frontside SiO.sub.2 layer over the photosensitive semiconductor material using implanted ions for a permanent storage and intense photon radiation for a semipermanent storage. To read out this stored information, the gate potential of the CCD is biased more negative than that used for normal imaging, and excess charge current thus produced through the oxide is integrated in the pixel wells for subsequent readout by charge transfer from well to well in the usual manner.

Janesick, James R.↗