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90 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail. The Timepix4 is the most recent ASIC designed in the framework of the Medipix4 Collaboration. It was manufactured in 65nm CMOS process, and consists of a four side buttable matrix of 448 × 512 pixels with 55µm pitch. The analog front-end has a gain of ~36mV/ke - when configured in High Gain Mode, and ~20mV/ke - when configured in Low Gain Mode. The Equivalent Noise Charge (ENC) is ~68e - rms and ~80e - rms in High Gain Mode and in Low Gain Mode respectively. In event driven mode the incoming hits can be time stamped within a ~ 200ps time bin and the chip can deal with a maximum flux of ~ 3.6MHzmm –2 s –1 . In photon counting mode, the chip can deal with up to ~ 5GHzmm –2 s –1 . The routine designed to optimize the Timepix4 front-end is then used to analyze the performance limits in terms of jitter and noise for Charge Sensitive Amplifiers in pixel detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Assembly of CMS Endcap MIP Timing Detector Module at FNAL

The High-Luminosity LHC (HL-LHC) will enable a more detailed exploration of new phenomena thanks to an anticipated increase in collisions where pileup is expected to reach approximately 200 simultaneous interactions. Many CMS systems will be significantly upgraded to prepare for this new era, including the MIP Timing Detector (MTD) project. The MTD is designed to mitigate the effect of pileup and is set to provide a timestamp accurate to 30 ~ 40 picoseconds for every event, ensuring sustained detector performance at HL-LHC. The MTD is divided into two sections, Barrel Timing Layer (BTL) and Endcap Timing Layer (ETL) which utilize different sensor and ASIC technologies due to the difference in active surfaces, irradiation conditions, and installation schedules. The ETL, composed of two double-sided disks, employs the Low Gain Avalanche Detector (LGAD) sensor and the Endcap Timing Readout Chip (ETROC). More than 8,000 modules, each consisting of four LGAD sensors and ETROCs are required for the ETL detector. These modules will be assembled using an automated robotic gantry that guarantees precise placement at a level of 10 micrometers. In addition, the full assembly of ETL modules includes film application with the jig, wire-bonding, encapsulation with the automated dispensing robot for protecting the wire-bonding, and film curing with a vacuum oven. This talk reports on the successfully completed throughput test with mockup components using the gantry and the successful assembly of real functional modules for beam tests at CERN and FNAL, including the first official ETL module.

Apresyan, Artur↗
DOE OSTI2023

The New Small Wheel electronics

The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that don't originate from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the “small” Thin Gap Chambers, with a total of 2.45 million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm 2 at the expected HL-LHC luminosity of $\mathcal{L}$= 7.5 × 10 34 cm -2 s -1 . The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Electrical performances of pre-production staves for the ATLAS ITk Strip Detector Upgrade

The ATLAS experiment is currently preparing for an upgrade of the inner tracking detector for the High-Luminosity LHC. The new tracker, ITk, employs an all-silicon detector with outer strip layers. The building block of the ITk strip barrel is the stave which consists of a low-mass support structure hosting the common electrical, optical and cooling services as well as 28 silicon modules. In this contribution, we outline the challenging aspects of the stave pre-production testing phase at Brookhaven National Laboratory. Here, the electrical characterization of these staves, hosting the final design of all ASICs, will be discussed in detail.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

3D Integrated Sensing Solutions

We will present the proposed research project to develop 3D-integrated sensors using advanced manufacturing capability for novel sensors, heterogeneously integrated with energy efficient readout circuits. The lack of precision timing in particle tracking detectors and the absence of low power, high throughput communications solutions to read them out limits progress in multiple fields of fundamental science. The aim of the project is to develop technology to enable large-scale particle detectors with 3D-integrated ASIC designs to simultaneously achieve 10 μm position resolution and 10 ps precision timing, with low-power consumption and high throughput rates. This research program leverages the unique combination of facilities and cross-disciplinary expertise of scientists and engineers at SLAC, FNAL, and LLNL and industrial partners.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

High spatial resolution direct conversion amorphous selenium X-ray detectors with monolithically integrated CMOS readout

Recent progress in the field of micron-scale spatial resolution direct conversion X-ray detectors for high-energy synchrotron light sources serve applications ranging from nondestructive and noninvasive microscopy techniques which provide insight into the structure and morphology of crystals, to medical diagnostic measurement devices. Amorphous selenium ( a -Se) as a wide-bandgap thermally evaporated photoconductor exhibits ultra-low thermal generation rates for dark carriers and has been extensively used in X-ray medical imaging. Being an amorphous material, it can further be deposited over large areas at room temperatures and at substantially lower costs as compared to crystalline semiconductors. Here, to address the demands for a high-energy and high spatial resolution X-ray detector for synchrotron light source applications, we have thermally evaporated a -Se on a Mixed-Mode Pixel Array Detector (MM-PAD) Application Specific Integrated Circuit (ASIC). The ASIC format consists of 128 × 128 square pixels each 150 μm on a side. A 200 μm a -Se layer was directly deposited on the ASIC followed by a metal top electrode. The completed detector assembly was tested with 45 kV Ag and 23 kV Cu X-ray tube sources. The detector fabrication, performances, Modulation Transfer Function (MTF) measurements, and simulations are reported.

36 MATERIALS SCIENCE↗
DOE OSTI2024

A first look at AS-ROC: a Si-Ge integrated chip readout for fast timing

Abstract Advances in timing detector technology require new specialized readout electronics. Applications demand below 10 ps time of arrival resolution and low power for a low repetition rate. A possible path to achieve O(10 ps) time resolution is an integrated chip using Silicon Germanium (SiGe) technology. Using DoE SBIR funding, Anadyne, Inc., in collaboration with UC Santa Cruz, has developed a prototype SiGe front-end readout chip optimized for low power and timing resolution. Two versions of the chip were produced with performance in simulation: a more power version with 10 ps resolution at 5 fC with 1.1 mW/channel, and a less power version with 10 ps resolution at 8 fC with 0.6 mW/channel.The chip was produced at Tower Semiconductor with 350 nm technology. The ASIC from the prototype run shows good performance: a rise time of 0.7–1 ns and 25 mV per fC response with RMS noise <1 mV. Simulation and results from the prototype will be reported in this paper.

Instruments & Instrumentation↗
DOE OSTI2026

Gaia: segmented germanium detector for high-energy X-ray fluorescence and spectroscopic imaging

We present Gaia, a monolithic array of 96 high-purity germanium pixel detectors integrated with a custom low-noise application-specific integrated circuit (ASIC) and a field-programmable gate array (FPGA)-based data acquisition system. The sensor operates at ∼100 K using a commercial closed-cycle cryocooler, with the in-vacuum electronics thermally isolated from the cold finger to ensure thermal stability. The system demonstrates an average energy resolution of 711 eV at 122 keV, measured using a 57 Co source, and 253 eV at 5.89 keV, measured with 55 Fe across all channels. The readout architecture incorporates a high-performance FPGA paired with a dual-core ARM processor, forming a complete embedded Linux-based computing platform. Communication between the processor and FPGA is handled via memory-mapped I/O, and data are streamed over high-speed gigabit Ethernet. A full-scale 384-pixel Gaia detector, based on this 96-element module, is currently under fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Beam test performance studies of CMS Phase-2 Outer Tracker module prototypes

A new tracking detector will be installed as part of thePhase-2 upgrade of the CMS detector for the high-luminosity LHC era.This tracking detector includes the Inner Tracker, equipped withsilicon pixel sensor modules, and the Outer Tracker, consisting ofmodules with two parallel stacked silicon sensors. The Outer Trackerfront-end ASICs will be able to correlate hits from chargedparticles in these two sensors to perform on-module discriminationof transverse momenta (p$_{T}$). The p$_{T}$information is generated at a frequency of 40 MHz and will be usedin the Level-1 trigger decision of CMS. Prototypes of theso-called 2S modules were tested at the Test Beam Facility at DESYHamburg between 2019 and 2020. These modules use the finalfront-end ASIC, the CMS Binary Chip (CBC), and for the firsttime the Concentrator Integrated Circuit (CIC), optical readoutand on-module power conversion. In total, seven modules were tested,one of which was assembled with sensors irradiated with protons. Animportant aspect was to show that it is possible to read out modulessynchronously. A cluster hit efficiency of about 99.75 % wasachieved for all modules. The CBC p$_{T}$ discriminationmechanism has been verified to work together with the CIC andoptical readout. The measured module performance meets therequirements for operation in the upgraded CMS tracking detector.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Multi-channel front-end ASIC for a 3D position-sensitive detector

Arrays of 3D position-sensitive detectors (3DPSD), operating at room temperature and using cadmium zinc telluride (CZT) and thallium bromide (TIBr) sensors, are suitable for gamma-ray spectrometry in many applications. One detector configuration, the 3D position-sensitive Virtual Frisch-Grid detector (VFG), is particularly advantageous for integrating into large area arrays. The signals generated inside each detector of the array are captured with the anode, cathode and four pads that enable the reconstruction of the position and energy of the ionizing interaction by measurements of amplitude and timing of the signals. For these applications, a low-noise front-end ASIC has been developed, capable of processing bipolar signals (needed because of AC-coupling of certain electrodes). The ASIC can be coupled to an ADC in order to form a compound “waveform digitizer” capable of post-processing the analog signals and determining amplitude and timing information. This paper describes a 32-channel front-end ASIC that is suitable for reading out a 3 × 3 or 4 × 4 element matrix in the VFG configuration. Each channel is composed of a low-noise charge amplifier with an adaptive continuous reset feedback circuit suitable for both positive and negative charge, a first order shaper and a single-to-differential converter output stage. Voltage and current references are all internally generated by 10-bit DACs and the chip is fully controllable with the I 2 C communication protocol. The readout channel response has been verified using the implemented injection circuit. Linear behavior up to ~75 ke ± with the gain of ~80 mV/fC, and up to ~200 ke ± with the gain of ~30 mV/fC was demonstrated. In conclusion, the first test result waveforms using a 137 Cs radioactive source on a 5 × 5 × 12 mm 3 TIBr crystal are reported.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Characterization of 128 × 128 MM-PAD-2.1 ASIC: a fast framing hard x-ray detector with high dynamic range

Here, we characterize a new x-ray Mixed-Mode Pixel Array Detector (MM-PAD-2.1) Application Specific Integrated Circuit (ASIC). Using an integrating pixel front-end with dynamic charge removal architecture, the MM-PAD-2.1 ASIC extends the maximum measurable x-ray signal (in 20 keV photon units) to > 10 7 x-rays/pixel/frame while maintaining a low read noise across the full dynamic range, all while imaging continuously at a frame rate of up to 10 kHz. The in-pixel dynamic charge removal mechanism prevents saturation of the input amplifier and proceeds in parallel with signal integration to achieve deadtime-less measurements with incident x-ray rates of > 10 10 x-rays/pixel/s. The ASIC format consists of 128 × 128 square pixels each 150 μm on a side and is designed to be 3-side buttable so large arrays can be effectively tiled. Here we use both laboratory x-ray sources and the Cornell High Energy Synchrotron Source (CHESS) to characterize two single ASIC prototype detectors for both low (single x-ray) and high incident flux detection. In the first detector the ASIC was solder bump-bonded to a 500 μm thick Si sensor for efficient detection of x-rays below 20 keV, whereas the second detector used a 750 μm thick CdTe sensor for x-rays above ~20 keV.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Design of an 8-channel 40 GS/s 20 mW/Ch waveform sampling ASIC in 65 nm CMOS

One picosecond timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in TSMC 65 nm process targetting one picosecond resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing for picosecond time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC. PSEC5 has been submitted for fabrication.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Calibration of a compact ASIC-based data acquisition system for neutron/$γ$ discrimination and spectroscopy with organic scintillators

Segmented neutron detectors that use silicon photomultipliers (SiPMs) are receiving significant attention in nuclear security applications. Some of these detectors employ hundreds of channels and would therefore benefit from the use of high-channel-density and low-cost-per-channel data acquisition (DAQ) systems. Candidate DAQ systems that meet these requirements exist, but few perform full waveform digitization, which permits neutron and gamma-ray interaction discrimination via pulse shape. In this work, we study the performance of the TOFPET2 (PETsys Electronics), an ASIC-based DAQ designed for positron emission tomography, which has been adapted to provide sensitivity to pulse shape by the use of variable-period charge integration. We use a light-emitting diode to calibrate a combination of an ON Semiconductor (SensL) 60035-64P J-Series SiPM and TOPFET2 DAQ and evaluate the linearity of their response and dynamic range. Here, the calibration curve was obtained by comparing the DAQ response to that measured with a photodiode interfaced with a traditional waveform digitizer. This calibration process was used for rudimentary spectroscopy of various neutron and sources.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Characterization of the ATLAS Liquid Argon Front-End ASIC ALFE2 for the HL-LHC upgrade

In this study, ALFE2 is an ATLAS Liquid Argon Calorimeter (LAr) Front-End ASIC designed for the HL-LHC upgrade. ALFE2 comprises four channels of pre-amplifiers and CR-(RC) 2 shapers with adjustable input impedance. ALFE2 features two separate gain outputs to provide 16-bit dynamic-range coverage and an optimum resolution. ALFE2 is characterized using a Front-End Test Board (FETB) based on a Zynq UltraScale+ MPSoC and two octal-channel 16-bit high-speed ADCs. The test results indicate that ALFE2 fulfills or greatly exceeds all specifications on gain, noise, linearity, uniformity, and radiation tolerance.

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

Robustness of the smartpixels classifier for different simulated sensor geometries and non-ideal detector conditions

Pixel tracking detectors at upcoming collider experiments will see unprecedented charged-particle densities. Real-time data reduction on the detector will enable higher granularity and faster readout, possibly enabling the use of the pixel detector in high-rate online event selection, such as the ATLAS or CMS first-level trigger systems. This data reduction can be accomplished with a neural network (NN) in the readout chip bonded with the sensor that recognizes and rejects tracks with low transverse momentum (p T ) based on the geometrical shape of the charge deposition (“cluster”). To design viable detectors for deployment, the dependence of the NN as a function of the sensor geometry, external magnetic field, irradiation, and noise must be understood. In this paper, we present first studies of the efficiency and data reduction for planar pixel sensors exploring these parameters. For the CMS HL-LHC sensor geometry, we obtain a signal efficiency of (91.9 ± 0.7)% and a data reduction of (29.7 ± 1.0)%. A smaller sensor pitch in the bending direction improves the p T discrimination, but a larger pitch can be partially compensated with detector thickness. Any accumulated radiation damage also changes the cluster shape, reducing the signal efficiency compared to the baseline by approximately 30–60% in absolute terms, but nearly all of the performance can be recovered through retraining of the network and updating the weights. Finally, the impact of noise was investigated, and retraining the network on noise-injected datasets was found to maintain performance within 6% of the baseline network trained and evaluated on noiseless data. •ASIC-compatible track-momentum classifier is robust in realistic detector conditions.•About 90% signal efficiency and 30% data reduction per layer for CMS HL-LHC geometry.•Single-layer signal efficiency increases for smaller pixel pitch or thicker sensors.•Performance with noise or after radiation damage mostly recovered by retraining.

Shekar, Danush [Illinois U., Chicago] (ORCID:00000↗
DOE OSTI2022

QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology

Here, the Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Lifetime study of the ColdADC for the Deep Underground Neutrino Experiment

ColdADC is a custom ASIC digitizer implemented in 65 nm CMOS technology using specialized techniques for long-term reliability in cryogenic environments. ColdADC was developed for use in the DUNE Far Detector complex, which will consist of four liquid argon time projection chambers. Each contains 17 kilotons liquid argon as the target material in order to measure neutrino oscillations. Approximately 40,000 ColdADC ASICs will be installed for DUNE in the first two large detectors and will be operated at cryogenic temperatures during the experiment without replacement. The lifetime of the ColdADC is a critical parameter affecting the data quality and physics sensitivity of the experiment. A measurement of the lifetime of the ColdADC was carried out, and the results shown in this paper assure orders of magnitude longer lifetime of the ColdADC than the planned operation time of the detectors.

Front-end electronics for detector readout↗
DOE OSTI2025

The AMACStar ASIC for the HL-LHC ATLAS ITk Strip detector: design, verification, testing, and quality assurance

For the high-luminosity upgrade to the LHC (HL-LHC), the ATLAS detector at CERN requires an all-new inner detector, the Inner Tracker (ITk). The ITk Strip subdetector is made up of silicon modules, which include three types of radiation-hard ASICs. One of these is the Autonomous Monitor and Control (AMAC). The AMAC is manufactured by Global Foundries using 130 nm CMOS8RF DM technology and is approximately 3 by 5 mm in size. This ASIC autonomously monitors the temperatures, voltages, and currents in the module components while controlling critical values in order to prevent these quantities from reaching dangerous levels. The final design, AMACStar, was verified, tested, and ensured to perform all necessary functions. A quality control procedure using an in-house probe station set-up was developed in order to ensure that every individual chip on each wafer of AMACStars required by the ITk Strip project met performance requirements. The average per wafer yield of usable AMACStars is 92.33%, exceeding the design-specific 90% yield estimated for project costing. This estimate was based on actual yields for similar designs in this process.

Analogue electronic circuits↗