High-performance Thermionic Converters Final Report, 19 May 1965 - 19 Jul. 1966
Precision variable parameter test vehicles for parametric studies of plane-parallel cesium vapor thermionic converter performance
PERFORMANCE CHARACTERISTICS↗
SEARCH · Engineering Papers
Results for “paralleled converters”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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A study of DC-DC converters with MCT's for arcjet power supplies
Many arcjet DC power supplies use PWM full bridge converters with large arrays of parallel FET's. This report investigates an alternative supply using a variable frequency series resonant converter with small arrays of parallel MCT's (metal oxide semiconductor controlled thyristors). The reasons for this approach are to: increase reliability by reducing the number of switching devices; and decrease the surface mounting area of the switching arrays. The variable frequency series resonant approach is used because the relatively slow switching speed of the MCT precludes the use of PWM. The 10 kW converter operated satisfactorily with an efficiency of over 91 percent. Test results indicate this efficiency could be increased further by additional optimization of the series resonant inductor.
Stuart, Thomas A.↗
Multi-resonant switched capacitor power converter architecture
A switched-capacitor (SC) network in an SC converter is controlled to operate at varying resonant modes to achieve high conversion ratio efficiency, at a low circuit component count. These power converters are suited to numerous application areas including improving energy efficiency of data centers. A family of resonant switched capacitor (SC) converters with multiple operating phases are presented “Multi-Resonant SC Converters”. Described in detail are an 8-to-1 Multi-Resonant-Doubler (MRD) converter and a 6-to-1 Cascaded Series-Parallel (CaSP). The topology of these converters make them amenable to combining like units in parallel toward reaching higher power levels.
Ye, Zichao↗
System-Level Efficiency Study of Modular DC/DC and Fuel Cell Stack Series–Parallel Configurations
This paper presents a system-level efficiency study of modular DC/DC converter and fuel cell stack configurations under series, parallel, and series–parallel connections. The investigation considers selected DC/DC converter topologies, including isolated and non-isolated architectures, boost, non-inverting buck-boost, and resonant converters, integrated with commercially available fuel cell stacks, including the Accelera FCE150, Ballard FCgen-HPS, and Toyota TFCM2. DC/DC converter modules are evaluated in modular configurations rated at 60 kW and 90 kW and two distinct output voltage ranges, specifically 580–730V and 780–930V, examining how different interconnection schemes impact overall system efficiency. The converters are evaluated under full load (100%), partial load (66%), and light load (33%) conditions, providing a comprehensive assessment of efficiency and operational characteristics across varying power demands. Approximately two-thousand efficiency data points are obtained from laboratory prototype–level component measurements and validated design evaluations across multiple converter topologies, modular configurations, voltage ranges, and load conditions, providing a robust dataset for comparative system-level efficiency analysis. The results highlight the effects of modularity and topology selection on system-level efficiency, offering a “playbook” framework for designers to select appropriate DC/DC converter arrangements and fuel cell stack connections for series, parallel, or hybrid configurations based on efficiency considerations.
DC/DC↗
Modular, multi-channel, interleaved power converters
A multi-phase power converter includes two or more multi-phase, bi-directional, multi-level, switching power converter subcircuits, connected in parallel at respective AC and DC sides, so as to provide a multi-channel, bi-directional, multi-level configuration. The AC sides of the switching converter subcircuits are directly coupled to one another and to a multi-phase AC input via series interface reactors, and the DC sides of the switching converter subcircuits are directly connected to one another and to a common split-capacitor bank at each level of the multi-level outputs of the switching converter subcircuits. A control circuit is configured to selectively control one or more switching semiconductor devices in each of the switching converter subcircuits. In some embodiments, the control circuit includes a closed-loop zero-sequence controller and a zero-sequence generator configured to eliminate circulating current among the switching converter subcircuits and to balance voltages across levels of the common split-capacitor bank.
24 POWER TRANSMISSION AND DISTRIBUTION↗
Interleaved multi-channel, multi-level, multi-quadrant DC-DC converters
Direct-current-to-direct-current (DC-DC) power converters that include two or more multi-quadrant, multi-level, DC-DC, switching converter subcircuits, connected in parallel at respective input and output sides, so as to provide a multi-channel, multi-quadrant, multi-level configuration, are disclosed. The DC-DC power converters further include a control circuit configured to control the switching converter subcircuits so that corresponding switching semiconductors in each of the switching converter subcircuits are switched in an interleaved manner. In some embodiments, each of the switching converter subcircuits is a three-level, neutral-point-clamped, four-quadrant DC-DC converter circuit. In other embodiments, each of the switching converter subcircuits is a three-level, neutral-point-clamped, two-quadrant DC-DC converter circuit. In any of these embodiments, a filter capacitor may be connected between across a pair of output terminals at the output sides of the switching converter subcircuits.
Du, Yu↗
Molecular solid-state inverter-converter system
A modular approach for aerospace electrical systems has been developed, using lightweight high efficiency pulse width modulation techniques. With the modular approach, a required system is obtained by paralleling modules. The modular system includes the inverters and converters, a paralleling system, and an automatic control and fault-sensing protection system with a visual annunciator. The output is 150 V dc, or a low distortion three phase sine wave at 120 V, 400 Hz. Input power is unregulated 56 V dc. Each module is rated 2.5 kW or 3.6 kVA at 0.7 power factor.
Birchenough, A. G.↗
On-Focal-Plane Successive Approximation A/D/ Converters for Digital CMOS Image Sensors
Two charge-scaling successive approximation A/D converters for culumn-parallel data processing in CMOS active pixel image sensors (APS) are presented.
APS active pixel sensors A/D converters↗
Experience of Migrating a Parallel Graph Coloring Program from CUDA to SYCL
We describe the experience of converting a CUDA implementation of a parallel graph coloring algorithm to SYCL. The goals are for our work to be useful to application and compiler developers by providing a detailed description of migration paths between CUDA and SYCL. We will describe how CUDA functions are mapped to SYCL functions. Evaluating the CUDA and SYCL implementations of the algorithm shows that the performance of SYCL and CUDA kernels are comparable over the test graph set on NVIDIA P100 and V100 GPUs. The SYCL program also allows for performance evaluation with the OpenCL and Level Zero interfaces and power profiling on an Intel GPU computing platform.
97 MATHEMATICS AND COMPUTING↗
Support for Debugging Automatically Parallelized Programs
This viewgraph presentation provides information on the technical aspects of debugging computer code that has been automatically converted for use in a parallel computing system. Shared memory parallelization and distributed memory parallelization entail separate and distinct challenges for a debugging program. A prototype system has been developed which integrates various tools for the debugging of automatically parallelized programs including the CAPTools Database which provides variable definition information across subroutines as well as array distribution information.
Hood, Robert↗
Research on design feasibility of high-power light-weight dc-to-dc converters for space power application
The development of 5 kW converters with 100 kHz switching frequencies, consisting of two submodules each capable of 2.5 kW of output power, is discussed. Two semiconductor advances allowed increased power levels. Field effect transistors with ratings of 11 A and 400 V were operated in parallel to provide a converter output power of approximately 2000 W. Secondly, bipolar power switching transistor was operated in conjunction with a turn-off snubber circuit to provide converter output power levels approaching 1000 W. The interrelationships between mass, switching frequency, and efficiency were investigated. Converters were constructed for operation at a maximum output power level of 200 W, and a comparison was made for operation under similar input/output conditions for conversion frequencies of 20 kilohertz and 100 kilohertz. The effects of nondissipative turn-off snubber circuitry were also examined. Finally, a computerized instrumentation system allowing the measurement of pertinent converter operating conditions as well as the recording of converter waveforms is described.
Wilson, T. G.↗
Characteristics of a thermionic converter with a chloride vapor deposited tungsten emitter /110/ and a collector of molybdenum deposited on niobium
Performance characteristics of parallel plane, variable spaced thermionic converter with tungsten emitter and molybdenum-niobium collector
Podkulski, S. P.↗
Method and Apparatus for High Data Rate Demodulation
A method to demodulate BPSK or QPSK data using clock rates for the receiver demodulator of one-fourth the data rate is presented. This is accomplished through multirate digital signal processing techniques. The data is sampled with an analog-to-digital converter and then converted from a serial data stream to a parallel data stream. This signal processing requires a clock cycle four times the data rate. Once converted into a parallel data stream, the demodulation operations including complex baseband mixing, lowpass filtering, detection filtering, symbol-timing recovery, and carrier recovery are all accomplished at a rate one-fourth the data rate. The clock cycle required is one-sixteenth that required by a traditional serial receiver based on straight convolution. The high rate data demodulator will demodulate BPSK, QPSK, UQPSK, and DQPSK with data rates ranging from 10 Mega-symbols to more than 300 Mega-symbols per second. This method requires less clock cycles per symbol tan traditional serial convolution techniques.
Gerald J Grebowsky↗
Implementation of a 3D mixing layer code on parallel computers
This paper summarizes our progress and experience in the development of a Computational-Fluid-Dynamics code on parallel computers to simulate three-dimensional spatially-developing mixing layers. In this initial study, the three-dimensional time-dependent Euler equations are solved using a finite-volume explicit time-marching algorithm. The code was first programmed in Fortran 77 for sequential computers. The code was then converted for use on parallel computers using the conventional message-passing technique, while we have not been able to compile the code with the present version of HPF compilers.
Roe, K.↗
A 2.5 kW cascaded Schwarz converter for 20 kHz power distribution
Because it avoids the high currents in a parallel loaded capacitor, the cascaded Schwarz converter should offer better component utilization than converters with sinusoidal output voltages. The circuit is relatively easy to protect, and it provides a predictable trapezoidal voltage waveform that should be satisfactory for 20-kHz distribution systems. Analysis of the system is enhanced by plotting curves of normalized variables vs. gamma(1), where gamma(1) is proportional to the variable frequency of the first stage. Light-load operation is greatly improved by the addition of a power recycling rectifier bridge that is back biased at medium to heavy loads. Operation has been verified on a 2.5-kW circuit that uses input and output voltages in the same range as those anticipated for certain future spacecraft power systems.
Shetler, Russell E.↗
Modeling of DC spacecraft power systems
Future spacecraft power systems must be capable of supplying power to various loads. This delivery of power may necessitate the use of high-voltage, high-power dc distribution systems to transmit power from the source to the loads. Using state-of-the-art power conditioning electronics such as dc-dc converters, complex series and parallel configurations may be required at the interface between the source and the distribution system and between the loads and the distribution system. This research will use state-variables to model and simulate a dc spacecraft power system. Each component of the dc power system will be treated as a multiport network, and a state model will be written with the port voltages as the inputs. The state model of a component will be solved independently from the other components using its state transition matrix. A state-space averaging method is developed first in general for any dc-dc switching converter, and then demonstrated in detail for the particular case of the boost power stage. General equations for both steady-state (dc) and dynamic effects (ac) are obtained, from which important transfer functions are derived and applied to a special case of the boost power stage.
Berry, F. C.↗
Studies in optical parallel processing
Threshold and A/D devices for converting a gray scale image into a binary one were investigated for all-optical and opto-electronic approaches to parallel processing. Integrated optical logic circuits (IOC) and optical parallel logic devices (OPA) were studied as an approach to processing optical binary signals. In the IOC logic scheme, a single row of an optical image is coupled into the IOC substrate at a time through an array of optical fibers. Parallel processing is carried out out, on each image element of these rows, in the IOC substrate and the resulting output exits via a second array of optical fibers. The OPAL system for parallel processing which uses a Fabry-Perot interferometer for image thresholding and analog-to-digital conversion, achieves a higher degree of parallel processing than is possible with IOC.
Lee, S. H.↗
Interface of the transport systems research vehicle monochrome display system to the digital autonomous terminal access communication data bus
An upgrade of the transport systems research vehicle (TSRV) experimental flight system retained the original monochrome display system. The original host computer was replaced with a Norden 11/70, a new digital autonomous terminal access communication (DATAC) data bus was installed for data transfer between display system and host, while a new data interface method was required. The new display data interface uses four split phase bipolar (SPBP) serial busses. The DATAC bus uses a shared interface ram (SIR) for intermediate storage of its data transfer. A display interface unit (DIU) was designed and configured to read from and write to the SIR to properly convert the data from parallel to SPBP serial and vice versa. It is found that separation of data for use by each SPBP bus and synchronization of data tranfer throughout the entire experimental flight system are major problems which require solution in DIU design. The techniques used to accomplish these new data interface requirements are described.
Easley, W. C.↗