Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “p-type”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Understanding the optoelectronic properties of doped 2D organic-inorganic halide perovskite quantum wells: towards efficient quantum well IR photodetectors

Metal halide perovskite (MHP) multiple quantum wells which consist of multilayers of alternate organic and inorganic layers exhibit large exciton binding energies due to the dielectric confinement between the inorganic and organic layers. These naturally formed multiple quantum wells have strong spin-orbit coupling (SOC) due to the presence of heavy elements in their crystal structures. Although the fundamental properties of 2D MHPs are far from being entirely understood, it is widely accepted that their band edge absorption coefficient results from strong exciton interactions. However, studies demonstrating how different exciton interactions and doping effects influence electronic traps and disorder on the band edge absorption coefficient of 2D MHPs have not been demonstrated. Understanding these interactions in MHPs will allow us to access low energy optical transitions for the fabrication of solution processable short-to-mid-wavelength IR photodetectors (1 – 8 μm). Moreover, upon doping, it is possible to move the Fermi energy into the conduction band (CB) to favorably promote the transport of charges in a working device. Herein, we study the development of 2D MHPs having strong SOC, high carrier mobility, and tunable quantum well structures. Our studies shed light on the design and modulation of fundamental physical phenomena by carefully elucidating the role of dopants (n-type and p-type), exciton heterogeneity, orientation, structure, and bias stress effects on the performance of MHPs as potential IR photodetectors.

36 MATERIALS SCIENCE↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2026

Boride-based Ceramic Super-high Temperature Thermocouples in Harsh Environments (Final Scientific/Technical Report)

An electromotive force (emf) can be generated along a temperature gradient between the cold end and hot end of a thermoelectric material, termed the Seebeck effect. Based on the Seebeck effect, metallic alloys have been extensively employed to detect temperatures for centuries, named thermocouples. However, commercially available thermocouple alloys suffer from limitations, such as oxidation, chemical degradation, and poor long-term stability under high-temperature harsh environments. This DOE-funded project aimed to develop high-temperature, chemically tolerant thermocouples suitable for operation in extreme environments relevant to semiconducting thermoelectric materials. The research focused on boride-based semiconducting thermoelectric compounds as candidates for next-generation thermocouples with enhanced oxidation resistance, chemical stability, and thermal robustness under conditions representative of charcoal-fired electricity facilities. During the funded years, boride materials were synthesized using an arc-plasma technique under ambient air and argon atmospheres, enabling scalable and cost-effective production compared with conventional boride fabrication methods. The synthesized borides were processed into nanostructured powders, followed by consolidation into dense bulk materials using a spark plasma sintering (SPS) bottom-up approach. Comprehensive characterization was performed, including microstructural analysis, electrical transport measurements, and optical and thermal property evaluation. Both p-type and n-type boride electric legs were fabricated and integrated into boride-based thermocouples. The thermal and irradiation stabilities of the boride nanomaterials and bulk thermoelectric materials were systematically evaluated to assess suitability for long-term operation in harsh environments. Additionally, 12 students were broadly hands-on trained spanning the full research workflow, including word processing and technical editing (e.g., LATEX for manuscript and poster preparation), data collection and analysis (using Python and related libraries and hardware interfaces), sample preparation (including arc-plasma synthesis and spark plasma sintering), and advanced characterization techniques (such as X-ray diffraction, UV–vis spectroscopy, electron microscopy, differential thermal analysis (DTA), and Seebeck coefficient measurements, etc). Overall, this project demonstrated the feasibility of boride-based thermoelectric materials as durable high-temperature thermocouples, providing a promising pathway toward robust temperature sensing technologies aligned with DOE energy infrastructure and extreme-environment monitoring needs.

20 FOSSIL-FUELED POWER PLANTS↗
DOE OSTI2026

Epitaxy of Beta-Ga2O3 on Highly-Offcut (Greater than 10 Degrees) Substrates

Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction.1 These films show step-flow growth from (-201) step-edges and high electron mobility. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (4.8 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe 100% reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Bandgap Engineering of Ga 2 O 3 by MOCVD Through Alloying with Indium

Ga 2 O 3 and In 2 O 3 are vital semiconductors with current and future electronic device applications. Here, we study the alloying of In 2 O 3 and Ga 2 O 3 (IGO) and the associated changes in structure, morphology, band gap, and electrical transport properties. Undoped films of IGO were deposited on sapphire substrates with varying indium (In) percentage from zero to 100% by metal-organic chemical vapor deposition (MOCVD). Some films were annealed in H 2 to induce electrical conductivity. The measurements showed the optical band gap decreased by adding In; this was confirmed by density functional (DFT) calculations, which revealed that the nature of the valence band maximum and conduction band minimum strongly relate to the chemistry and that the band gap drops by adding In. The as-grown films were highly resistive except for pure In 2 O 3 , which possesses p-type conductivity, likely arising from In vacancy-related acceptor states. N-type conductivity was induced in all films after H-anneal. DFT calculations revealed that the presence of In decreases the electron effective mass, which is consistent with the electrical transport measurements that showed higher electron mobility for higher In percentage. The work revealed the successful band gap engineering of IGO and the modification of its band structure while maintaining high-quality films by MOCVD.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Fast Growth of Ga2O3 on Highly Offcut (100)-Oriented Substrates

Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. More importantly, the impact ionization coefficients along the [100] direction are low, leading to the highest possible critical fields. This is advantageous compared to the current state of the art, (001), due to reduced surface defects and increased possible breakdown voltage. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption, and on-axis (100) growth easily forms twin domains. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction. These films show step-flow growth from (20-1) step-edges and high electron mobility due to suppressed twins. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (>5 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3 and critical breakdown field in Schottky barrier diodes comparable with state-of-the-art (001) Ga2O3 without edge termination.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Data for "Gold-Induced Chemical Perturbations in CdTe-Based Photovoltaic Cells"

Back contacting p-type CdTe has been identified as one of the major areas of loss in CdTe photovoltaic (PV) power conversion efficiency (PCE). In research settings, Au is a common contact material due to its ease of use and decent performance. This work provides a detailed investigation into using gold for back contacting As-doped, CdCl2 treated, polycrystalline CdTe that has been exposed to air after absorber processing, another routine practice. First, X-ray photoemission spectroscopy (XPS) is used to determine the native oxide to be 1.6 nm of CdTeO3 using a combination of angle-resolved XPS and the cadmium modified Auger parameter. During gold metallization of CdTe, oxygen and oxidized tellurium are eliminated from the thin CdTeO3 native oxide. The fate of the released oxygen and possibly cadmium and tellurium are not known, but these reaction byproducts can enter the absorber bulk or grain boundaries, stay at the interface, or dissolve in the Au. Interfacial hole barriers between CdTe and Au are measured for samples with and without the native oxide present prior to metallization. Results show that the thin CdTeO3 alleviates the downward band bending by 40 meV from 470 meV to 430 meV even though it is consumed during interface formation. The implications of these chemical reactions on the device are assessed through photoluminescence (PL) spectroscopy which shows losses in internal open circuit voltage (iVoc) from 820 meV to 795 meV, carrier lifetime from 123 ns to 45 ns, and PL quantum yield from 2.9x10-5 to 1.2x10-5. Modeling time-resolved PL lifetimes demonstrates the back surface recombination velocity due to metallization reduces minority carrier lifetimes. These results identify the native oxide and show that it plays an important role in mediating downward band bending along with how the back interface reaction can negatively impact device-scale parameters and reduce PV PCE.

14 SOLAR ENERGY↗
NASA NTRS1964

Economical fabrication process produces high quality junction transistors

A convenient, three-step fabrication process, with a p-type layer of gallium arsenide vapor deposited on a starting wafer of germanium, is used to produce heterojunction-homojunction p-n-p transistors. These are of high quality with good injection efficiency and low capacitance.

Source record↗
NASA NTRS1966

Radiation used to temperature compensate semiconductor strain gages

Exposure to high energy electron radiation reduces the temperature coefficients of resistance and gage factor of a range of resistivities of n- and p-type semiconductor silicon strain gages. After irradiation, the gages are heated to a high temperature for a 24-hour period to stabilize their temperature coefficients.

Gross, C.↗
NASA NTRS1972

Hybrid TE panel test results

Test results are presented for a nine couple (3 x 3 array) thermoelectric panel of hybrid thermocouples. In the hybrid couple, a hollow cylinder of p-type Si-Ge is used to encapsulate a segmented PbTe/Si-Ge n-leg. The hybrid couple is predicted to offer a 10- to 15-percent improvement in performance relative to all Si-Ge couples. The efficiency, output power, and internal resistance of the panel as well as the resistances of the individual hybrid couples are presented as a function of test time covering a period of more than 2600 hours. Initial test results indicated hybrid couple performance consistent with design predictions. Extraneous resistance ranged from 20 to 25% of the hybrid couple thermoelectric resistance.

Bifano, W. J.↗
DOE OSTI2025

Hierarchical Hybrid Multifunctional Materials through Interface Engineering

This project focuses on the development of stimuli-responsive hybrid multifunctional materials. We place emphasis on the design, synthesis, structural characterization, evaluation of functional properties (electronic, thermal and optical) of several (1-x)Cu 2 Se/(x)WBGS hierarchical bulk composites between Cu 2 Se, a narrow band gap semiconductor (NBGS), with a range of wider band gap semiconductors (WBGS) such as CuMSe 2 (M = Al, Ga, In, Fe, Cr) and Cu 4 TiSe 4 . Cu2Se is a well-studied NBGS with excellent thermoelectric properties (high electrical conductivity, large thermopower, etc.) while CuMSe 2 and Cu 4 TiSe 4 are high performance solar absorber materials (large band gap, large absorption coefficient, etc.). Our primary objectives are (i) to demonstrate the ability to integrate dissimilar functional properties such as large optical absorption coefficient and high electronic conductivity, within (1-x)Cu 2 Se/(x)WBGS composite; and (ii) to establish the correlation between the hierarchical structural entanglement of Cu 2 Se with WBGS (CuMSe 2 or Cu 4 TiSe 4 ) phase, the interactions between native electronic defects within the coexisting phases in the resulting (1-x)Cu 2 Se/(x)WBGS bulk composites , and the impacts on their electronic conductivity, thermal transport and optical properties.

36 MATERIALS SCIENCE↗