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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

JTAG-based PLC memory acquisition framework for industrial control systems

In industrial control systems (ICS), programmable logic controllers (PLC) are the embedded devices that directly control and monitor critical industrial infrastructure processes such as nuclear plants and power grid stations. Cyberattacks often target PLCs to sabotage a physical process. A memory forensic analysis of a suspect PLC can answer questions about an attack, including compromised firmware and manipulation of PLC control logic code and I/O devices. Given physical access to a PLC, collecting forensic information from the PLC memory at the hardware-level is risky and challenging. It may cause the PLC to crash or hang since PLCs have proprietary, legacy hardware with heterogeneous architecture. This paper addresses this research problem and proposes a novel JTAG (Joint Test Action Group)-based framework, Kyros, for reliable PLC memory acquisition. Kyros systematically creates a JTAG profile of a PLC through hardware assessment, JTAG pins identification, memory map creation, and optimizing acquisition parameters. It also facilitates the community of interest (such as ICS owners, operators, and vendors) to develop the JTAG profiles of PLCs. Further, we present a case study of Kyros implementation over Allen-Bradley 1756-A10/B to help understand the framework's application on a real-world PLC used in industry settings. The sample PLC memory dumps are shared with the research community to facilitate further research.

Rais, Muhammad Haris↗
NASA NTRS2007

Two-Way Communication Using RFID Equipment and Techniques

Equipment and techniques used in radio-frequency identification (RFID) would be extended, according to a proposal, to enable short-range, two-way communication between electronic products and host computers. In one example of a typical contemplated application, the purpose of the short-range radio communication would be to transfer image data from a user s digital still or video camera to the user s computer for recording and/or processing. The concept is also applicable to consumer electronic products other than digital cameras (for example, cellular telephones, portable computers, or motion sensors in alarm systems), and to a variety of industrial and scientific sensors and other devices that generate data. Until now, RFID has been used to exchange small amounts of mostly static information for identifying and tracking assets. Information pertaining to an asset (typically, an object in inventory to be tracked) is contained in miniature electronic circuitry in an RFID tag attached to the object. Conventional RFID equipment and techniques enable a host computer to read data from and, in some cases, to write data to, RFID tags, but they do not enable such additional functions as sending commands to, or retrieving possibly large quantities of dynamic data from, RFID-tagged devices. The proposal would enable such additional functions. The figure schematically depicts an implementation of the proposal for a sensory device (e.g., a digital camera) that includes circuitry that converts sensory information to digital data. In addition to the basic sensory device, there would be a controller and a memory that would store the sensor data and/or data from the controller. The device would also be equipped with a conventional RFID chipset and antenna, which would communicate with a host computer via an RFID reader. The controller would function partly as a communication interface, implementing two-way communication protocols at all levels (including RFID if needed) between the sensory device and the memory and between the host computer and the memory. The controller would perform power V

Jedry, Thomas↗
NASA NTRS1992

Parallel fault-tolerant robot control

A shared memory multiprocessor architecture is used to develop a parallel fault-tolerant robot controller. Several versions of the robot controller are developed and compared. A robot simulation is also developed for control observation. Comparison of a serial version of the controller and a parallel version without fault tolerance showed the speedup possible with the coarse-grained parallelism currently employed. The performance degradation due to the addition of processor fault tolerance was demonstrated by comparison of these controllers with their fault-tolerant versions. Comparison of the more fault-tolerant controller with the lower-level fault-tolerant controller showed how varying the amount of redundant data affects performance. The results demonstrate the trade-off between speed performance and processor fault tolerance.

Hamilton, D. L.↗
NASA NTRS1979

Implementing a bubble memory hierarchy system

This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

Segura, R.↗
DOE OSTI2026

Magnon confinement in epitaxial antiferromagnetic oxide heterostructures.

Magnons, the quanta of spin waves, have been extensively studied in a range of materials for spintronics, particularly for non-volatile logic-in-memory devices. Controlling magnons in conventional antiferromagnets and harnessing them in practical applications, however, remains a challenge. Here, we demonstrate highly efficient magnon transport in a LaFeO3/ BiFeO3/ LaFeO3 all-antiferromagnetic system, which can be controlled electrically, making it highly desirable for energy-efficient computation. Leveraging spin-orbit-driven spin-charge transduction, we demonstrate that this material architecture permits magnon confinement in ultrathin antiferromagnets, enhancing the output voltage generated by magnon transport by several orders of magnitude, which provides a pathway to enable magnetoelectric memory and logic functionalities. Additionally, the non-volatility of output voltage enables ultralowpower logic-in-memory processing, where magnonic devices can be efficiently reconfigured via electrically controlled magnon spin currents within magnetoelectric channels.

Husain, Sajid↗
NASA NTRS1987

Flexible structure control laboratory development and technology demonstration

An experimental structure is described which was constructed to demonstrate and validate recent emerging technologies in the active control and identification of large flexible space structures. The configuration consists of a large, 20 foot diameter antenna-like flexible structure in the horizontal plane with a gimballed central hub, a flexible feed-boom assembly hanging from the hub, and 12 flexible ribs radiating outward. Fourteen electrodynamic force actuators mounted to the hub and to the individual ribs provide the means to excite the structure and exert control forces. Thirty permanently mounted sensors, including optical encoders and analog induction devices provide measurements of structural response at widely distributed points. An experimental remote optical sensor provides sixteen additional sensing channels. A computer samples the sensors, computes the control updates and sends commands to the actuators in real time, while simultaneously displaying selected outputs on a graphics terminal and saving them in memory. Several control experiments were conducted thus far and are documented. These include implementation of distributed parameter system control, model reference adaptive control, and static shape control. These experiments have demonstrated the successful implementation of state-of-the-art control approaches using actual hardware.

Vivian, H. C.↗
NASA NTRS1988

Memory protection

Accidental overwriting of files or of memory regions belonging to other programs, browsing of personal files by superusers, Trojan horses, and viruses are examples of breakdowns in workstations and personal computers that would be significantly reduced by memory protection. Memory protection is the capability of an operating system and supporting hardware to delimit segments of memory, to control whether segments can be read from or written into, and to confine accesses of a program to its segments alone. The absence of memory protection in many operating systems today is the result of a bias toward a narrow definition of performance as maximum instruction-execution rate. A broader definition, including the time to get the job done, makes clear that cost of recovery from memory interference errors reduces expected performance. The mechanisms of memory protection are well understood, powerful, efficient, and elegant. They add to performance in the broad sense without reducing instruction execution rate.

Denning, Peter J.↗
NASA NTRS1993

Programmable DMA controller

In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

Hendry, David F.↗
NASA NTRS1980

Adaptive/learning control of large space structures - System identification techniques

Techniques developed for the control of aircraft under changing operating conditions are used to develop a learning control system structure for a multi-configuration, flexible space vehicle. A configuration identification subsystem that is to be used with a learning algorithm and a memory and control process subsystem is developed. Adaptive gain adjustments can be achieved by this learning approach without prestoring of large blocks of parameter data and without dither signal inputs which will be suppressed during operations for which they are not compatible. The Space Shuttle Solar Electric Propulsion (SEP) experiment is used as a sample problem for the testing of adaptive/learning control system algorithms.

Thau, F. E.↗
DOE OSTI2024

Learning Constrained Parametric Differentiable Predictive Control Policies With Guarantees

We present differentiable predictive control (DPC), a method for offline learning of constrained neural control policies for nonlinear dynamical systems with performance guarantees. We show that the sensitivities of the parametric optimal control problem can be used to obtain direct policy gradients. Specifically, we employ automatic differentiation (AD) to efficiently compute the sensitivities of the model predictive control (MPC) objective function and constraints penalties. To guarantee safety upon deployment, we derive probabilistic guarantees on closed-loop stability and constraint satisfaction based on indicator functions and Hoeffding’s inequality. We empirically demonstrate that the proposed method can learn neural control policies for various parametric optimal control tasks. In particular, we show that the proposed DPC method can stabilize systems with unstable dynamics, track time-varying references, and satisfy nonlinear state and input constraints. Our DPC method has practical time savings compared to alternative approaches for fast and memory-efficient controller design. Specifically, DPC does not depend on a supervisory controller as opposed to approximate MPC based on imitation learning. We demonstrate that, without losing performance, DPC is scalable with greatly reduced demands on memory and computation compared to implicit and explicit MPC while being more sample efficient than model-free reinforcement learning (RL) algorithms.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1985

Optical Mass Memory System Specification

Specifications given for computer controlled optical mass memory system that stores and retrieves data from silver halide fiches 148-mmsquare and 7 mils (0.18mm) thick at user bit density of 30 Mbit/in. 2 (4.7 Mbit/cm2) with uncorrectable bit-error rate of 10 to negative 9th power or less. Allows for expansion to 10 the 15th power bit capacity.

Source record↗
NASA NTRS1990

Primary lithium cell life studies

One solution for providing a truly independent power source is to package, within the critical subsystem element, a primary battery that can remain dormant for time periods as long as the mission life, which can be 10-15 years, maximum. When primary power from the spacecraft solar array/battery system is interrupted, the backup battery system, which is connected through a diode to the power input line, would automatically support the load to avoid a power interruption to the critical load for a time period long enough to ensure that ground control could access the satellite and correct the anomaly by sending appropriate commands to the spacecraft. Critical subsystems identified for the application are telemetry and command circuits, volatile computer memory, attitude control circuits, and some critical payloads. Due to volume packaging and weight restrictions that exist on most spacecraft, coupled with the long storage periods required, lithium cell technology was selected for the backup power source. Because of the high energy density (200-400 Wh/kg), long shelf life, and load capability, soluble cathode primary lithium technology was chosen. The most important lithium cell properties that require detail characterization for this application are capacity loss, shelf life, and the voltage delay mechanism. These are functions of storage time and temperature. During storage, a passive film builds up on the lithium electrode. The film protects the lithium electrode from progressive capacity decay but requires time to break down when a load is applied. This phenomenon results in a depressed voltage during the period of film breakdown which can last from fractions of a second to minutes.

Capulli, John↗
DOE OSTI2024

The ECP SICM project: Managing complex memory hierarchies for exascale applications

The Exascale Computing Project (ECP)’s Simplified Interface to Complex Memories (SICM) effort focuses on developing universal interfaces for discovering, managing, and sharing data across complex memory hierarchies. These facilitate the exploitation of emerging memory technologies and support precise control over their various trade-offs such as high-bandwidth versus low-latency, persistent versus ephemeral, high-capacity versus low-capacity, and near-CPU versus near-GPU. SICM comprises three interrelated components: a low-level interface, a high-level interface, and a persistent-heap interface. The low-level SICM interface is intended for system and run-time developers as well as expert application developers who prefer full control of the memory objects used within their application. The high-level SICM interface builds upon the low-level interface, employing application-level profiling and analysis to optimize data management for complex memory hierarchies. The persistent-heap interface provides applications with a persistent memory allocator that can allocate custom C++ data structures in both block-storage and byte-addressable persistent memories.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Computational processor-in-memory with enhanced strided memory access

A computational memory for a computer. The memory includes a memory bank having a selected-row buffer and being configured to store records up to a number, K. The memory also includes an accumulator connected to the memory bank, the accumulator configured to store up to K records. The memory also includes an arithmetic and logic unit (ALU) connected to the accumulator and to the selected row buffer of the memory bank, the ALU having an indirect network of 2K ports for reading and writing records in the memory bank and the accumulator, and the ALU further physically configured to operate as a sorting network. The memory also includes a controller connected to the memory bank, the ALU, and the accumulator, the controller being hardware configured to direct operation of the ALU.

DeBenedictis, Erik↗
NASA NTRS1973

Development and flight test of a digital fly-by-wire F8.

The objective of the F-8 digital fly-by-wire program is to establish a technology base for the implementation of advanced flight control systems. The central element is the Apollo Lunar Guidance Computer (LGC). This versatile computer ran over 2000 hours in support of fly-by-wire without a failure. Difficulties encountered in the first flights were corrected rapidly and simply by changes in the erasable software memory. Control-configured vehicles offer significant weight-saving possibilities.

Peterson, B. A.↗
NASA NTRS2005

System-Level Design of a Shape Memory Alloy Actuator for Active Clearance Control in the High-Pressure Turbine

This paper describes results of a numerical analysis evaluating the feasibility of high-temperature shape memory alloys (HTSMA) for active clearance control actuation in the high-pressure turbine section of a modern turbofan engine. The prototype actuator concept considered here consists of parallel HTSMA wires attached to the shroud that is located on the exterior of the turbine case. A transient model of an HTSMA actuator was used to evaluate active clearance control at various operating points in a test bed aircraft engine simulation. For the engine under consideration, each actuator must be designed to counteract loads from 380 to 2000 lbf and displace at least 0.033 inches. Design results show that an actuator comprised of 10 wires 2 inches in length is adequate for control at critical engine operating points and still exhibits acceptable failsafe operability and cycle life. A proportional-integral-derivative (PID) controller with integrator windup protection was implemented to control clearance amidst engine transients during a normal mission. Simulation results show that the control system exhibits minimal variability in clearance control performance across the operating envelope. The final actuator design is sufficiently small to fit within the limited space outside the high-pressure turbine case and is shown to consume only small amounts of bleed air to adequately regulate temperature.

DeCastro, Jonathan A.↗
NASA NTRS2006

Surface Control of Cold Hibernated Elastic Memory Self-Deployable Structure

A new class of simple, reliable, lightweight, low packaging volume and cost, self-deployable structures has been developed for use in space and commercial applications. This technology called 'cold hibernated elastic memory' (CHEM) utilizes shape memory polymers (SMP)in open cellular (foam) structure or sandwich structures made of shape memory polymer foam cores and polymeric composite skins. Some of many potential CHEM space applications require a high precision deployment and surface accuracy during operation. However, a CHEM structure could be slightly distorted by the thermo-mechanical processing as well as by thermal space environment Therefore, the sensor system is desirable to monitor and correct the potential surface imperfection. During these studies, the surface control of CHEM smart structures was demonstrated using a Macro-Fiber Composite (MFC) actuator developed by the NASA LaRC and US Army ARL. The test results indicate that the MFC actuator performed well before and after processing cycles. It reduced some residue compressive strain that in turn corrected very small shape distortion after each processing cycle. The integrated precision strain gages were detecting only a small flat shape imperfection indicating a good recoverability of original shape of the CHEM test structure.

glass transition temperature Tg↗
NASA NTRS2003

SpaceWire Driver Software for Special DSPs

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Clark, Douglas↗