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NASA NTRS1988

Storage and computationally efficient permutations of factorized covariance and square-root information matrices

A unified method to permute vector-stored upper-triangular diagonal factorized covariance (UD) and vector stored upper-triangular square-root information filter (SRIF) arrays is presented. The method involves cyclical permutation of the rows and columns of the arrays and retriangularization with appropriate square-root-free fast Givens rotations or elementary slow Givens reflections. A minimal amount of computation is performed and only one scratch vector of size N is required, where N is the column dimension of the arrays. To make the method efficient for large SRIF arrays on a virtual memory machine, three additional scratch vectors each of size N are used to avoid expensive paging faults. The method discussed is compared with the methods and routines of Bierman's Estimation Subroutine Library (ESL).

Muellerschoen, R. J.↗

NASA NTRS1989

Optical backplane interconnect switch for data processors and computers

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Hendricks, Herbert D.↗

NASA NTRS1972

Feasibility investigation of a cellularly organized data processor

The application of cellular arrays to NASA missions was studied. Cellular arrays are iterative logical and memory structures which can be programmed to accomplish a wide variety of logical tasks. Used in long-duration space missions, spare cellular arrays can be remotely programmed to replace faulty logical subsystems as the need arises.

Minnick, R. C.↗

NASA NTRS2016

System Assessment of a High Power 3-U CubeSat

The Advanced eLectrical Bus (ALBus) CubeSat project is a technology demonstration mission of a 3-UCubeSat with an advanced, digitally controlled electrical power system capability and novel use of Shape Memory Alloy (SMA) technology for reliable deployable solar array mechanisms. The objective of the project is to, through an on orbit demonstration, advance the state of power management and distribution (PMAD) capabilities to enable future missions requiring higher power, flexible and reliable power systems. The goals of the mission include demonstration of: 100 Watt distribution to a target electrical load, efficient battery charging in the orbital environment, flexible power system distribution interfaces, adaptation of power system control on orbit, and reliable deployment of solar arrays and antennas utilizing re-settable SMA mechanisms. The power distribution function of the ALBus PMAD system is unique in the total power to target load capability of 100 W, the flexibility to support centralized or point-to-load regulation and ability to respond to fast transient power requirements. Power will be distributed from batteries at 14.8 V, 6.5 A to provide 100 W of power directly to a load. The deployable solar arrays utilize NASA Glenn Research Center superelastic and activated Nitinol(Nickel-Titanium alloy) Shape Memory Alloy (SMA) technology for hinges and a retention and release mechanism. The deployable solar array hinge design features utilization of the SMA material properties for dual purpose. The hinge uses the shape memory properties of the SMA to provide the spring force to deploy the arrays. The electrical conductivity properties of the SMA also enables the design to provide clean conduits for power transfer from the deployable arrays to the power management system. This eliminates the need for electrical harnesses between the arrays and the PMAD system in the ALBus system design. The uniqueness of the SMA retention and release mechanism design is the ability to reset the mechanism, allowing functional tests of the mechanisms prior to flight with no degradation of performance. The project is currently in preparation at the NASA Glenn Research Center for a launch in late calendar year of 2017. The 100 Watt power distribution and dual purpose, re-settable SMA mechanisms introduced several system level challenges due to the physical constraints in volume, mass and surface area of 3-U CubeSats. Several trade studies and design cycles have been completed to develop a system which supports the project objectives. This paper is a report on the results of the system level trade studies and assessments. The results include assessment of options for thermal control of 100 Watts of power dissipation, data from system analyses and engineering development tests, limitations of the 3-U system and extensibility to larger scale CubeSat missions.

CubeSat↗

NASA NTRSDate not supplied

Parallelized Convolutional Interleaver Implementation for Efficient DDR Memory Access

Convolutional interleavers are used in many different communications systems to correct for burst errors due to atmospheric fades and scintillation. The interleaver size is related to the channel coherence time and the data rate. Small convolutional interleavers can be implemented in a field programmable gate array (FPGA) block random access memory (BRAM). However, large interleavers exceeding the size of the BRAM on the FPGA are necessary for channels with longer fades and higher data rates. Therefore, an implementation utilizing double data rate (DDR) memory external to the FPGA is necessary. Wide DDR memory data buses can make the use of DDR memory for convolutional interleavers inefficient when individual symbols are written to and read from the memory. DDR memory operational speeds can also limit the data rate of the interleaver. The Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency (HPE) standard utilizes a convolutional channel symbol interleaver. A previous implementation of the HPE standard utilized BRAM for the convolutional interleaver, but mission requirements for the upcoming Optical Artemis-2 Orion (O2O) communications demonstration dictate the use of an interleaver exceeding the size of the BRAM. An algorithm and method for implementing the convolutional interleaver in the FPGA with DDR memory is described in this paper.

optical communications↗

NASA NTRSDate not supplied

Parallelized convolutional interleaver implementation for efficient DDR memory access

Optical communications↗

NASA NTRS1996

High-performance ultra-low power VLSI analog processor for data compression

An apparatus for data compression employing a parallel analog processor. The apparatus includes an array of processor cells with N columns and M rows wherein the processor cells have an input device, memory device, and processor device. The input device is used for inputting a series of input vectors. Each input vector is simultaneously input into each column of the array of processor cells in a pre-determined sequential order. An input vector is made up of M components, ones of which are input into ones of M processor cells making up a column of the array. The memory device is used for providing ones of M components of a codebook vector to ones of the processor cells making up a column of the array. A different codebook vector is provided to each of the N columns of the array. The processor device is used for simultaneously comparing the components of each input vector to corresponding components of each codebook vector, and for outputting a signal representative of the closeness between the compared vector components. A combination device is used to combine the signal output from each processor cell in each column of the array and to output a combined signal. A closeness determination device is then used for determining which codebook vector is closest to an input vector from the combined signals, and for outputting a codebook vector index indicating which of the N codebook vectors was the closest to each input vector input into the array.

Tawel, Raoul↗

NASA NTRS1994

High-performance, flexible, deployable array development for space applications

Flexible, deployable arrays are an attractive alternative to conventional solar arrays for near-term and future space power applications, particularly due to their potential for high specific power and low storage volume. Combined with low-cost flexible thin-film photovoltaics, these arrays have the potential to become an enabling or an enhancing technology for many missions. In order to expedite the acceptance of thin-film photovoltaics for space applications, however, parallel development of flexible photovoltaics and the corresponding deployable structure is essential. Many innovative technologies must be incorporated in these arrays to ensure a significant performance increase over conventional technologies. For example, innovative mechanisms which employ shape memory alloys for storage latches, deployment mechanisms, and array positioning gimbals can be incorporated into flexible array design with significant improvement in the areas of cost, weight, and reliability. This paper discusses recent activities at Martin Marietta regarding the development of flexible, deployable solar array technology. Particular emphasis is placed on the novel use of shape memory alloys for lightweight deployment elements to improve the overall specific power of the array. Array performance projections with flexible thin-film copper-indium-diselenide (CIS) are presented, and government-sponsored solar array programs recently initiated at Martin Marietta through NASA and Air Force Phillips Laboratory are discussed.

Gehling, Russell N.↗

NASA NTRS1977

Bridge/amplifier configuration for switched arrays

Bridge network connected to differential amplifier and used with bubble-domain memories draws no power during standby and can be arrayed with other bridge amplifiers of like design. Two-node arrangement greatly simplifies conventional configurations where more than two nodes are involved.

Bohning, O. D.↗

NASA NTRS1995

Solid-state image sensor with focal-plane digital photon-counting pixel array

A photosensitive layer such as a-Si for a UV/visible wavelength band is provided for low light level imaging with at least a separate CMOS amplifier directly connected to each PIN photodetector diode to provide a focal-plane array of NxN pixels, and preferably a separate photon-counting CMOS circuit directly connected to each CMOS amplifier, although one row of counters may be time shared for reading out the photon flux rate of each diode in the array, together with a buffer memory for storing all rows of the NxN image frame before transfer to suitable storage. All CMOS circuitry is preferably fabricated in the same silicon layer as the PIN photodetector diode for a monolithic structure, but when the wavelength band of interest requires photosensitive material different from silicon, the focal-plane array may be fabricated separately on a different semiconductor layer bump-bonded or otherwise bonded for a virtually monolithic structure with one free terminal of each diode directly connected to the input terminal of its CMOS amplifier and digital counter for integration of the photon flux rate at each photodetector of the array.

Fossum, Eric R.↗

NASA NTRS1990

Execution time supports for adaptive scientific algorithms on distributed memory machines

Optimizations are considered that are required for efficient execution of code segments that consists of loops over distributed data structures. The PARTI (Parallel Automated Runtime Toolkit at ICASE) execution time primitives are designed to carry out these optimizations and can be used to implement a wide range of scientific algorithms on distributed memory machines. These primitives allow the user to control array mappings in a way that gives an appearance of shared memory. Computations can be based on a global index set. Primitives are used to carry out gather and scatter operations on distributed arrays. Communications patterns are derived at runtime, and the appropriate send and receive messages are automatically generated.

Berryman, Harry↗

NASA NTRS1990

Execution time support for scientific programs on distributed memory machines

Berryman, Harry↗

NASA NTRS1993

Automatic array alignment in data-parallel programs

FORTRAN 90 and other data-parallel languages express parallelism in the form of operations on data aggregates such as arrays. Misalignment of the operands of an array operation can reduce program performance on a distributed-memory parallel machine by requiring nonlocal data accesses. Determining array alignments that reduce communication is therefore a key issue in compiling such languages. We present a framework for the automatic determination of array alignments in array-based, data-parallel languages. Our language model handles array sectioning, reductions, spreads, transpositions, and masked operations. We decompose alignment functions into three constituents: axis, stride, and offset. For each of these subproblems, we show how to solve the alignment problem for a basic block of code, possibly containing common subexpressions. Alignments are generated for all array objects in the code, both named program variables and intermediate results. We assign computation to processors by virtue of explicit alignment of all temporaries; the resulting work assignment is in general better than that provided by the 'owner-computes' rule. Finally, we present some ideas for dealing with control flow, replication, and dynamic alignments that depend on loop induction variables.

Chatterjee, Siddhartha↗

NASA NTRS1992

Optimal evaluation of array expressions on massively parallel machines

We investigate the problem of evaluating FORTRAN 90 style array expressions on massively parallel distributed-memory machines. On such machines, an elementwise operation can be performed in constant time for arrays whose corresponding elements are in the same processor. If the arrays are not aligned in this manner, the cost of aligning them is part of the cost of evaluating the expression. The choice of where to perform the operation then affects this cost. We present algorithms based on dynamic programming to solve this problem efficiently for a wide variety of interconnection schemes, including multidimensional grids and rings, hypercubes, and fat-trees. We also consider expressions containing operations that change the shape of the arrays, and show that our approach extends naturally to handle this case.

Chatterjee, Siddhartha↗

NASA NTRS2011

CoNNeCT Baseband Processor Module

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Yamamoto, Clifford K↗

NASA NTRS1994

Non-volatile magnetic random access memory

Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

Katti, Romney R.↗

NASA NTRS1972

LSI computer fabrication - SUMC/DV.

The SUMC/DV (Space Ultrareliable Modular Computer Demonstration Vehicle), which required the design and fabrication of ten different array types, was designed, partitioned, assembled, tested, and made completely operational in less than one year. This paper describes the assembly, the physical and electrical characteristics, and the basic electrical testing procedures used on SUMC/DV. The paper includes a description of the packaging concepts, the physical assembly, the fabrication and testing of the various components including the LSI/CMOS arrays, the hierarchy of the memory complement, the clock generation and distribution scheme, additional system testing techniques, and the procedure employed in the electrical checkout of the system.

Feller, A.↗

NASA NTRS1981

A computer controlled television detector for light, X-rays and particles

A versatile, high resolution, software configurable, two-dimensional intensified vidicon quantum detector system has been developed for multiple research applications. A thin phosphor convertor allows the detection of X-rays below 20 keV and non-relativistic particles in addition to visible light, and a thicker scintillator can be used to detect X-rays up to 100 keV and relativistic particles. Faceplates may be changed to allow any active area from 1 to 40 mm square, and active areas up to 200 mm square are possible. The image is integrated in a digital memory on any software specified array size up to 4000 x 4000. The array size is selected to match the spatial resolution, which ranges from 10 to 100 microns depending on the operating mode, the active area, and the photon or particle energy. All scan and data acquisition parameters are under software control to allow optimal data collection for each application.

Kalata, K.↗