Characterization of Soft Error Rate Against Memory Elements Spacing and Clock Skew in a Logic with Triple Modular Redundancy in a 65nm Process
Single Event Effects introduce soft errors in ASICs. Design methodologies like Triple ModularRedundancy (TMR) with clock skew insertion, a system level redundancy technique is a commonpractice by designers to mitigate soft errors. However, the optimal spacing between memoryelements in a TMR in 65nm process hasn't been addressed so far. RD53SEU is a mini ASICdevelopment under the framework of the CERN RD53 collaboration to characterize the soft errorrates against the separation spacing and clock skew between memory elements in a TMR. Thisarticle describes the architecture and design aspects of the various test structures on the RD53SEUtest chip.