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At least 91 records · Page 5

Digital tracking loops for a programmable digital modem

In this paper, an analysis and hardware emulation of the tracking loops for a very flexible programmable digital modem (PDM) will be presented. The modem is capable of being programmed for 2, 4, 8, 16-PSK, 16-QAM, MSK, and Offset-QPSK modulation schemes over a range of data rates from 2.34 to 300 Mbps with programmable spectral occupancy from 1.2 to 1.8 times the symbol rate; these operational parameters are executable in burst or continuous mode. All of the critical processing in both the modulator and demodulator is done at baseband with very high-speed digital hardware and memory. Quadrature analog front-ends are used for translation between baseband and the IF center frequency. The modulator is based on a table lookup approach, where precomputed samples are stored in memory and clocked out according to the incoming data pattern. The sample values are predistorted to counteract the effects of the other filtering functions in the link as well as any transmission impairments. The demodulator architecture was adapted from a joint estimator-detector (JED) mathematical analysis. Its structure is applicable to most signalling formats that can be represented in a two-dimensional space. The JED realization uses interdependent, mutually aiding tracking loops with post-detection data feedback. To expedite and provide for more reliable synchronization, initial estimates for these loops are computed in a parallel acquisition processor. The cornerstone of the demodulator realization is the pre-averager received data filter which allows operation over a broad range of data rates without any hardware changes and greatly simplifies the implementation complexity. The emulation results confirmed tracking loop operation over the entire range of operational parameters listed above, as well as the capability of achieving and maintaining synchronization at BER's in excess of 10(exp -1). The emulation results also showed very close agreement with the tracking loop analysis, and validated the resolution apportionment of the various hardware elements in the tracking loops.

Poklemba, John J.↗

Application of multirate digital filter banks to wideband all-digital phase-locked loops design

A new class of architecture for all-digital phase-locked loops (DPLL's) is presented in this article. These architectures, referred to as parallel DPLL (PDPLL), employ multirate digital filter banks (DFB's) to track signals with a lower processing rate than the Nyquist rate, without reducing the input (Nyquist) bandwidth. The PDPLL basically trades complexity for hardware-processing speed by introducing parallel processing in the receiver. It is demonstrated here that the DPLL performance is identical to that of a PDPLL for both steady-state and transient behavior. A test signal with a time-varying Doppler characteristic is used to compare the performance of both the DPLL and the PDPLL.

Sadr, Ramin↗

Critical Knowledge Gaps in Mass Transport through Single-Digit Nanopores: A Review and Perspective

Not all nanopores are created equal. By definition, nanopores have characteristic diameters or conduit widths between ~1 and 100 nm. However, the narrowest of such pores, perhaps best called Single Digit Nanopores (SDNs) and defined as those with regular diameters less than 10 nm, have only recently been accessible experimentally for precision transport measurements. This Review summarizes recent experiments on pores in this size range that yield surprising results, pointing toward extraordinary transport efficiencies and selectivities for SDN systems. These studies have identified critical gaps in our understanding of nanoscale hydrodynamics, molecular sieving, fluidic structure, and thermodynamics. These knowledge gaps are, in turn, an opportunity to discover and understand fundamentally new mechanisms of molecular and ionic transport at the nanometer scale that may inspire a host of new technologies, from novel membranes for separations and water purification to new gas-permeable materials and energy storage devices. Furthermore, we highlight seven critical knowledge gaps in the study of SDNs and identify the need for new approaches to address these topics.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Digital filtering of random digits

Digital simulation of linear filter, investigating noise and rounding errors effects on decoding signals from lunar and interplanetary probes

Jennings, G.↗

Digital hardware and computer system for a digital image recorder.

Description of the digital memory and related computer system used at the Palomar Mountain Observatory. The memory was designed to have a large number of pixels, a high capacity for each pixel, and fast access for use with a variety of image sensors. As an image integration and storage device, this memory is shown to possess ideal properties, namely, it is strictly linear, has a wide dynamic range, and the image does not deteriorate with time. The observer has a visual display which enables him to monitor the image as it is being integrated.-

Dennison, E. W.↗

Digital system identification and its application to digital flight control

On-line system identification of linear discrete systems for implementation in a digital adaptive flight controller is considered by the conventional extended Kalman filter and a decoupling process in which the linear state estimation problem and the linear parameter identification problem are each treated separately and alternately. Input requirements for parameter identifiability are established using the standard conditions of observability for a time variant system. Experimental results for simulated linearized lateral aircraft motion are included along with the effect of different initialization and updating procedures for the priming trajectory used by the filter.

Kotob, S.↗

Digital systems design language. Design synthesis of digital systems

The Digital Systems Design Language (DDL) is implemented on the SEL-32 computer systems. The details of the language, translator and simulator programs are included. Several example descriptions and a tutorial on hardware description languages are provided, to guide the user.

Shiva, S. G.↗