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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

MIND-MAC: Multi-Level In-memory Quasi Non-Destructive MAC Operation in Compact 2T-nC FeRAM for Efficient DNN Accelerator

We present MIND-MAC, a compact 2T-nC FeRAM architecture that performs multi-level, quasi-non-destructive in-memory multiply–accumulate (MAC) for deep neural networks. By exploiting voltage-controlled partial domain switching in MFM capacitors and read-transistor amplification, the cell stores multi-bit weights and gates bit-serial inputs to produce an accumulated current on shared lines. We combine TCAD-extracted parasitics with experimentally calibrated ferroelectric models in SPICE to validate device-/circuit-level behavior, and validate multi-level sensing and QNRO with measurements on a fabricated 2T-3C test vehicle. An analytical system model maps MIND-MAC to a 6-GB main-memory in-memory compute (IMC) architecture and benchmarks VGG13 inference in 61.08 ms at 964.99 mJ. Results indicate high density, reduced rewrite overhead, and energy efficiency, positioning 2T-nC FeRAM as a promising IMC candidate for next-generation AI hardware.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Content-aware foveated camera for multi-target tracking

Modern image sensors deliver substantial space-time bandwidth, yet indiscriminate acquisition often overwhelms memory, computation, and downstream perception. We present a content-aware, multi-foveated camera that dynamically reallocates sensing and magnification to multiple regions of interest (ROIs). A phase-only spatial light modulator (SLM) serves as a solid-state, inertia-free beam-steering and lens element, enabling per-frame field-of-view (FOV) reconfiguration and content-aware target tracking. By interleaving frames across foveae, our system preserves a wide-FOV situational context while refreshing each ROI at high rates, thereby reducing data volume without degrading task performance. We constructed a prototype employing a single-SLM, single-sensor architecture and demonstrated its application in real-time multi-object tracking with dynamic ROI maintenance across multiple viewpoints. The approach offers a general pathway to integrate detection, tracking, and segmentation algorithms in the acquisition loop, shifting workload from post hoc processing to intelligent capture.

Zang, Zihan [Univ. of California, Los Angeles, CA ↗
DOE OSTI2023

Disorder, interactions, and their interplay in novel narrow-gap Dirac materials and Weyl semimetals

Progress of the modern day condensed matter physics is to a large extent driven by the synthesis of new materials, advances in their experimental characterization and theoretical description. Recent discoveries of novel gapless Weyl semimetals, such as NaBi,CdAs, and BiTe-based films, in which magnetic dopants essentially suppress the gap, have added to the family of graphene and topological insulators actively investigated over the past decade. With the field of novel semimetals rapidly maturing, its focus necessarily shifts from demonstrations of the feasibility of such materials to their quantitative characterization. While the transport and optical properties of graphene and topological insulators are well captured within the picture of free non-interacting electrons, gapless 3D Weyl semimetals and narrow-gap 2D semiconductors with Dirac spectrum are known to be extremely susceptible to disorder and electron-electron interactions. This susceptibility obscures the manifestations of nontrivial band structure -- like quantum anomalous Hall effect -- of the new topological materials. Among particular projects to be addressed are: 1) optical conductivity of 3D gapless Dirac fermions in the presence of smooth disorder, 2) interplay of disorder and Coulomb interactions in the spectral properties of such fermions, 3) formation and structure of the impurity band with Coulomb supercritical clusters, 4) Coulomb interaction-driven renormalization of the electron spectrum and of the transport response in the presence of strong magnetic field, 5) instanton approach to the disorder-induced fluctuation states in zero-gap 3D materials, and 6) the role of disorder in quantum anomalous Hall effect. The proposal relies upon the investigators' previous broad expertise in interacting and disordered electron systems. The methods to be employed include perturbative diagrammatic technique, non-perturbative instanton and self-consistent approximations, hydrodynamics of electron liquid. Both analytical as well as numerical approaches are to be employed. The anticipated broader outcome of the proposal includes gaining an in-depth understanding of the interplay of the disorder and interactions under the conditions when this interplay has the most dramatic impact on observables. Traditionally, interaction effects are among the most challenging and interesting problems of condensed matter physics. Similarly, disordered systems typically present very difficult but extremely rich problems in the description of various materials. Importantly, understanding the spectral and transport properties of such materials not only presents the fundamental objective, but is also of particular interest for many applications, such as computation, memory, optics, plasmonics. In particular realization of the quantum anomalous Hall effect may lead to the development of low-power-consumption electronics. Indeed, a major constraint for practical use of the quantum Hall effect is limited by the requirement of the quantizing magnetic field. At the same time, the quantum anomalous Hall effect samples exhibit non-dissipative edge quantum transport in a zero magnetic field.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Electron Quantum Dynamics in Strong-Field Irradiation

The major goal of the project was to investigate the nonsequential ionization dynamics of atomic systems with two active electrons under intense laser irradiation. In order to gain insights into such nonlinear dynamical systems, one must resort to clever numerical methods due to the poor scaling of computational memory and time. Accordingly, we have extended the virtual detector method of Feuerstein and Thumm by incorporating quasi-classical “virtual” particles that evolve alongside the Schrödinger wavefunction. A major and recent part of this research effort was to further extend the virtual-detector method to model a two-active-electron atomic system.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2020

Continuous Test and Transition Infrastructure for Quantum Networking for Science Complex

We propose a network architecture with a separate quantum dataplane and a conventional control plane: (a) Quantum Data Plane: The Quantum Data plane consists of links of dark fibers connecting quantum switches and repeaters, which in turn, connect to quantum computers, memory and sensors. Since the current reach is limited to local areas, it will begin as a collection of site networks at laboratories, (b) Conventional Control Plane: The Control plane provides management access to quantum devices for configuration and provisioning via control nodes with firewall and encryption capabilities. Continuous Test and Transition Infrastructure: We propose an infrastructure with a control plane connecting multiple sites via encrypted tunnels over conventional networks consisting of the following: (a) Site Quantum Networks: Individual site networks supported by their fiber plants connect laboratories that house and connect to their quantum devices for testing and interoperability.(b) Site Control Planes: Sites are connected over individual control planes with control hosts with Software Defined Networking capabilities, which can be peered with other networks via ESnet.(c) Progressive Expansion: Initially, sites will develop individual data planes with their specific quantum devices and fiber connections, and mechanisms to interface with conventional networks. They progressively expand and interconnect, under a wide-area ecosystem of peered control planes for device testing, interoperability development and roll off into production environments.

Rao, Nageswara S.↗
DOE OSTI2021

An Analysis of System Balance and Architectural Trends Based on Top500 Supercomputers

Supercomputer design is a complex, multi-dimensional optimization process, wherein several subsystems need to be reconciled to meet a desired figure of merit performance for a portfolio of applications and a budget constraint. However, overall, the HPC community has been gravitating towards ever more Flops, at the expense of many other subsystems. To draw attention to overall system balance, in this paper, we analyze balance ratios and architectural trends in the world’s most powerful supercomputers. Specifically, we have collected the performance characteristics of systems between 1993 and 2019 based on the Top500 lists and then analyzed their architectures from diverse system design perspectives. Notably, our analysis studies the performance balance of the machines, across a variety of subsystems such as compute, memory, I/O, interconnect, intra-node connectivity and power. Our analysis reveals that balance ratios of the various subsystems need to be considered carefully alongside the application workload portfolio to provision the subsystem capacity and bandwidth specifications, which can help achieve optimal performance.

Khan, Awais↗
DOE OSTI2022

Techniques for storing data to enhance recovery and detection of data corruption errors

Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Mills, Peter↗
DOE OSTI2023

Techniques for storing data to enhance recovery and detection of data corruption errors

Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Mills, Peter↗
DOE OSTI2024

Harnessing ML Privacy by Design Through Crossbar Array Non-idealities

Deep Neural Networks (DNNs), handling computeand data-intensive tasks, often utilize accelerators like Resistiveswitching Random-access Memory (RRAM) crossbar for energyefficient in-memory computation. Despite RRAM’s inherent nonidealities causing deviations in DNN output, this study transforms the weakness into strength. By leveraging RRAM non-idealities, the research enhances privacy protection against Membership Inference Attacks (MIAs), which reveal private information from training data. RRAM non-idealities disrupt MIA features, increasing model robustness and revealing a privacy-accuracy tradeoff. Empirical results with four MIAs and DNNs trained on different datasets demonstrate significant privacy leakage reduction with a minor accuracy drop (e.g., up to 2.8% for ResNet-18 with CIFAR-100).

artificial intelligence↗
DOE OSTI2025

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling ( XY/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using technology computer-aided design (TCAD) and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node (FN) dynamics, which together dictate sense margin (SM) and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the SM from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T-nC suffers more from charge sharing with the bitline (BL), while 2T-nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T-nC and 2T-nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.

1T-nC↗
DOE OSTI2025

Flexible and Effective Object Tiering for Heterogeneous Memory Systems

Computing platforms that package multiple types of memory, each with their own performance characteristics, are quickly becoming mainstream. To operate efficiently, heterogeneous memory architectures require new data management solutions that are able to match the needs of each application with an appropriate type of memory. As the primary generators of memory usage, applications create a great deal of information that can be useful for guiding memory management, but the community still lacks tools to collect, organize, and leverage this information effectively. To address this gap, this work introduces a novel software framework that collects and analyzes object-level information to guide memory tiering. The framework includes tools to monitor the capacity and usage of individual data objects, routines that aggregate and convert this information into tier recommendations for the host platform, and mechanisms to enforce these recommendations according to user-selected policies. Moreover, the developed tools and techniques are fully automatic, work on standard Linux systems, and do not require modification or recompilation of existing software. Using this framework, this study evaluates and compares the impact of a variety of design choices for memory tiering, including different policies for prioritizing objects for the fast memory tier as well as the frequency and timing of migration events. In conclusion, the results, collected on a modern Intel platform with conventional DDR4 SDRAM as well as Intel Optane NVRAM, show that guiding data tiering with object-level information can enable significant performance and efficiency benefits compared with standard hardware- and software-directed data-tiering strategies for a diverse set of memory-intensive workloads.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Bit error protection in cache memories

A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

Kalamatianos, John↗
DOE OSTI2025

Ultra-Fast Non-Volatile Resistive Switching Devices with Over 512 Distinct and Stable Levels for Memory and Neuromorphic Computing

Low-current multilevel programmability with inherent non-volatility and high stability of resistance states is required for both multi-bit memory storage and deep learning accelerators but is difficult to achieve. Here, in a resistive switching system, this work realizes >512 (>9 bits) distinct non-volatile conductance levels with stable retention for each state with current levels down to the nanoampere range, highly promising for potential integration with small processing nodes with ultra-low power consumption requirements. This is achieved by demonstrating a new thin film design concept that encompasses three key features: an ultra-thin epitaxial oxygen ionic switching layer that provides a tunable energy barrier at the bottom electrode, an overcoat amorphous layer that acts as an ion migration barrier for stable state retention, and a partial conductive filament as a localized electronic transport channel to the epitaxial switching layer. A large dynamic resistance range of up to seven orders of magnitude is achieved with reset-free transitions among intermediate states, and programmability is demonstrated with ultra-fast (20 ns) pulses. Artificial neural network (ANN) simulations, based on the experimental performance and its non-idealities, demonstrate close-to-ideal inference accuracies for various Modified National Institute of Standards and Technology (MNIST) data sets.

36 MATERIALS SCIENCE↗
DOE OSTI2023

IRIS-DMEM: Efficient Memory Management for Heterogeneous Computing

This paper proposes an efficient data memory management approach for the Intelligent RuntIme System (IRIS) heterogeneous computing framework along with new data transfer policies. IRIS provides a task-based programming model for extreme heterogeneous computing (e.g., CPU, GPU, DSP, FPGA) with support for today's most important programming languages (e.g., OpenMP, OpenCL, CUDA, HIP, OpenACC). However, the IRIS framework either forces the programmer to introduce data transfer commands for each task or relies on suboptimal memory management for automatic and transparent data transfers. The work described here extends IRIS with novel heterogeneous memory handling and introduces novel data transfer policies by employing the Distributed data MEMory handler (DMEM) for efficient and optimal movement of data among the various computing resources. The proposed approach achieves performance gains of up to 7× for tiled LU factorization and tiled DGEMM (i.e., matrix multiplication) benchmarks. Moreover, this approach also reduces data transfers by up to 71% when compared to previous IRIS heterogeneous memory management handlers. This work compares the performance results of the IRIS framework's novel DMEM with the StarPU runtime and MAGMA math library for GPUs. Experiments show a performance gain of up to 1.95× over StarPU and 2.1× over MAGMA.

Miniskar, Narasinga Rao↗
DOE OSTI2023

Flexible and Effective Object Tiering for Heterogeneous Memory Systems

Computing platforms that package multiple types of memory, each with their own performance characteristics, are quickly becoming mainstream. To operate efficiently, heterogeneous memory architectures require new data management solutions that are able to match the needs of each application with an appropriate type of memory. As the primary generators of memory usage, applications create a great deal of information that can be useful for guiding memory tiering, but the community still lacks tools to collect, organize, and leverage this information effectively. To address this gap, this work introduces a novel software framework that collects and analyzes object-level information to guide memory tiering. Using this framework, this study evaluates and compares the impact of a variety of data tiering choices, including how the system prioritizes objects for faster memory as well as the frequency and timing of migration events. The results, collected on a modern Intel platform with conventional DRAM as well as non-volatile RAM, show that guiding data tiering with object-level information can enable significant performance and efficiency benefits compared to standard hardware- and software-directed data tiering strategies.

Kammerdiener, Brandon↗
DOE OSTI2024

Zoned namespaces for computing device main memory

Disclosed in some examples are methods, systems, memory devices, memory controllers, and machine-readable mediums which provide for reserving physical memory device resources to specific execution units. Execution units may include processes, threads, virtual machines, functions, procedures, or the like. Physical memory device resources may include channels, modules, ranks, banks, bank groups, and the like. For example, a physical memory device resource that is reservable may be a smallest unit that allows for parallel access with another of the same size unit.

Sheridan, Patrick Michael↗