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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Grid Forming Inverter With Increased Short-Circuit Contribution to Address Inverter-Based Microgrid Protection Challenges

Substantial differences in fault levels between grid-tied and islanded modes is one of the primary challenges of microgrid protection. During grid-tied mode, the bulk grid provides significant short-circuit, while during islanded operation the short-circuit magnitude is small due to inverter-based resources limiting their current output close to nominal ratings. Consequently, conventional distribution protection strategies based on overcurrent cannot reliably protect microgrids when operating in islanded mode. Fuses and circuit breakers are particularly affected because of their inverse characteristics. Presently, the absence of affordable solutions for protecting microgrids in islanded mode leads to microgrids shutting down during electrical faults. The contribution of this article is two-fold. The first innovation proposes specific hardware modifications to grid-forming inverters to increase their short-circuit current during electrical faults. The second innovation introduces a novel control strategy designed to preserve control stability margins even when the grid-filter saturates, ensuring sinusoidal output currents under normal and fault conditions. Through experimental results, the inverter with the proposed modifications can provide more than three-times its nominal current during electrical faults. For the prototype testbed, this was sufficient to enable the use of traditional legacy overcurrent protection, achieving the fuse-to-relay and relay-to-relay minimum coordination time for the line-to-ground, line-to-line to ground, and three-phase electrical faults.

42 ENGINEERING↗
DOE OSTI2025

ASDF: A Compiler for Qwerty, a Basis-Oriented Quantum Programming Language

Qwerty is a high-level quantum programming language built on bases and functions rather than circuits. This new paradigm introduces new challenges in compilation, namely synthesizing circuits from basis translations and automatically specializing adjoint or predicated forms of functions. This paper presents ASDF, an open-source compiler for Qwerty that answers these challenges in compiling basis-oriented languages. Enabled with a novel high-level quantum IR implemented in the MLIR framework, our compiler produces OpenQASM 3 or QIR for either simulation or execution on hardware. Our compiler is evaluated by comparing the fault-tolerant resource requirements of generated circuits with other compilers, finding that ASDF produces circuits with comparable cost to prior circuit-oriented compilers.

Adams, Austin J [Georgia Tech]↗
DOE OSTI2022

Understanding Power Systems Protection in the Clean Energy Future

Wind and solar power and battery energy storage are often referred to as inverter-based resources (IBRs), which means they rely on power electronics (inverters) to generate grid-compatible electricity. This is unlike the fossil, nuclear, and hydroelectric plants that use spinning synchronous generators that have provided nearly all U.S. electricity until recently. Synchronous generators can inherently provide several services used to maintain a safe and stable grid and as they are replaced with IBRs it becomes important to understand how these services can be provided. One of these services is fault current, or the ability to inject large amounts of current during a short circuit. This current can easily be detected with low-cost equipment such as circuit breakers. IBRs do not inherently produce large amounts of fault current, and this may eventually require finding alternative sources of fault current or new system protection schemes. This document describes several alternative approaches to maintaining fault current protection and provide a safe, reliable power grid.

14 SOLAR ENERGY↗
DOE OSTI2021

DC Circuit Breakers: A Technology Development Status Survey

DC circuit breakers (DCCBs) play a significant role in obtaining the reliability and stability of DC power systems. Selective and fast isolating of faults minimizes the power supply outages to end electricity users and protects the power converters implemented in the DC system. During the last decades, DCCBs have been deeply investigated in industry and academia. There has been impressive progress in terms of efficiency, response time, power-density, lifetime, and electrical operating ratings. Introducing wide bandgap (WBG) devices further has motivated researchers to propose more efficient and novel topologies. This paper provides a point of reference and a background review for DCCBs from novel aspects, fulfilling absent parts in the literature. The elaborated subjects include current commutation circuitry, DCCBs trip-curves developments, newly added functions to DCCBs, as well as marketing analysis. The advancements of DCCBs are surveyed and development needs are recognized. This paper aims to identify the future research needs of DCCBs for emerging DC power systems.

42 ENGINEERING↗
DOE OSTI2024

IBR Short Circuit Modeling in ETAP

Mohammad Zadeh from ETAP presented various modeling improvements that included the following: • Address convergence issues by using complete Norton Equivalent model including the IBR series filter impedance. • Fault ride through identification within iterations while short circuit results have not been converged and how that may impact final SC results. • Options for FRT curve 1- using a timer to lock FRT logic vs a hysteresis in FRT curve to avoid unwanted toggling. • Report recent co-operation between software vendors (Aspen, CAPE and ETAP) for adopting a C++ interface for IBR blackbox SC modeling. There was lot of interest to know about the model improvements that are being considered.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2023

Active Fault Current Limiting Control for Half-Bridge MMC in HVDC Systems

DC faults of MMC can result in a significantly large fault current due to the discharge of submodule capacitors. The fault current not only risks damaging the MMC but also demands a considerable breaking capacity from the dc circuit breaker (DCCBs). This paper introduces two novel active fault current limiting methods (AFCLs), namely virtual impedance-based and energy control-based AFCL. The first method utilizes circulating current feedforward, which introduces a virtual arm impedance to suppress the rate of rise of the fault current. Meanwhile, the second method relies on the control of the internally stored energy of the MMC to automatically minimize the number of submodules that discharge during a dc-side fault. Therefore, both the dc-side current and the MMC arm current can be effectively suppressed after the occurrence of the fault. The proposed methods do not require fault detection and their response is proportional to the rate of rise in the fault current. Simulation case studies are presented to demonstrate the proposed methods.

active current limiting control↗
DOE OSTI2024

Solid state protective smart plug device

A wireless-controlled smart plug device and methods of use and operation, using a solid state switch to provide electrical power from an outlet to a load, and provide protection against overload, short circuit, ground, arc, or voltage surge faults. The switch includes a bidirectional semiconductor switch with two back-to-back connected transistors, such as silicon power MOSFETs, silicon insulated-gate bipolar transistors (IGBTs), silicon carbide (SiC) transistors, or gallium nitride (GaN) transistors, each configured to control the current flow from the electrical receptacle to the external electrical load.

Shen, Zheng↗
DOE OSTI2025

Logical error rates for the surface code under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions

With fault-tolerant quantum computing (FTQC) on the horizon, it is critical to understand sources of logical errors in plausible hardware implementations of quantum error-correcting codes. Detailed error modeling of computational instructions on particular FTQC architectures will enable the better prediction of error propagation in FT-encoded quantum circuits while revealing where greater attention is needed in hardware design. In this work, we consider logical error rates for the surface code implemented on a hypothetical grid-based trapped-ion quantum charge-coupled device architecture. Specifically, we construct logical channels for the idling surface code and examine its diamond error under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions. We include the coherent dephasing noise that is known to accumulate during physical qubit idling and transport in these systems, determining idling and transport durations using the time-resolved output of an open-source trapped-ion surface code compiler. To estimate expectation values of logical Pauli observables following hardware circuits containing non-Clifford sources of noise, we utilize a Monte Carlo technique to sample from an underlying quasiprobability distribution of Clifford circuits that we independently simulate in a phase-sensitive fashion. We verify error suppression up to code distance 𝑑 = 11 at coherent dephasing rates near and below those of current-generation trapped-ion quantum computers and find that logical error rates align with those of analogous fully stochastic simulations in this regime. Exploring higher dephasing rates at 𝑑 = 3−5, we find evidence for growing coherent rotations about all three logical Pauli axes, increased diagonal logical error process matrix elements relative to those of stochastic simulations, and a reduced dephasing rate threshold. Overall, our work paves a way toward realistic hardware emulation of small fault-tolerant quantum processes, e.g., members of an FTQC instruction set.

Quantum benchmarking↗
DOE OSTI2024

Highly-efficient quantum Fourier transformations for certain non-Abelian groups

Quantum Fourier transformations are an essential component of many quantum algorithms, from prime factoring to quantum simulation. While the standard Abelian QFrT is well studied, important variants corresponding to non-Abelian groups of interest have seen less development. In particular, fast non-Abelian Fourier transformations are important components for both quantum simulations of field theories as well as approaches to the non-Abelian hidden subgroup problem. In this work, we present fast quantum Fourier transformations for a number of non-Abelian groups of interest for high energy physics, B T , B O , 6 Δ ( 27 ) , Δ ( 54 ) , and Σ ( 36 × 3 ) . For each group, we derive explicit quantum circuits and estimate resource scaling for fault-tolerant implementations. Our work shows that the development of a fast Fourier transformation can substantively reduce simulation costs by an up to three orders of magnitude for the finite groups that we have investigated.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2022

Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor

Advanced, superscalar microprocessors (μP) are highly susceptible to wear-out failures because of their highly complex, densely packed circuit structure and extreme operational frequencies. Although many types of fault detection and mitigation strategies have been proposed, none have addressed the specific problem of detecting faults that lead to information leakage events on I/O channels of the μP. Information leakage can be defined very generally as any type of output that the executing program did not intend to produce. In this work, we restrict this definition to output that represents a security concern, and in particular, to the leakage of plaintext or encryption keys, and propose a counter-based countermeasure to detect faults that cause this type of leakage event. Fault injection (FI) experiments are carried out on two RISC-V microprocessors emulated as soft cores on a Xilinx multi-processor System-on-chip (MPSoC) FPGA. The μP designs are instrumented with a set of counters that records the number of transitions that occur on internal nodes. The transition counts are collected from all internal nodes under both fault-free and faulty conditions, and are analyzed to determine which counters provide the highest fault coverage and lowest latency for detecting leakage faults. We show that complete coverage of all leakage faults is possible using only a single counter strategically placed within the branch compare logic of the μPs.

42 ENGINEERING↗
DOE OSTI2026

Oxide-nitride heteroepitaxy for low-loss dielectrics in superconducting quantum circuits

Superconducting qubits show great promise for the realization of fault-tolerant quantum computing, but lossy, amorphous dielectrics limit current technology. Identifying highly crystalline and stoichiometric dielectrics with intrinsically low microwave loss is therefore a central materials challenge, yet experimentally validated platforms remain scarce. In this work, we integrate a crystalline dielectric into a heteroepitaxial TiN/$γ$-Al$_2$O$_3$/TiN trilayer grown via pulsed laser deposition. Correlative high-resolution imaging, diffraction, and spectroscopy measurements confirm the single-crystal quality and chemical integrity of all layers, with minimal defects and limited anion interdiffusion across the oxide-nitride interfaces. Using microwave lumped-element resonators with parallel-plate capacitors, we report the first direct measurement of the dielectric loss of epitaxial $γ$-Al$_2$O$_3$, for which we find a low intrinsic two-level system loss, $δ_{\text{TLS}}^0 = (2.8 \pm 0.1) \times 10^{-5}$. These results establish heteroepitaxial oxides on transition metal nitrides as an attractive materials platform for superconducting quantum circuits, particularly for integration into compact device architectures such as merged-element transmons and microwave kinetic inductance detectors.

Garcia-Wetten, David A. [Northwestern U.]↗
DOE OSTI2025

Synthesis of Single Qutrit Circuits from Clifford + R Gates

The Clifford + R gate-set is a promising basis for fault-tolerant synthesis of qutrit unitaries. We present an algorithm for approximating an arbitrary single-qutrit unitary with a circuit over the Clifford + R gates. Moreover, we analyze its complexity and obtain the non-Clifford gates cost.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Fault-Tolerant Operation of Bosonic Qubits with Discrete-Variable Ancillae

Fault-tolerant quantum computation with bosonic qubits often necessitates the use of noisy discrete-variable ancillae. In this work, we establish a comprehensive and practical fault-tolerance framework for such a hybrid system and synthesize it with fault-tolerant protocols by combining bosonic quantum error correction (QEC) and advanced quantum control techniques. We introduce essential building blocks of error-corrected gadgets by leveraging ancilla-assisted bosonic operations using a generalized variant of path-independent quantum control. Using these building blocks, we construct a universal set of error-corrected gadgets that tolerate a single-photon loss and an arbitrary ancilla fault for four-legged cat qubits. Notably, our construction requires only dispersive coupling between bosonic modes and ancillae, as well as beam-splitter coupling between bosonic modes, both of which have been experimentally demonstrated with strong strengths and high accuracy. Moreover, each error-corrected bosonic qubit is comprised of only a single bosonic mode and a three-level ancilla, featuring the hardware efficiency of bosonic QEC in the full fault-tolerant setting. We numerically demonstrate the feasibility of our schemes using current experimental parameters in the circuit-QED platform. Finally, we present a hardware-efficient architecture for fault-tolerant quantum computing by concatenating the four-legged cat qubits with an outer qubit code utilizing only beam-splitter couplings. Our estimates suggest that the overall noise threshold can be reached using existing hardware. These developed fault-tolerant schemes extend beyond their applicability to four-legged cat qubits and can be adapted for other rotation-symmetrical codes, offering a promising avenue toward scalable and robust quantum computation with bosonic qubits. Published by the American Physical Society 2024

Physics↗
DOE OSTI2024

Advanced Sensor Deployment for Distribution System State Estimation and Fault Identification

Distribution systems are currently facing steep operational challenges as a result of the rapidly increasing integration of renewables and other distributed energy resources (DERs) at both the primary and secondary circuit levels. Distribution utilities and system operators have traditionally had some visibility of their primary circuits using low-frequency supervisory control and data acquisition systems, and they have had very poor if not zero visibility of the secondary circuits where the presence of DERs is constantly increasing. Therefore, this paper presents simulation studies to demonstrate the benefits of an advanced, high-fidelity sensor technology, called as the Meta-Alert System (MAS), developed by Electrical Grid Monitoring, Ltd. (EGM), on the distribution grid. First, a reliable model of the EGM sensors is developed, and then two use cases, distribution system state estimation (DSSE) and fault identification are simulated to evaluate the performance of the MAS technology. Simulation results on the Electric Power Research Institute J1 feeder demonstrate that the MAS can effectively participate in system-level DSSE programs and can detect and locate faults faster than traditional distribution protection schemes.

distribution system↗
DOE OSTI2020

Reduced-Order Parameterized Short-Circuit Current Model of Inverter-Interfaced Distributed Generators

The short-circuit response of inverter-interfaced distributed generators (IIDGs) is not adequately represented in many conventional protection studies. This paper presents an in-depth analysis of IIDG behavior during grid faults and proposes a more accurate reduced-order parameterized short-circuit current (RPSC) model of inverters. Typical inverter components are thoroughly investigated to identify those that play dominant roles during faults. The paper shows that the current limiter is the dominant factor for the steady-state fault-current of inverter; while the inverter filter along with the severity of the voltage disturbance largely determine the initial transient spike of inverter fault current. The proposed model is low-order and can be used in large scale simulations. The parameters of the proposed RPSC model can be extracted from laboratory experiments without requiring proprietary manufacturer information. The proposed fault-current model is analogous to the well-known synchronous machine model that segregates the inverter fault current into subtransient, transient, and steady-state fault currents. Finally, experimental and simulation tests are presented to validate the model.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2021

Optimization-Based Formulations for Short-Circuit Studies with Inverter-Interfaced Generation in PowerModelsProtection.jl

Protecting inverter-interfaced microgrids is challenging as conventional time-overcurrent protection becomes unusable due to the lack of fault current. There is a great need for novel protective relaying methods that enable the application of protection coordination on microgrids, thereby allowing for microgrids with larger areas and numbers of loads while not compromising reliable power delivery. Tools for modeling and analyzing such microgrids under fault conditions are necessary in order to help design such protective relaying and operate microgrids in a configuration that can be protected, though there is currently a lack of tools applicable to inverter-interfaced microgrids. This paper introduces the concept of applying an optimization problem formulation to the topic of inverter-interfaced microgrid fault modeling, and discusses how it can be employed both for simulating short-circuits and as a set of constraints for optimal microgrid operation to ensure protective device coordination.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2022

Mitigation of fault related voltage swell on distribution feeders using DER-based advanced inverter controls

Unbalanced faults in distribution feeders can impact voltages on the non-faulted phases. This paper models a real-life feeder with a high penetration level of solar photovoltaic (PV) units in detail including the secondary circuits, and shows a large voltage swell in one of the non-faulted phases of the feeder during a single line to ground fault. The voltages seen during this swell are more than 1.2 p.u., which can have detrimental impacts on the connected equipment and can also lead to loss of connected generation. The reason for this voltage swell is found to be the equivalent impedance at the fault location resulting from the ratio of zero and positive sequence cable impedances. It is seen that the connected solar PV units with appropriate control are able to reduce the severity of the voltage swell, especially for higher penetration levels of solar PV considered, but not entirely eliminate it.

14 SOLAR ENERGY↗